Siemens AP75 Service Manual
12/2005
Release 1.0
Service Repair Documentation
Level 4 (level 2,5e)
M315 / AP75
Release Date Department Notes to change
R 1.0
Technical Documentation
TD_Repair_L4 M315/AP75_R1.0.pdf Page 1 of 42
12.12.2005
BenQ Mobile (Taipei/KLF)
New document
12/2005
Release 1.0
Table of Content
1
Introduction ...............................................................................................................................3
1.1 PURPOSE...............................................................................................................................3
1.2 SCOPE ...................................................................................................................................3
1.3 TERMS AND ABBREVIATIONS ...................................................................................................3
2 List of available level 4 (level 2,5e) parts ...............................................................................4
3 Required Software for Level 4 (level 2,5e) ..............................................................................5
4 Radio Part ..................................................................................................................................6
4.1 RECEIVER OPERATION............................................................................................................6
4.2 TRANSMITTER OPERATION......................................................................................................7
4.3 VCXO OPERATION.................................................................................................................8
4.4 BLUETOOTH OPERATION.........................................................................................................9
5 Logic ( Base-Band ).................................................................................................................10
5.1 CALYPSO-LITE......................................................................................................................12
5.2 IOTA....................................................................................................................................15
5.3 POWER SUPPLY ...................................................................................................................19
5.3.1 System power on/off Sequence ...................................................................................21
5.4 MEMORY CIRCUIT .................................................................................................................22
5.5 LCD MODULE ( LCDM).........................................................................................................24
6 Interfaces .................................................................................................................................27
6.1 AUDIO CIRCUIT .....................................................................................................................27
6.2 MELODY IC...........................................................................................................................29
6.3 AUDIO CIRCUIT .....................................................................................................................31
6.4 10 PINS I/O CONNECTOR......................................................................................................33
6.5 KEYPAD LED CIRCUIT...........................................................................................................35
6.6 VIBRATOR ............................................................................................................................36
6.7 SIM CIRCUIT ........................................................................................................................37
6.8 KEYPAD................................................................................................................................38
6.9 RTC CIRCUIT.......................................................................................................................40
7 Charging circuit.......................................................................................................................41
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1 Introduction
1.1 Purpose
This Service Repair Documentation is intended to carry out repairs on BenQ repair level 3-4.
1.2 Scope
This document is the reference document for all BenQ authorised Service Partners which are
released to repair Siemens mobile phones up to level 2.5.
1.3 Terms and Abbreviations
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2 List of available level 4 (level 2,5e) parts
(according to Component Matrix V1.xx - check C-market for updates)
Product ID Order Number Description CM
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
M315
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Required Equipment for Level 4 (level 2,5e)
GSM-Tester (CMU200 or 4400S incl. Options)
PC-incl. Monitor, Keyboard and Mouse
Adapter cable for Bootadapter (F30032-xx-A1)
Troubleshooting Frame M315_AP75 (F30032-xx-A1)
Power Supply
Spectrum Analyser
Active RF-Probe incl. Power Supply
Oscilloscope incl. Probe
RF-Connector (N<>SMA(f))
Power Supply Cables
Dongle (F30032-xx-A1)
BGA Soldering equipment
Reference: Equipment recommendation V1.6
(downloadable from the technical support page)
3 Required Software for Level 4 (level 2,5e)
Windows XP
XCSD Tools Level 2
GRT Version 3 or higher
Internet unblocking solution (JPICS)
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4 Radio Part
M315 / AP75 utilizes TI’s chipsets (CALYPSO-Lite and IOTA) as base-band solution. Base-band is
composed with two potions: Logic and Analog/Codec. CALYPSO-Lite is a GSM/GPRS digital baseband logic solution included microprocessor, DSP, and peripherals. IOTA is a combination of
analog/codec solution and power management which contain base-band codec, voice-band codec,
several voltage regulators and SIM level shifter etc. In addition, 56E22 integrates with other
features such as LED backlight, color LCD display, DSC, vibration, melody tone and charging etc.
The following sections will present the operation theory with circuitry and descriptions respectively.
4.1 Receiver Operation
RX GSM: 925~960 MHz
T/R
Switch
1805~1880 MHz
1930~1990 MHz
DCS:
PCS:
GSM LNA
0
90
DCS LNA
0
90
PCS LNA
RFVCO
PCS:3860~3980 MHz
DCS:3610~3760 MHz
GSM:3700~3840 MHz
0
90
Shift(1/2)
0
90
Shift(1/2)
2
GSM:
1850~1920 MHz
DCS:
1805~1880 MHz
PCS:
1930~1990 MHz
RF
Synth
ADC/DAC & Control Logic for DC Offset Cancellation
The Receiver structure in HD155155NP is a zero-IF solution. That means RF signal is directly downconverted to the baseband signal. And by the way, all of the DC-offset canceling processes
are done within chip. We do not have to care about that.
The LNA amplifies the RF signal after passing the T/R switch and RF SAW filter and before it enters
the down-converter section. The RF signal is mixed with a local oscillator (LO) signal to generate the
baseband signal.
Three LPFs are used in the baseband signal processing for reducing blocking signals. The first LPF
employs two external capacitors, and we can check whether the front-end (LNA + Mixer) is
functionally well or not by probing these two capacitors to see if there is any baseband
signal(<200kHz).
After three stages of DC-offset cancelling, the signal (I+/I-/Q+/Q-) then output to the baseband IC for
further processing.
IRxP
IRxN
QRxP
QRxN
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4.2 Transmitter Operation
PCS:3860~3980 MHz
DCS:3580~3730 MHz
RFVCO
T/R
Switch
Quad-Band PA
TX GSM: 880~ 915 MHz
DCS:1710~1785 MHz
PCS:1850~1910 MHz
GSM:3840~3980 MHz
GSM
GSM: 960~995 MHz
Charge
Pump
Loop Filter
2
DCS/
PCS
2
PCS:1930~1990 MHz
DCS:1790~1865 MHz
PFD
80/82 MHz
RF
Synth
Shift(1/2)
IF
Synth
0
90
I&Q Mod
IFVCO
640/656 MHz
2
2
ITxP
ITxN
QTxP
QTxN
The transmitter chain converts differential IQ baseband signals to a suitable format for
transmission by a power amplifier.
The common mode voltage range of the modulator inputs is 1.05 V to 1.45 V and they have 2.0 Vpp
differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The
Local signals are generated by dividing the IFLO signals by 8 in GSM band and by 4 in DCS band,
and then passed to the modulator through a phase splitter / shifter. The IF signals generated are
then summed to produce a single modulated IF signal which is amplified and fed into the offset PLL
block.
Within the offset PLL block there are a down converter, a phase comparator and a VCO driver. The
down converter mixes the first local signal and the TXVCO signal to create a reference local signal
for use in the offset PLL circuit. The phase comparator and the VCO driver generate an error
current, which is proportional to the phase differential between the reference IF and the modulated
IF signals. This current is
used in a third order loop filter to generate a voltage, which in turn modulates the TXVCO.
The RF signal is then amplified by PA and power control loop to the assigned power level within the
burst ramping mask. After passing the LPF of the T/R switch, the signal is then radiated through the
antenna.
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4.3 VCXO Operation
+R-R
HD155155NP provides a VCXO function. With that function, we can build a reference clock
generation circuits as shown in the above graph. This means that the VCTCXO module is not
necessary for clock application, and only one crystal with 8ppm tolerance and one variocap are
enough.
The transistor in HD155155NP and two internal capacitors (C1, C2) provide a negative
resistance, and the crystal (X1) combined with some other passive components (including
variocap r : D1) to provide a positive resistance. When these two resistance values equal to each
other at some frequency, the oscillation will happen at that frequency. In our design target, the
oscillation frequency should be within 26MHz +/-15 ppm.
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4.4 Bluetooth Operation
26MHz
B5E-VCXO
VBAT
LDO
2.8V
CLK_S E L
OR
Gate
TCXOEN
2402~2480 MHz
IRDA
UART
B C 3-Handphone
G2-lite
MCSI
SPI Int erface
The Bluetooth main chip – BC3-Handphone deals with BT RF signal from chip antenna and
baseband signal from G2-lite including down/up-converting, de/- modulation and de/- coding … The
BC3-Handphone could accept clock frequency from 8MHz to 40MHz. In our application, we feed the
chip with 26MHz clock from RF chip, HD155155N, and share with G2-lite by an OR-Gate. So GSM
part and BT part could go to sleep respectively. BC3-Handphone could wake G2-lite up by a
interrupt. The BC3-Handphone is controlled by AT commands that come from G2-lite via IRDA
UART. The Data between BC3-Handphone and G2-lite are transmitted and received via MCSI
interface. The SPI interface is reserved for firmware downloading for BT chip of Flash-type. The
power BT chip needed outside is 2.8V the same with voltage level of I/O interface of G2-lite.
INTE RRUPT
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5 Logic ( Base-Band )
Introduction:
56E22 utilizes TI’s chipsets (CALYPSO-Lite and IOTA) as base-band solution. Base-band is
composed with two potions: Logic and Analog/Codec. CALYPSO-Lite is a GSM/GPRS digital
base-band logic solution included microprocessor, DSP, and peripherals. IOTA is a combination
of analog/codec solution and power management which contain base-band codec, voice-band
codec, several voltage regulators and SIM level shifter etc. In addition, 56E30 integrates with
other features such as LED backlight, color LCD display , DSC, vibration, melody tone and
charging etc. The following sections will present the operation theory with circuitry and
descriptions respectively.
Block Diagram CPU CALYPSO (HERCROM40 )
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IOTA
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5.1 Calypso-Lite
CALYPSO-Lite (HERCROM400) is a chip implementing the digital base-band processor of a
GSM/GPRS mobile phone. This chip combines a DSP sub-chip (LEAD2 CPU) with its program
and data memories, a Micro-Controller core with emulation facilities (ARM7TDMIE) and an
internal 2M-bit RAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM
and CMOS gates.
Major functions of this chip are as follows:
Real Time Clock (RTC)
The RTC block is an embedded RTC module fed with an external 32.768KHz Crystal. Its basic
functions are:
1. Time information (seconds/minutes/hours)
2. Calendar information (Day/Month/Year/ Day of the week) up to year 2099
3. Alarm function with interrupts (RTCINT is generated to wake up ABB)
4. 32KHz oscillator frequency gauging
Pulse Width Light (PWL)
This module allows the control of the backlight of LCD and keypad by employing a 4096 bit
random sequence .In the 56E30, we use the LT/PWL function to turn on the keypad light LED.
MODEM-UART
This UART interface is compatible with the NS 16C750 device which is devoted to the
connection to a MODEM through a standard wired interface. The module integrates two 64
words (9 and 11 bits) receive and transmit FIFOs which trigger levels are programmable. All
modem operations are controllable either via a software interface or using hardware flow control
signals. In 56E30 , we implement software flow control by only two signals: TXD0 and RXD0.
General Purposes I/O (GPIO)
Calypso-Lite provides 16 GPIOs configurable in read or write mode by internal registers. In
56E30, we utilize 9 of them as follows , others are used in the dual function mode or N/A:
IO 0 : SPK_FM_HF
IO 1 : VOL_CLK
IO 2 : MELODY_INT
IO 3 : VOL_UpDown
IO 4 : FM_SPK
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IO 5 : X
IO 6 : ACCESSORY_IN
IO 7 : NRESET_OUT
IO 8 :
IO 9 : NLED_DRIVE_SD
IO 10 : FM_EN
IO 11 : FM_SCL
IO 12 : FM_SDA
IO 13 :
IO14: SRAM high-byte enable
IO15: SRAM low-byte enable
Serial Port Interface (SPI)
The SPI is a full-duplex serial port configurable from 1 to 32 bits and provides 3 enable signals
programmable either as positive or negative edge or level sensitive. This interface is working on
13MHz and is used for the GSM/GPRS baseband and voice A/D, D/A with IOTA
Memory Interface and internal Static RAM
For external memory device (Flash and SRAM), this interface performs read and write access
with adaptation to the memory width. It also provides 6 chip-select signals corresponding each
to an address range of 8 mega bytes. One of these chip-select is dedicated to the selection of
an internal memory. In 56E30, we employ nCS0 (NROM_CS0) for external 64 Mbits Flash and
nCS1 (NRAM_CS1) for external 16Mbits SRAM. A 2Mbit SRAM is embedded on the die and
memory mapped on the chip-select nCS6 of the memory interface .The access cycle is
guaranteed with 0 wait-state for any cycle frequency up to 39MHz. About others chip selects
allocation are nCS2 (NDSCM_CS2) for DSC backend IC and nCS3 (NLCDM_CS3) for LCDM
driver and nCS4 for melody IC ..
SIM Interface
The Subscriber Identity Module interface will be fully compliant with the GSM 11.11 and ISO/IEC
7816-3 standards. Its external interface is 3 Volts only. 5 Volts adaptation will be based on
external level shifters.
JTAG
In 56E30, JTAG is used for software debugging.
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