Shuttle G2 12MHz Zero-Wait ’286 User's Manual

G2 12MHz Zero-Wait

’286 Turbo Mainboard

U ser’s Manual

-* 'i

V '

TABLE OF CONTENTS

____________

I . SPECIFICATION
II . G2 AT CHIPSET INTRODUCTION
III. SYSTEM SUPPORT FUNCTION
IV . I/O CHANNEL INTRODUCTION
V. JUMPER SETTING AND CONNECTOR PIN

ASSIGNMENT

VI. HOW TO CONTROL THE SYSTEM SPEED BY

SOFTWARE

.............................

.......................

...........

..............

.............

...........................

2
5

9

1 4

29

34

PAGE 1

I. SPECIFICATION

* Intel or Compatible (AM D , HARRIS) 80286-10,

12 Microprocessor

* System Support Function:

- 7-Channel Direct Memory Access ( D M A)

- 16-Level interrupt

- System clock

- Three programmable timer

* 32KB, 64KB selectable Read-Only Memory

(R O M ) subsystem, expandable to 128K B, fully

compatible with IBM AT BIOS.

* Su p p o r t on b oard 5 1 2 K /64OK/ I M / 2 M/4M

Random-Access Memory (R A M) subsystem, and
expandable to 16MB RAM by added memory card

on slot.
* 12MHz/0 wait state with 100ns DRAM.
* Complementary metal oxide semiconductor

(CMOS) mem ory RAM to maintain system

conf igurat ion.
* Real - Time Clock (RTC).
* Batte ry b ackup for CMOS configu ration

table and Real-Time Clock.
* Keyboard attachment.
* Speaker attachment.
* Support Hardware reset.
* Support Hardware speed change, and Turbo

LED attachment.

PAGE 2

* 5 Input/Output (I/ O) slots with a 36-pin

and a 62-pin card edge socket.

SYSTEM

A ddre ss
0 00 0 00 to

0 7F FF F
0 80 000 to
0 9F FF F

0 A0 0 00 to
0 BF FF F
0 C0 000 to

0 DF FF FF
0 E0 0 00 to
0 EF FF FF
O F 00 00 to

0 FF FF F F

1 00 00 0 to
F DFF FF

F E0 00 0 to
F EFF FF
F F0 00 0 t o
F FFF FF

MEMORY MAP

N ame
5 12kb s ys t em
b oa r d

1 28 kb

1 28 kb vid eo
R AM
1 28 kb I/O
e xp a ns ion RO M

64 kb R es e rv ed

o n sy s te m b oa rd
6 4 kb R OM
o n sy s te m boar d
M aximum
m e mo r y 15Mb

6 4 kb R es e rv ed

o n sy s te m b oa r d
6 4 kb R OM on
t he sy s te m b oa rd

F un ct io n
S ys t em b oa rd m emor y

I/ O ch an nel me mory - IB M Per so na l
C om pu te r AT 1 28 kb M em o ry E xp an si on
O pt i on
R es erve d for gr ap hi cs d i sp la y f uf fe r

R es e rv ed for RO M on I/O a da pt er s

D up li c at ed c od s ass ig nm en t at ad dr es s

F E00 00

D up lica ted co ds as si gn me nt at ad dr es s

F F00 00
I/ O ch an ne l me m or y - IB M Pe rso nal
C om pu ter A T 5 12 kB M emor y Ex pa ns io n
O pt ion
D up li c at ed c od e as si gn men t at ad dr es s 0E 00 00

D up lica ted co de as si gn me nt at
a dd re ss 0F 00 00

PAGE 3

I/O ADDRESS MAP

H EX RA NG E

0 0 0-0 1F D M A co n tr olle r 1 S ys tem
0 20 - 03 F Int e rr up t con trol ler 1 S ys tem
0 4 0-0 5F T i me r S ys tem

0 60-0 6F 8 042 ( Ke yboa rd ) S ys tem
0 70-0 7F Re al t ime cl oc k, NMI m as k S ys tem
0 80-0 9F DMA p ag e regi st er S ys tem
0 A0 -0BF I nt er ru pt con tr o ll er 2 S ys te m
0 C0-0 DF D M A cont roll er 2 S ys tem
0 F0 C lear Ma th Co pr o ce ss o r bu s y S ys tem
0F 1 R es et Math Co pr o ce ss o r Sys tem
0 F8 -0FF M at h Coproc esso r Sys te m
1 F0 -1F8 F i xe d d is k I/ O

2 00-207 G ame I /O I/ O
2 78 - 27 F P ar al le l pri nter po rt 2 I/ O

2 F8 -2FF Ser ial p or t 2 I/ O
3 0 0 -31F P roto t yp e car d I/ O
3 60-3 6F Reser v ed I/ O
3 78 - 37 F Par al l el p ri nt er po rt 1 I/ O
3 80 - 38 F SDLE , b i sy nchr on o us 2 I/ O
3 A0-3 AF B is yn c hr o no u s 1 I/ O
3 B0 - 3B F M onochr o me di s pl a y and pr inte r ad ap te r I /O
3 C0-3 CF Re se r ve d I/ O
3 D0 - 3D F Col or / gr a ph i c mo ni t or a da pt er I/ O
3 F 0-3F7 Flo pp y di sket t e cont ro ll e r I/ O

3 F8 - 3F F Seri al p or t 1 I/ O

______

D EV I CE S

____________________

usage

PAGE 4

II. 62 AT CHIPSet introduction

This mother board use G2 chipset, include a
GC101A and two GC102, to instead most of LSI ,

MSI and SSI logic in standard IBM PC-AT, and

implement a fully IBM PC-AT compatible sys

tem.

The GC101A is a peripheral controller. One of

^ two GC102S is a data buffer, the other is an

address buffer. Following is the introduc
tion of this chipset:

6C101 Peripheral Controller Functional De
scription

The GC101 Peripheral Controller chip, the
heart of a three-chip system, forms most of
the control circuits and "glue" logic of the
AT architecture into a single CMOS VLSI chip.
Circuits embedded in this device include: an
82284, 74612, 8284, 8254, two 8237s, and two
8259s. The 82284 generates PROCCLK, /READY
and /RESET for system use. It also provides
all the CPU I/O command signals for memory,
peripherals, and add-on boards. A 9-bit
refresh counter produces the row address of
memory during refreshes. The 74612 supplies

/Ä' memory mapping addresses. An 8284 uses the

14.318MHz input clock to generate OSC and a
base clock for the 8254 timer/counter. This
timer is programmed by the CPU and provides

signals for system timing, refresh, and
speaker tone generation.

PAGE 5

A-:

The 8237s support Direct Memory Access,
transferring 8-bit and 16-bit data between

memory and I/O devices. Two 8259s are con

figured as master/slave; they receive inter

rupt requests from a timer, keyboard control

ler, a real time clock, the numeric processor
and up to 11 other sources. They issue a
signal to the CPU to initiate interrupt

routines. The GC101 converts 16-bit buses

for peripherals having only 8-bit wide buses;

thus maintaining compatibility with the 8088
PC> The GC101A can access both 1M and 256k
DRAMs, because it has two extra pins (ADRSEL
and M A 9); while the GC101 can access only

256Kxl or 256KX4 DRAMs. NOTE: references to
the GC101 are generic, meaning either the
GC101A or GC101. Except for the two extra
pins in the GC101A, there is no difference
between the two versions.

The GC101 design encompasses one wait state
for memory operations and four wait states
for I/O. The GC101 is internally programmed

to insert, command delay based on the cycle
type as shown in the table on the following

page. To improve performance, use faster RAM

and CPU, or reduce the memory wait states to
zero by adding external synchronization

logic. Memory is configurable from 256k to 4
MB by using RSEL0-RSEL2. Two inputs, HISPEED
and IOSPEED, est ablish chip and system
speeds. The chip operates up to 16MHz in the
full commercial temperature range. (0-70#C)

PAGE 6

6C102 Data Buffer Functional Description

The GC102 Data Buffer chip buffers data for
the CPU (DO-15), the system expansion data
bus (SDO-15), and the memory data bus (MDO-

15) . Two signals select data flow direction;
DT/R controls flow between the D and SD
buses, MBDIR controls flow between the MD and
SD buses. For each signal, a high dictates
flow to the SD bus , a low means flow from the
SD bus. In addition, data latches between
the D and SD buses are latched when CNTLOFF
is high. The GC102 Data Buffer includes

parity checking logic, for board implementa
tions that can use it .

During memory read cycles, 16 RAM chips on
the system board output MD to the GC102. Two
additional RAM output MDPOUTO (lower byte)
and MDP0UT1 (upper byte). These 8 inputs are
used in two 9—bit—wide parity—error detection
circuits. During memory writes, the GC102
supplies MDPINO, MDPIN1 and the MD bus to

those 18 RAM chips.

Parity-error checking is enabled when MDPCKE

input is high. If an error is detected on
either byte of the memory data b u s, and
checking is enabled, /MDPCKN output goes low .
Strap pin 73 HIGH to select Data Buffer mode.

(LOW selects Address Buffer functions.)

PAGE 7

6C102 Address Buffer Functional Description

The GC102 Address Buffer chip provides ad
dress buffers for the System expansion bus

(SAO-15), the local I/O bus (XA1-16), and the
system board DRAMs (MAO-8). ALE is included
to latch addresses from the CPU .

Two signals select direction flow of the
addresses; /DMAAEN controls the XA and SA
buses, and CPUHLDA controls the MA and SA

address buses. A low on either signal sends
addresses to the SA bus, a high indicates the
SA address bus is driving one of the other
buses.

ADRSEL is input to the GC101A, and it con
trols RAS and CAS timing of bit MA9. A 10-

bit address, needed for accessing 1 Mbit

DRAMs, is produced by adding MAO-8 from this

chip with MA9 from the GC101A. Strap pin 73

LOW to select Address Buffer mode. (HIGH

selects Data Buffer functions.)

PAGE 8

Ill

SYSTEM SUPPORT FUNCTION

SYSTEM TIMERS

The system has three programmable timer/
counters controlled by an Intel 82542 timer/
counter chip. These are channels 0 through

2 , defined as follows:

C ha nn el 0
G AT E 0

C LK IN 0
C LK OU T 0

C ha nn el 1
G AT E 1
C LK IN 1
C LK OU T 1

S y st e m Ti me r
T ie d o n
1 .1 90 M H z OSC
8 25 9 A I RQ

R ef re sh Re qu es t G en er at or
T ied on

1 .1 90 MH z OS C

R qe us t R ef re sh Cycl e

Note: Channel 1 is programmed to generate a

15 micro-second period signal.

C ha nn el 2
G AT E 2
C LK IN 2
C LK OUT 2

T on e G e ne ra t io n fo r S pe ak er
C ontr ol l ed by b it 0 of port h ex 61 PPI bi t
1 .1 90 M H z SO C
U s ed t o driv e t he sp ea ke r

SYSTEM INTERRUPTS
Sixteen levels of system interrupts are

provided by the 80286 NMI and two 8259A

Interrupt Controller chips. The following
shows the interrupt-level assignments in
decreasing priority:

PAGE 9

L EVE L
M icro p ro cess or N M I
I nt er ru pt co nt roll er s
C TR L 1 C TR L 2

I RQO
IRQ1
I RQ 2

IR Q8
IR Q9
IR Q 10
IR Q1 1
IR Q 1 2
I RQ13
I RQ14

IR Q 1 5
I RQ 3
IR Q4
IR Q5
I RQ6
I RQ7

F UNC TI ON
P ar ity or I/O channel c he ck

T im er outp ut 0
K ey b oa rd (O ut pu t bu ff er fu ll )
I nte rr up t fro m CTR L 2
R ea ltim e cl oc k i nt errupt
S of tw a re re di re ct ed to IN T O AH (I RQ2 )
R es er ved
R es erve d
R es er ved
C op ro ce ss or
F ix ed d is k co nt ro ll er
R es er ved
S erial p ort 2
S eria l port 1
P ara ll el por t 2
D is k et te c on tr ol le r
P aral lel p ort 1

DIRECT MEMORY ACCESS
Eight DMA channels are supported by the

system. TWo Intel 8237-5 DMA controller
chips (four channels in each chi p) are used.
DMA channels are assigned as follows:

C TR L 1
C h0 - Sp are
C hl - SD LC
C h2 -Dis kett e
C h3 -Spa re

C TR L 2
C h4 -C a sc ade for C TR L 1
C h5 - Sp ar e
C h6 -Spa re
C h7 -Spa re

PAGE 10

Channels 0 through 3 are contained in DMA
controller 1 . Transfers of 8-bit data, 8-bit

I/O adapters and 8-bit or 16-bit system

memory are supported by these channels. Each

of these channels will transfer data in 64KB
blicks throughout the 16-megabyte system

address space.
Channel 4 through 7 are contained in DMA

controller 2. To cascade channels 0 through

3 to the microprocessor, use channel 4.
Transfers of 16-bit data between 16-bit
adapters and 16-bit system memory are sup
ported by channels 5 , 6, 7. DMA channels 5
through 7 will transfer data in 128KB blocks
throughout the 16-megabyte system address

space. These channels will not transfer data

on odd-byte boundaries.

The addresses for the page register are as

follows:

P AG E R ES 1G ER

D MA Ch an ne l 0

D MA Ch an ne l 1

D M A Chan ne l 2

D MA C hannel 3

D MA Ch anne l 5

D MA C ha nn el 6

D MA Channe l 7

R ef re s h

I /O HEX A DD RE SS

0 08 7
0 08 3
00 81
0 08 2
0 08 B
0 08 9
0 08 A
0 08F

PAGE 11

Address generation for the DMA channels is as
follows:

* For DMA channels 3 through 0

SOURCE DMA PAGE REGISTERS 8237A-5

Address A23 - A16 A15 - AO

Note: To generate the addressing signal "bvte

high enable" ;

(B HE) invert address line AO.

* For DMA channels 7 through 5

SOURCE DMA PAGE REGISTERS 8237A-5
Address A23 - A17 A16 - a

Note: The BHE and AO addressing signals are

forced to a logic 0. DMA channel ad-
dresses do not increase or decrease
through page boundaries (64KB for
channels 0 through 3 and 128KB for

channels 5 through 7) .

REAL TIME CLOCK AND NONVOLATILE RAM
The real time clock MC146818 and its 64 bytes

of RAM information are backed up by 6V DC
battery. The internal clock circuitry uses
14 bytes while the rest is allocated to

system configuration.

PAGE 12

A DDRE SS
0 0
01

02
03
04
05
0 6
0 7

0 8
0 9
0A
OB
OC
OD
OE

OF
10
11
12

13
14
15
16
17
18
1 9-2D
2 E- 2F
3 0
31
3 2
3 3
3 4- 3F

D ESCR IPTI ON
S ec o nd s
S ec o nd alar m
M in u te s
M inut e al a rm

H ou rs
H ou r alar m
D a y of we ek
D ate of mo nt h
M on th
Y ea r
S ta tu s reg is ter A
S ta tus r eg is t er B
S ta tus r eg is t er C

S ta tus r eg is te r D

D iagn o st ic st at us b yt e

S hutd ow n
D iske t te driv e ty pe by te - dri ve r A an d B
R eser ved

F ix ed dis k ty pe by te - d ri ver C a nd D

R eser ved

E qu i pm en t b yt e
L ow ba se m e mo r y
H igh bas e m e mo ry
L ow ex pans i on mem o ry b yte
H igh e xp a ns ion memo ry b yt e
R eser ve d
2 byte CM OS ch ecks um

L ow ex pans i on mem o ry b yte
H igh expan sion mem o ry b yt e

D at a cent ury by te

I nf orma ti on flag s (s et d ur in g po we r on)

R eser ve d

PAGE 13

IV I/O CHANNEL INTRODUCTION

The I/O channel supports:

* I/O address space hex 100 to hex 3FF
* 24 - bit memory address (1 6 M B)

* Refr esh of system memory from channel

microprocessor

* Selection of data accesses (either 8 bit or

16 bit )
* Interrupt
* DMA channels

*1 / 0 wait - state generation

* Op en-b us structure (allowing multiple

micropr ocesso rs to share the s y s tem 1s
resources, including memory)

The following figure shows the pin numbering
for I/O channel connectors JP15, JP16. JP17

JP18, JP31. '

PAGE 14

Rear Panel

Bl A1

B IO

B 20

B3 1

-

1 1 t 1 1 1 Mill

-

-

Mil Mil 1 Í 1

-

A 10

A 20

A3 1

I/O Channel Pin Numbering

C om po ne nt Si de

PAGE 15

The following figure shows the pin numbering
for I/O channel connectors JP6, JP7, JP8,

JP9, JP14.

R ea r Pa nel

D1

D IO

D 18

I/O Channel Pin Numbering

Cl

CI O

C 18

C om po ne nt Side

PAGE 16

The following figures summarize pin assign
ments for the I/O channel connectors.

I /O P in

A1
A 2 S D7
A 3
A 4
A 5
A 6
A 7
A 8
A 9
A 10
Al l
A 12
A 13
A 14
A 15
A 16
A 1 7
A 1 8
A 19
A 20
A2 1
A 22
A 23
A 24
A 25

A 26
A 2 7
A 28
A 29
A 30
A3 1

S ign al N am e

- I/O CH CK

S D6
S D5
S D4
S D3
S D2
SD1
S DO

-I /- CH RD Y
A EN
S A1 9
S A1 8
S A1 7
S A1 6
S A15
S A1 4
S A1 3
S A12
SA 11
S A1 0
S A9
S A8
S A7
S A6
S A5
S A4
SA 3
S A2
SA1
S AO

I / O

I
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I

0

I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O

I/ O

I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O

I/O Channel (A-Side,JP15.JP16,JP17,JP18,JP31)

PAGE 17

I/ O Pin
B1
B 2
B3
B4
B5
B 6
B 7
B 8
B 9
B IO
B1 1
B 12
B 13
B 14

B 15 - DA CK 3
B 16
B 17
B 18
B 19
B 20
B21
B 22
B 23 IRQ5
B 24 I RQ4
B 25
B 26
B 27
B 28
B 29
B 30
B31

S ig nal Nam e
G ND
R ES ET D RV

+ 5 Vdc

I RQ9

-5 Vd c

D RQ2

- 12 V d c
o us
+ 12 Vd c
G ND

- SM EM W

- SM EMR

- IO W

- I OR

D RQ 3

- DA CK 1
D RQ1

- Re fr es h
CL K1

I RQ7
I RQ6

I RQ3

- DA CK 2
T /C
B AL E

+ 5 Vd c
O SC

G ND

»/ O

G ro un d
0
P ow er

I
P ow er

I
P ow er

I
P ow er
G ro un d
0
0

I/ O
I/ O
0
I
0
I
I/ O
0
I
I
I
I
I

0
0
0
P ow er
0
G ro un d

I/O Channel (B-Side,JP15,JP16,JP17,JP18,JP31)

PAGE 18

I /O P i n Signa l N am e
Cl SBHE
C 2 L A23
C 3 LA 22
C 4
C5
C 6
C 7 LA 18 I/ O
C 8
C 9
C IO
Cl 1
C 12 S D0 9 I /O
C 13
C 14 SA11 I /O
C IS SA 12
C 16 S A1 3 I /O
C 17
C 18 S A15 I /O

I /O C hannel (C- Si d e, JP 6, JP 7 ,J P8 .J P9,J P1 4)

LA 21
L A20
L A1 9 I/ O

LAI 7 I /O

- MEMR I/ O

- MEMU

S D0 8

S A1 0

S A14

I/ O
I/ O
I/ O
I/ O
I/ O
I/ O

I/ O
I/ O

I/ O

I/ O

I/ O

PAGE 19

I/ O Pi n
D1
D 2
D 3
D 4
D 5
D 6

D 7
D 8
D 9
D IO
Dl l
D 12

D 13
D 14
D 15
D 16
D 1 7
D 18

I/ O Ch an nel ( D- Side ,J P6 ,J P7, J P8 ,JP9 ,J P1 4)

S ig nal N ame

- ME M C S16

- I/ O C S1 6
I RQ1 0
IR Q1 1
I RQ12
IR Q1 5
I RQ14

- DA CK O

D RQO

- DA CK5
D RQ 5

- DA CK 6
D RQ6

- DA CK 7
D R Q7
+ 5 V dc

- MA STER
G ND

I /O

I
I

I
I
I
I
I

0

I

0

I

0

I

0

I

P ow er

I

G ro un d

I/O Channel signal Description

The following is a description of the system
board's I/O channel signals. All signal lines
are TTL-compatible. I/O adapters should be
designed with a maximum of two low-power

shottky (L S) loads per lin e .

SAO through SA19 (I/O)

Address bits 0 through 19 are used to address
memory and I/O devices within the system.
Three 20 address lines, in addition to LA17
through LA23, allow access of up to 16MB of
memory. SAO through SA19 are gated on the
system bus when 'BALE', is high and are

PAGE 20

latched on the falling edge of 'BALE '. These

signals are generated by the microprocessor
or DMA controller. They also may be driven by
other microprocessor or DMA controllers that
reside on the I/O channel.

LA17 through LA23 (I/O)

Theses signals (unlatched) are used to ad
dress memory and I/O devices within the

system. These signals are valid when "BALE"

is high. LAI7 through LA23 are not latched
during microprocessor cycles and therefore do
not stay valid for the whole cycle. Their
purpose is to generate memory decodes for 1
wait-state memory cycles. These decodes

should be latched by I/O adapters on the

falling edge of 'BALE.' These signals also

may be driven by other microprocessors or DMA

controllers that reside on the I/O channel.

CLK (0)

This is the 6-MHz system clock. It is a

synchronous microprocessor cycle clock with a

cycle time of 167 nanoseconds. The clock has

a 50% duty cycle. This signal should only be

used for synchronization. It is not intended

for uses requiring a fixed frequency.

RESET DRV (0)

'Reset drive' is used to reset or initialize

system logic at power-up time or during a low

line-voltage outage. This signal is active

high.

PAGE 21

SDO through SD15 (I/O)

These signals provide bus bits 0 through 15
for the microprocessor, memory, and I/O

devices. DO is the least-significant bit and

D15 is the most-significant bit. All 8-bit
devices on the I/O channel should use DO
through D7 for communications to the micro
processor. The 16-bit devices will use DO
through D15. To support 8-bit devices, the
data on D8 through D15 will be gated to DO
through D7 during 8-bit transfers to these
devices; 16-bit microprocessor transfers to
8-bit devices will be converted to two 8-bit
transfers.

BALE (0) (buffered)

'Address latch enable1 is provided by the
82288 bus controller and is used on the
system board to latch valid addresses and

memory decodes from the microprocessor. It is
a available to the I/O channel as an indica
tor of a valid microprocessor or address SAO
through SA19 are latched with the falling
edge of 'BALE '. 'B AL E ' is forced high during

DMA cycles.

-I/O CH CK ( I)

1~I/O channel check' provides the system

board with parity (err or) information about
memory or devices on the I/O channel. When
this signal is active, it indicates an uncor—
rectable system error.

PAGE 22

I/O CH RDY (I)

'I/O channel ready' is pulled low (not ready)

by a memory or I/O device to lengthen I/O or

memory cycles. Any slow device using this

line should drive it low immediately upon
detecting its valid address and a Read or
Write command. Machine cycles are extended by
an integral number of clock cycles (167
nanoseconds). This signal should be held low
for no more than 2.5 microseconds.

IRQ3-IRQ7, IRQ9-IRQ12 and IRQ 14 through 15

Interrupt Requests 3 through 7 , 9 through 12,

and 14 through 15 are used to signal the
microprocessor that an I/O device needs
attention. The interrupt requests are priori
tized, with IRQ9 through IRQ12 and IRQ14
through IRQ15 having the highest priority

(IRQ9 is the highest) and IRQ3 through IRQ 7

having the lowest priority (IRQ7 is the

lowest). An interrupt request is generated
when an IRQ line is raised from low to high.
The line must be held high until the micro
processor acknowledges the interrupt request

(Interrupt Service routine). Interrupt 13 is
used on the system board and is not available
on the I/O channel. Interrupt 8 is used for

the read-time clock.

PAGE 23

-IOR (I/O)

'-I/O Read' instructs an I/O device to drive

its data onto the data bus. It may be driven

by the system microprocessor or DMA control

le r, or by a microprocessor or DMA controller

resident on the I/O channel. This signal is

active low .

-IOW (I/O)

'-I/O Write' instructs an I/O device to read
the data on the data bus. It may be driven
by any microprocessor or DMA controller in
the system. This signal is active lo w .

-SMEMR (O) -MEMR (I/O)

These signals instruct the memory devices to
drive data onto the data bus. '-SMEMR' is
active only when the memory decode is within
the low 1Mb of memory space. '-MEMR' is
active on all memory read cycles. '-MEMR'
may be driven by any microprocessor or DMA

controller in the system. . '-SMEMR' is de
rived from '-MEMR', it must have the address
lines valid on the bus for one system clock

period before driving '-MEMR' active. Both

signals are active LOW.

-SMEMW (O) -MEMW (I/O)

These signals instruct the memory devices to
store the data present on the data bus. '-
SMEMW' is active only when the memory decode

is within the low 1Mb of the memory space.

'-MEMw' is active on all memory read cycles.
'-MEMW' may be driven by any microprocessor

or DMA controller in the system. '-SMEMW ' is

PAGE 24

derived from '-MEMW1 and the decode of the

low 1Mb of memory. When a microprocessor on

the I/O channel wishes to drive '-MEMW', it

must have the address lines valid on the bus

for one system clock period before driving

'-MEMW ' active. Both signals are active lo w .

DRQ0-DRQ3 and DRQ5-DRQ7 (I)

DMA Requests 0 through 3 and 5 through 7 are
asynchronous channel requests used by periph
eral devices and the I/O channel microproc
essors to gain DMA service (o r control of the
system). They are prioritized, with 'DRQO'

having the highest priority and 'DRQ7' having

the lowest. A request is generated by bring

ing a DRQ line to an active level. A DRQ
line must be held high until the correspond

ing 'DMA Request Acknowledge' (DACK) line
goes active. 'DRQO",through 'DRQ3 ' will
perform 8-bit DMA transfers; 'DRQ5' through

IDRQ7' will perform 16-bit transfers. 'DRQ4'

is used on the system board and is not avail
able on the I/O channel.

-DACKO to -DACK3 and -DACK5 to -DACK7 (O)

-DMA Acknowledge 0 to 3 and 5 to 7 are used

to acknowledge DMA requests (DRQO through
DRQ7). They are active low .

AEN (O)

'Address Enable* is used to degate the micro
processor and other devices from the I/O
channel to allow DMA transfers to take place.

When this line is active, the DMA controller
has control of the address bus, the data-bus

PAGE 25

Read command lines (memory and I/O), and the
Write command lines (memory and I/O).

-REFRESH (I/O)

This signal is used to indicate a refresh

cycle and can be driven by a microprocessor
on the I/O channel.

T/C (O)

'Terminal Count' provides a pulse when the
terminal count for any DMA ch annel is
reached.

SBHE (I/O)

'Bus High Enable' (sy st em ) indicates a trans

fer of data on the upper byte of the data
bus, SD8 through SD15. Sixteen-bit devices
use 'SBHE ' to condition data bus buffers tied
to SD8 through SD15.

-MASTER (I)

This signal is used with a DRQ line to gain
control of the system. A processor or DMA
controller on the I/O channel may issue a DRQ
to a DMA channel in cascade mode and receive

a '-DACK'. Upon receiving the '-DACK', an

I/O microprocessor may pull '-MASTER' low,
which will allow it to control the system

address, data, and control lines (a condition
known as tri-state) . After '-MASTER' is lo w ,
the I/O microprocessor must wait one system

clock period before driving the address and
data lines, and two clock periods before

issuing a Read and Write command. If this

signal is held low for more than 15 microsec-

PAGE 26

onds, system memory may be lost because of a
lack of refresh.

'MEM CS16 (I)

'-MEM 16 Chip Select' signals the system
board if the present data transfer is a 1
wait-state, 16-bit, memory cycle. It must be
derived from the decode of LA17 through LA23.

'-MEM CS16 should be driven with an open
collector or tri-state driver capable of

sinking 20 mA.

'I/O CS16 (I)

'“I/O 16 bit Chip Select' signals the system

board that the present data transfer is a

16-bit, 1 wait-state, I/O cycle. It is

derived from an address decode. '-I/O CS16'

is active low and should be driven with an

open collector or tri-state driver capable of
sinking 20 mA.

OSC (O)

'Oscillator' (O S C ) is a high-speed clock with
a 70-nanosecond period (14.31818 MHz). This
signal is not synchronous with the system
clock. It has a 50% duty cycle.

OWS (I)

The 'Zero Wait State' (O W S) signal tells the

micro processor that it can complete the

present bus cycle without inserting any addi
tional wait cycles. In order to run a memory
cycle to a 16-bit device without wait cycles,

' OWS' is derived from an address decode gated

with a Read or Write command. In order to

PAGE 27

run a memory cycle to an 8-bit device with a
minimum of two wait states, 'OW S' should be
driven active one system clock after the Read
or Write command is active gated with the
address decode for the device. Memory Read
and Write commands to an 8-bit device are
active on the falling edge of the system
clock. 'OWS' is active low and should be

driven with an open collector or tri-state
driver capable of sinking 20 mA.

PAGE 28

V JUMPER SETTING AND CONNECTOR PIN ASSIGN

MENT

The system board has the following connectors
and jumpers. Configure your system according

to the table below:

J UM PE R
J 2 0
J 2 5
J 26
J 27 ,J 28,J
J 3 4

J 3 5

C ON NECT OR

J 1
J 2
J 3
J A
J 5

J 1 9
J 3 2
J 3 3

F UN CT IO N
B a tt e ry pow er O N/ OF F
E PR OM si ze sele ct i on
D i spla y s e le ctio n

2 9 D RA M si ze s e tt in g

R TC c hi p s el e ct ion

P arity e na b le /dis able

F UN CT IO N
K eylo ck an d Po wer on LE D c onne ct or

T urbo mod e LED i nd ic at or
S pe aker conn ecto r
H ardw ar e re se t con ne ct o r
T urbo swi tc h f or se le ct hi gh or low spe ed

E xt er na l b atte r y co nn ecto r
P ow e r supp l y co n ne ct or
K eybo a rd co nnec tor

1. Description of Jumper Setting

Placing a jumper cap over some jumper means

"ON"; Removing it away means "OFF"

J 2 0: B atte r y po we r

ON : C on ne ct b at t er y t o th e RT C ci rcu it .

O FF: Disco n ne c t b atte r y to th e RT C c ircu it.

PAGE 29

If the system board would be shipped for a

long time, this jumper cap could be removed
for saving power consumption. But on normal
operation, this jumper cap must be placed

over.

J 2 5: EPR OM SI ZE
1- 2 ON: 2 71 2 8 RO M i ns er te d
2 - 3 O N: 27 2 56 ROW in se rted

J 2 6: D i sp l ay sele ctio n

ON : Co lor gr aphi c

O FF: M onoc h ro m e

J 27,J 28,:DRAM Size setting when using 256K
J 29 DRAM, J 28 must be "ON ", and J 27,

J 29 perform as follows:

S el ec t

J 2 9

J 2 7
ON
O N

O FF

O FF

O N
O FF
O N
O FF

T ES T M ODE
0 -5 1 2K
0 -6 4 0K
0 -640 K, 1M- 1. 38 4M

When using 1M DRAM, J 28 must be "OFF",and

J 2 7 , J 29 perform as follows:

J 27 J 2 9 Se le ct
O N O N 0-512 K
O N OF F 0-6 40K
O FF O N 0-64 0K , 1M -2 .3 84 M
O FF O FF 0- 64 0K , 1 M- 4.384M

J 34 : RTC chip se lect i on
1 - 2 O N: R TC ch i p us i ng DS 1287
2 - 3 ON: R TC chip u si ng 1 4681 8

________

PAGE 30

J 3 5: Par i ty en able /dis ab l e
O N : P arit y e nabl e
O FF: Pa ri ty di sa b le

2. Description Of Connector Pin Assignment
J 1: Keylock and Power on LED connector

P IN AS SI G NM EN T

1 P ow er LED
2 No t used
3 G ND
4 K eybo a rd in hi bi t
5 GN D u su a lly conn ecte d w it h Bl a ck w ir e

J 2: Turbo LED Indicator

J2 is connect e d with e xtern al Tu rbo LED

indicator. LED turns on when the system is in
12 MHz.

j 3: Speaker Connector

P IN ASS I GN MENT
1 Data ou t

u se d

N ot

2

G ND

3

+ 5 V usua l ly c o nn ecte d wi th re d wi re

4

Hardware reset

4 :

J

J 4 is connected with External Hardware Reset
Button to enable Hardware Reset

PAGE 31

J 5; Turbo switch for select high or low speed

J 5 is connected with external hardware speed

change button to change processor frequency.

J 19: External battery connector

If J 19 is used to take place of rechargeable
battery, the four "AA" batteries will sustain
about 4 months

P IN ASS I GNME N T WI R E C OL OR

1 6 V Red
2 Not used D on't car e

3 GND Bla ck
4 GND B l ac k

J 32: Power Supply Connector
J32 is used to connect to the power supply

cable

P IN

A SSIG N ME N T

1 Power g oo d

2 + 5 V
3 +12 V

4

- 12 V

5

G ND

6 GND

7 G ND

8 G ND

•

9

V/1

<
10 +5V
11

+ 5 V

12

+ 5V

W IR E CO LO R
O r ange
R ed
Y ellow
B lue
B lack
B la c k
B la c k

B lack
W h it e
R ed
R e d
R ed

PAGE 32

J 33: Keyboard Connector
J 33 is a 5-pin, 90-degree printed circuit

board mounting, DIN connector.

P IM ASS IGNM ENT

1 K e yb o ar d clo ck

K ey b oa r d D at a

2

N ot u se d

4

G ND
+ 5V

5

PAGE 33

VI. HOW TO CONTROL THE SYSTEM SPEED BY

SOFTWARE

1. Press "Ctrl", "Alt" and "-" to change speed or press "Ctrl",
"Alt" and "+" to change speed.

A: <Alt>
C: <Ctrl>
S: <Shift>

<- >

+ : <+ >

\: <\> slash

2. When equipment of mainboard used AWARD BIOS and PTC 8042 Con
troller.

A: <Alt>
B: <Ctrl>

<- >

+ : <+>

\: <\> slash

3. When equipment of mainboard used AMI BIOS.

A: <Alt>
B: <Ctrl>
C: <\> slash

AGE 34

62 MAIN BOARD OUTLINE DIAGRAM

I I J 3 4 S

1, 2: 1
2, 3:

O N '. Colo r

0F F : H o n o

J 33 : Ke y b oa r d C o n n e c to r

1 S128 7
1 4681 8

□

Oil

ON : B a t t e r y

Po w e r Up

OF F : B att e r y

Po w e r
O F F

J 19: Exter n a 1-H

Ba t t e r y
Co n n e c t o r

J 2 7

J 2 8 J29

ON

ON

O N

O N OF F B- 5 1 2 K
OF F ON
O F F

ON O F F 0 - 640K, 1ÍH.384N
ON

OF F ON 0- 5 1 2 K
O N

OF F OF F
OF F OFF
O F F OFF OFF

wmm

J3 2 : P o n e r S u p p l y

Co n n e c t o r

$ 0 ÜD

BON S i z e

O N Tes t Nod e
O N 0- 6 48K

0- 6 4 0 K

O N 0-640H, 1N-2. 3 8 4 N

0 - 64 0 K, 1N - 4 . 3 8 4 N

1, 2:2 7 1 2 8
2, 3 : 2 7 2 5 6

i

---

11

JU L

* I f J 2 8 "O N" mus t in ser t 25 6 K

i . e.4 12 5 6 , 4 4 2 5 6 or 2 5 6 K B A N No du l e
i nto DI P soc k e t o r BON N od u l e s ocke t
Bu t the y c a n ' t b e in sta l led

s i aultaneo u s.

« If J2 8 " O F F " c a n in s tall I N BO N

No d ul e on ly .

:Pa r i t y E n a b l e

OF F : P a r it y D i s a b l e

B3 : T ur b o L E D

Co nne c tor

Ha r d w a re Bes e t
Co nne c tor

5: T u r b o Swi t c h

1 I— Jl: P o w e r LED a nd

Ke y l o c k Conn e c to r

[-J3: Sp e a k e r C o n necto r

PAGE 35