The SA4600 Disk Controller is a complete preprogrammed microprocessor based controller
for the Shugart
SA4000 series disk drives and SA800/8S0 Floppy Disk Drive.
The
SA4600 Disk Controller is designed to perform asyncronous
data
transfers between the
SA4000 and a host CPU.
The SA4600 features a general purpose DMA
type
interface designed
to
easily adapt
to
com-
mercially available DMA controller chips.
Several optional configurations also make this interface adaptable to virtually any
type
of
mini or micro computer. Some main features
of
this controller are
as
follows:
A)
Control
of
one
to
four SA4000 drives and one
to
four SA800/8S0 Floppy Disk Drives.
B)
Asyncronous DMA transfer with full sector buffering.
C)
Four
user selectable formats - 32 sectors
of
S12 bytes, 60 sectors
of
2S6 bytes, 104
sectors
of
128 bytes,
or
26 sectors
of
2S6 bytes (Floppy
option
only).
D)
Overlap seek operation (up to four drives).
E) Single five volt supply.
2.0 SPECIFICATION SUMMARY
Environmental Limits
Ambient temperature
=
O°C
to
SO°C
= 20% to 80%
Relative humidity
OC
Voltage Requirements
+S
VDC ±
S%
7.0A typical 7.S maximum (with floppy option)
Heat Disipation
= 120 BTU/hr. typical
Mechanical Dimensions (reference Figure 8)
Length
= 18" (4S.72cm)
Width
=
l2.S"
(31.7Scm)
Height
= 1" (2.S 4cm)
3.0 SA4000
DRIVE
INTERFACE DESCRIPTION (Reference
Figure
1)
The SA4000 drives are interfaced through connectors
Jl,
J2, J3,
J4
and JS.
Jl
is a
SO
pin ribbon cable
type
edge connector which connects the SA4000 drives in a daisy
chain configuration.
Up
to
four drives may be bussed together on this cable. This cable
should
not
exceed 20 feet (6 meters). Refer
to
section
9.l.S
- Cable Termination
Description.
J2 through JS are
20 pin ribbon cable type edge connectors which are the radial connectors
for
up
to four drives.
J2
is
the
radial connector for Drive
1.
J3
is
the radial connector for
Drive
2,
etc. These cables should
not
exceed 20 feet (6 meters). Refer
to
Figure 2 for a
diagram
of
the pinouts for J 1 and J2 through JS.
Refer
to
section 12.2 for Connector Physical Description.
2
Jl
SA4000
HOST
CPU
CONTROL
HOST
CPU
DATA
J6
50 PIN
SA4600
J6
50
PIN
Jl
50 PIN
J2
20 PIN
J3
20
PIN
J4
20 PIN
J5
20 PIN
w
.....J
co
«
u
z
«
I
u
>-
U)
«
Cl
w
>
cr:
Cl
DRIVE
J2
Jl
SA4000
DRIVE
J2
Jl
SA4000
DRIVE
J2
Jl
SA4000
DRIVE
J2
1
2
3
4
Figure
1.
SA4600 Interface Block Diagram
4.0 HOST
The SA4600
plished
Figure 3 for pin assignments. All signals
cable should
This
A description
CPU
host
through
of
INTERFACE DESCRIPTIOr\l
CPU interface
connector
not
exceed 10 feet (3 meters).
J6.
is
a general purpose DMA
J6
is a 50
pin
ribbon
to
the CPU interface are
the CPU interface lines follows:
type
interface which
type
cable edge connector. Refer
TTL
4.1 Reset
This line will cause the controller
command,
operation
200
nanoseconds. The SA4600 will
The
host
status, and result registers, and go
may cause
CPU must time
improper
out
data
for 3 ms.
cease all
to
be written. The RESET pulse
not
operation,
into
accept a
clear local ram
a normal wait loop. A reset during a write
command
for 3 milliseconds
to
4.2 Controller Select
This signal functions as a device select and should only be active when
registers in the controller are
to
be
operated
on.
4.3 Address
The address line selects which register will be read/written. See Table
is
accom-
to
negative true, 48MA.
memory,
width
one
must
after
of
the four
reset the
be
at
least
a reset.
1.
3
Ground
Ground 49
J1
1 2
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
J2 - J5
-Head Select 1
4
6
8
-Head Select 2
-Head Select 4
-Head
Select
-Index
-Ready
-Sector Mark
-Drive
Select 1
-Drive
Select 2
-Drive
Select 3
-Drive
Select 4
-Direction
-Step
-Fault
-Write
-Track
-Write
-Read Gate
Clear
Gate
00
Fault
!\I/C
8
-Index
-Ready
-Byte
Clk
-Seek
+PLO Clock
+WRT
Ground
-Write
Ground
-Read
Complete
Data
Clock
Data
Sector
1 2
3
5
7 8
9 10
11
13 14
15
17
19 20
4
6
12
16
18
Ground
Ground
Ground
Ground
-WRT
+WRT Clock
Ground
-PLO
+Read Data
Ground
Data
Clock
NIC
Figure 2.
Assignments
for
J1
and
J2 Thru J5
Pin
4.4 Read
When
this line
is
active along with controller select, one
of
two read only registers will be
read onto the data bus. See Table 1 and host interface timing, Figure
4.5 Write
When
this line
written to from the data bus. See Table 1 and Figure
4.6 Data
The data bus consists
significant bit. See Section
-ADDRESS = 1
-ADDRESS = 0
is
active along with controller select, one
Bus
0-7
of
8 bit bi-directional tri-state lines with data bus bit 0 being the least
8.0 for an optional configuration.
Table
1.
Interface
READ
ONLY
of
two write only registers will be
4.
Register
REGISTERS WRITE
STATUS COMMAND
RESULT
Map
4.
ONLY
PARAMETER
REGISTERS
4
G rou n d I 1 I
Ground
•
I £
49
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
A
'l
I
4
6
8
nnnr-rat""
J-\U
U n
c;);)
READ
WRITE
CONTROL SELECT
INTERRUPT
DMA
REQUEST
DMA
ACKNOWLEDGE
RESET
DATA
0
DATA
1
DATA
2
DATA
3
DATA
4
DATA
5
DATA
6
DATA
7
*
*
*
*
*
*
*
*
All
signals are negative true.
*See
4.7 DMA
Section
Figure
Request
3.
Pin
8.
0
for
optional
Assignments
configuration.
for
Host
CPU
After a data transfer command has been received and data
controller will make this line active to request a memory
timing),
4.8
This signal is made active by the host CPU to indicate
and
the data bus. The data bus
Refer
4.9 I nterru pt
This signal
it
result register
See Section 8.0 for optional configuration.
DMA
Acknowledge
that
data
is
either present on the data bus
is
active during acknowledge for either a read
to
Figure 5 (DMA timing). See Section 8.0 for optional configuration.
is
made active by the controller to indicate
is
in need
of
service for presenting the ending result byte. The interrupt
is
read. All commands end with an interrupt.
that
or
data has been written into memory from
that
I/O (J6)
is
ready to be transferred, the
cyde.
Refer to Figure 5 (DMA
a memory cycle has been granted,
or
write operation.
an operation has terminated and
is
reset when the
5
CONTROL SELECT-
ADDRESS
READ
DATA
BUS
*
\ /
Ij
II II
~l!j!IJIJ
I I I
~~~~~~~~~~~~~~~~~~~~~~
/III
!II!
\
\
~~j
P.
m
!/!/IIJl(//J11I11!/
/~I--
j.-10
/IJ/
NS
!!If//;
MIN.
CONTROL SELECT
ADDRESS
WRITE
71
ONS
MIN.~
DATA
5.0 HOST
There are four registers in the controller (shown in Table
tions. They are the command, parameter, status, and result registers. These
available
(see Figure 4).
BUS*
CPU
on
the
INTERFACE REGISTER DESCRIPTION
data bus when the associated read, write, and address lines are activated
\ /
(//II
fJ!/HfJJ/
I I L A I
--.\
Figure 4. Host
/
/II
///';:y
~
q p
F-15
CPU
NS
MIN.
Control Interface Timing
I)
7!)
/I
I/IJ/
that
provide the control func-
mp;;
j.-10
1/1/1
I
/I
!//
NS
MIN.
registers are
5.1 Command Register
This
is
a 8 bit write only register
sequence. This register may
CPU.
Table 2 lists the commands executed
Section
5.2 Parameter Register
All
eter register
controller. Table 2 lists the number
Table 3 describes the usage for each
Commands will
6.0 describes each command in detail.
commands issued
is
a 8 bit write only register
that
when loaded signifies the beginning
not
be reloaded until a result has been presented to the host
by
the controller and their binary bit patterns.
to
the controller require additional data to be executable. The param-
that
serves to transfer the parameter data to the
of
parameter bytes required for each command and
of
the four possible parameters.
not
be executed until the last parameter byte has been transferred.
The status register provides the means for control information
host CPU and the controller. Contents
The status register bit assignment is
5.3.1 Command Busy and Command
When the Host CPU sets a command into the command register,
command busy bits will be set. When the controller reads the command and begins execution, it will reset the command register full bit. During execution, the command busy bit
remains set. The controller will then set interrupt
sequence and reset command busy after the result register has been read. The exception to
this rule is the seek command where command busy
so
5.3.2 Parameter
When
troller will reset this bit after the parameter register has been read, at which time the Host
CPU
to
Section 8.0
that overlapped seeks may be performed.
the Host CPU loads a byte into the parameter register this bit \vill be set. The con-
may send the next parameter byte.
Reg
for
Optional Configurations.
Figure 5. Host
as
follows:
Reg
Full
CPU
DMA Interface Timing
of
the status register is
Full
at
the completion
is
reset when the seek
to
be passed between the
not
valid during
both
the command full and
of
the command
DMA
is
implemented
transfer.
7
Table 2. Command
Code
Chart
1
Read
I.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11. Search Data Equal and Special
12. Search High
13. Search High
14. Search
15. Search
16.
17.
18.
19.
20.
21. Write
ID
Read
Diagnostic
Verify
Data
Verify
Data and Special
Seek
Recalibrate
Terminating Sector Request 0 0
Read
Data
Read
Data and Special
Search Data Equal
or
Equal X X
or
Equal and Special X
Low
or
Equal X
Low
or
Equal and Special X X
Write
ID
Format
Initialize
Write Data
Write Special Data
Cyl inder
Buffer
Inhibits
Multiple
Inhibits
Retry When
Sector Gp. When Set
Imbedded Seek When Set
set~
MSB
7
6
X 0
X 0
X X
X
X
X
0
0
0
X
X
X
X
X
X
X X
X
X
0 0
0 0
0 0
X
X
X X
a x I
I
-----l
~
BIT
4 3
5
1
0
0 0 0
0 0
X
X 0 0
0 0
0
0 0
0
0 0 0
X 0
X 0
X 0
X
0
0 0
X
2 1
0 0
0 0
0 0
0
1 1
0 0
0 0
0
0 1
LSB
0 Parameter
0
0 1
1 3
1
1
0
0
0
1
0
1
0
0
3-4
3-4
3-4
3-4
3-4
3-4
3-4
X 0 0 1 3-4
1
X 0
X
0 1
0
0
0 0 0
X 0 0
X
'
1
0 0
0
0 0
0
0
0
0
1 3-4
0
1 2
1
0
0
1 3-4
0
0
3-4
3-4
3-4
#
2
1
1
3
3 (SPECIAL)
5.3.3 Result
This bit is set
must read
Reg
at
the
result register. This
CPU. The result register is only valid when this
5.3.4 Interrupt
The controller will set this
rupt
line (Figure 3). The
by the Host
CPU.
5.4 Result Register
The result
is
loaded after the completion
abnormal occurance during
retried
if
an error occurs (see Section 11.0).
pletion result will be sent. However,
execution)
the
error still exists,
configura tion.
Full
the
completion
of a command
bit
is
reset when
bit
when it requires service. This
interrupt
the
bit
and line will be reset when
of
a command sequence. Its
execution
of
the
If a retry
if
after
2 retries (3
the
error
result
sequence
bit
to
the
result register
is set.
indicate
bit
that
is
read
will also activate
the
result register
content
the
Host CPU
by
the
indicates any
the
command. Certain commands may be
was successful,
attempts
is sent. See Table 5
only
including
for
the
the
good com-
the
initial
result
byte
Host
inter-
is
read
8
7 6
Table
3. Parameter Description
Bit
2
5
4
3
1 0
I • Drive Address: Drive 0-3 are
L:'
Not
Head Address: Bit 4
for 2 sided
fixed disks,
Used
floppy's.
is
4-
the
7 are
second
floppy
side
disks ..
7
6
I
7
6
L'
Not
6
7
I
5
5
Used
5
4
4
4
c=:.
3
3
3
Table
Fixed Head:
as
the
2
2 0
2
4. Status Register
fixed
0
I
I
0
I
The
head
•
..
r
head
address.
Cylinder
Starting
Multiple
Map
address
is
interpreted
Address
Sector
Address
Sector Count
LSB
o
'----
9
2
Command
Command
3 4
'-----
Parameter
Reg Full
Busy
5 6
L
L--
__
Interrupt
Result Reg Full
Reg Full
MSB
7
LLNotUsed
Not
Used
Not
Used
5.4.1 Result Byte Description
There are four types
information. These are shown by the completion codes (bits
to Table
5.
of
result bytes that are further broken down
to
give
more specific
6,
5,
and 4 respectively). Refer
5.4.1.1 Good Completion (Completion Type 00)
000 - Command completed without error.
00 1 Srch Not Met - The specified argument and the specified sector(s) did not
satisfy the search command.
010 Srch Met
011
100 thru
Srch Met High or Low - The unequal search
III
and drive
5.4.1.2 Sub-System Error (Completion Type 01)
This type
of
error indicates an error occurred in the drive or control unit.
Equal-
The argument and the sector contents are identical where specified.
was
satisfied.
- Seek complete - Result byte issued after a seek command
is
ready to read or write.
is
000 - Seek Error - Posted only for imbedded seeks when the control unit cylinder or
not
00 1 -
head register does
the
ID
field
of
a sector. The control unit
arm
if
retry
is
not
CRC
Error ID Field - The control unit detected a
match the cylinder or head address read
inhibited before posting this result.
will
re-calibrate and re-seek the head
CRC
error in an
off
the disk in
ID
complete
field.
Comp
Code
Completion
Type
letion
000
001
010
011
100
101
110
111
Table 5. Result Register
Result
Reg
MSB
LSB
Good
Completion
00
Good Completion Seek
Srch
Not
Met
Srch Met Equal
Met High
Srch
or
Levv
Seek
Complete
Drive 1
Seek
Complete Data Sync
Drive 2
Seek Complete
Drive 3
Seek
Complete
Drive 4
01
CRC
Field
CRC
Data
Sector
ID Sync
Map
7
----
65
r-
J,----
4
. Completion Type
3
]f----
2
----
o
----
Sub-System
Error
Error*
Error I D*
Error*
Field
Error
Err*
Err*
Not
Used
Completion Code
Speciai Data Found
Defective I D Found
10 Intervention
Drive
Not
Write Protection Check Record
(floppy
Restore
Write
Fault
Operator Command
Ready Illegal Length
only)
Error
Error
11
Not
Found*
Invalid Command
Late
DMA
*With inhibit retry
is
sent. With seek inhibit set
result
bit
in
command
not
set these error conditions
in
the command these errors
are
retried 2 times before
will
not
be retried.
10
010
- CRC
all
- Sector
100 - ID Sync
101 - Data Sync
5.4.1.3 Operator Intervention (Completion Type 10)
This
type
of
Error
Data Field - The controller was unable
retry
is
inhibited this result will be sent
error has been sent. When
data
the
DMA
twice and
transfer
Error
does
not
agree
Error -The
field within a 4
Error
field within a 4
error
cannot
if
this
of
data
takes place.
- The controller has determined
with
the
maximum sector code sent in
controller was unable
byte
tolerance.
- The controller was unable
byte
tolerance.
be resolved
retry
is
not
without
after
is
enabled the controller will
successful the result will be posted before any
outside help.
to
read the
the DMA transfer
that
the time between sectors
the
initialize command.
to
find
the
sync
to
find
the
sync
data
of
attempt
byte
for
byte
field.
the
for a
data
to
an
If
in
read
ID
data
100 - Drive
101 - Write
110 - Restore
111
5.4.1.4
This
type
000
00
1 - Record
a
10 - Invalid
all
Not
Ready - The ready line from
selected.
operation
recal
- Write
Protection
when
Error
command
Fault
Check - This
the
diskette
- While stepping
the
controller was unable
is
error
write
the
- The write fault line was active
The controller will reset the write fault
Command
of
result
Error (Completion Type 11)
is
sent when
the
control
unit
- Illegal Length - The parameters for
cylinder, head
command
Not
read from the track.
Command
- Late DMA - Can
supplied a
the desired
for
Found
byte
data
or
sector capacity
that
drive.
- The specified sector did
Cylinder and head numbers did match.
of
and
- The
only
data
command
occur
on
::l
before it was required. The data field does
should be re-written.
the
disk
can only
occur
protected.
maximum
to
number
detect
at
at
the
beginning
cannot
of
the
the
execute
command
drive as specified
not
code is undefined.
write
operation
is
not
on
track
the
end
the
exceed the
occur
where the
active
after
the
drive
a floppy disk write
of
cylinders during a
00
line active.
of
a write operation.
of
a new command.
command
as specified.
maximum
by
the
initialize
in any
of
host
the
ID fields
DMA has
not
contain
is
not
6.0 COMMAND DESCRIPTION
The
commands
read/write. There are
multiple sector and inhibit
only
will
controller
the
try
operation
will
are organized
three
optional bits set with
imbedded
for
one
not
accept a new head address,
into
revolution, instead
previous command.
6.1
Control
6.1.1 Initialize
The initialize
characteristics
than
those used for all
Commands
command
of
the drives are
other
is
used
by
at
commands. They are listed in table
11
three groups:
seek. Refer
(1)
the
to
of
control,
certain
table
three.
but
the system to specify
each address. This
command
(2) read/write and (3)
command
2.
If
retry
If
imbedded seek
will use
the
to
the controller what the physical
codes:
is
inhibited, controller
Inhibit
is
inhibited,
head address from
has different parameters
6.
control
retry,
the
Table
6.
Initialize Parameter
Map
Parameter #1
Parameter
Parameter
#2
#3
7
I
I
7
7
I
6 5
I
6 5
6
4
3 2
I
I
4
3 2 0
I
I
0
I
Drive Address
Number
Set When Fixed
I
of
Maximum Cylinder Code
Moveable
Heads
are
Heads
Installed
o = 202 (fixed disk)
(floppy
77
1 = Future
Maximum Sector Code
disk)
Use
o = 128 bytes
1
= 256 bytes
= 512 bytes
2
3
= Floppy Format
4
5
I
2
3
0
I
Sector I nterleave Code
(See
Table
7)
The initialize command
on
or
a reset. The sector interleave code is specified
must
be issued
to
each drive
attached
by
this command and
to
the
controller
Section 6.1.1.1. The sector interleave codes allow for slow DMA transfer
place
without
Care should be
on
the
disk when a reformat
waiting for a complete revolution
taken
to
insure
of
that
disk is
the
code issued for
not
going
of
to
the
be
disk
on
a multiple sector operation.
the
initialize command matches
done.
6.1.1.1 Sector Interleave Code
must
be
A sector interleave code
tiple sector reads
or
writes
each sector transfer. Sequential sector transfers are
of
the
controller firmware:
The sector interleave code specifies
example shows an interleave code
Physical Sector:
0 1 2 3 4 5 6 7 8 9 10
19
20
Logical Sector: 0 7 14
24
31
Note
that
this interleave code has 4 sectors between consecutive sectors
the
track
but
only 3 toward
specified during an initialize command allowing
to
occur
without
the
of 7 with
21
22 23
21
28 1 8
24
31
4
the
end. This example
having
to
wait
not
possible due
one
revolution
spacing between logical sectors. The following
a 32 sector format:
11
12 13
24
25 26 27 28 29 30
15
22 29 2 9 16 23
11
18
25
5 12 19 26 6
is
given
to
show
to
timing limitations
14
that
must be chosen carefully.
after
is
discussed in
of
data
to
for
of
the
disk for
15
16 1 7 18
31
30
3 10
13
20 27
at
the
beginning
the
interleave code
a power
take
that
mul-
17
of
Several codes for each sector size
are shown in
the
following table:
option
that
give a
constant
number
of
interleaved sectors
12
Table 7. I nterleave Code
Sectors/Track I nterleave Code Interleave
32
32
32
60
60
60
60
104
104
104
104
16
11
30
20
15
12
52
35
26
21
2
8
3
2
3
4
1
2
3
4
6.1.2 Recal ibrate
A recalibrate will step the head arm towards track
indication.
seek
to
After
zero in
each step the controller waits for seek complete. This
that
the
controller does
not
calculate and
00
until
then
the
drive sends the track
is
different
issue
the
required
step pUlses. The controller will reset its cylinder register with this command. An
is
set
upon
completion
of
a recalibrate.
00
than
a
number
interrupt
of
6.1.3 Seek
A seek command will move the head arm assembly the required
position over
read
an
After issuing a seek
to accept a command
a seek complete result byte. Note
the
ID field
addressed track and select
to
verify operation, however, track
on
a fixed disk drive
to
another
drive.
that
the
the
An
interrupt
command busy bit
desired head. A seek command will
00
switch
is
controller will drop command busy and
is
set
upon
is
not
6.1.4 Terminating Sector Request
This command
bytes DMA transferred
sector for the last sector
the
with
and sector
defective ID found, an ID
The first three bytes are used
is valid after a read, write, search
to
the
CPU memory. The first three bytes are
the
controller operated on.
ID field for
bytes
that
sector,
the
read from the disk. Note
CRC error,
to
determine:
last four
that
or
a seek error.
Of
bytes
the
verify
last four
uata
If
an error occurred
transferred are the flag, cylinder, head
bytes
A) At what sector a search was met.
B)
At what sector an error occurred
Mter
DMA is complete an
ReadIWrite Commands
6.2
interrupt
Read and write commands transfer data
is
sector buffer (512 bytes)
with a generator polynomial
used in the controller
of
X
on
a multiple sector command.
is
sent and a good completion result
to
or
from CPU memory via DMA transfer. A full
to
16
+
X12
+ XS + 1 are appended
avoid data overruns. Two CRC bytes
for error detection.
number
of
cylinders
to
not
monitored
completion
for
errors.
of
the seek with
is
free
set with this interrupt.
command. There are seven
the
cylinder, head and
that
was associated
are only valid after a
is
set.
to
all records on the track
13
All
read/write commands, unless otherwise specified, will perform a seek
cylinder and head and search for the desired sector before attempting
data field. Any errors encountered during this procedure cause a retry (maximum
before the error
is
posted. Retry may be inhibited with a bit in the command code. Read/
write operations may be single or multiple sector transfers. An interrupt
transfer
6.2.1 Format Cylinder
A seek
is
complete.
to
the specified cylinder will be performed by the controller and the
to
to
read
is
set after
the specified
or
write the
of
two)
DMA
ID
fields
written according to the interleave code specified in the initialize command. All heads in
that cylinder are formatted. Data fields are
not
written. With the fixed head bit set all
fixed heads are formatted.
6.2.2 Write
A write ID command will orient
interleave code and write the ID field with the
ID
to
the field specified in the parameters according to the
DMA
data. The data field will not be changed.
For the fixed disk drives, a flag, cylinder, head and sector byte must be transferred. See
Section
head, sector, and a record size byte. Refer
set when command
6.2.3 Write Data
This command will write the data field
Data transfer from memory will begin filling the sector buffer before the sector
read/write head and
6.2.4 Write Data
This command operates the same
the beginning
6.2.5
A Read ID will transfer the first ID field encountered back
not perform an imbedded seek. This command
10.0 for flag byte definition. For a floppy disk four bytes are required; cylinder,
to
Section 10.0 track formats. An interrupt
is
complete.
of
the length specified in the initialize command.
is
under the
DMA
overrun will be checked during the write operation.
Special
as
Read
of
the data field.
ID
a write data except a unique address mark
to
the
CPU.
This command will
is
intended
as
a diagnostic and for alternate
is
written
sector assignment.
is
at
6.2.6
Read
Data
The specified data
data for
DMA
See
6.2.7
that
sector
transfer
is
Section 11.0 for retry conditions.
Read
Data
This command operates the same
beginning
6.2.8
of
Search
the data field
Data
This command will read the specified sector(s) and compare this data with the data in
memory.
transfer
Once the data in memory
is
required. Any hex
for equivalence. Special data fields will be ignored.
is
DMA
transferred
is
transferred and the special data found bit
to
memory.
If
complete for all sectors an interrupt
and
Special
as
a write data except a special sync byte
Equal
is
DMA
transferred
'FF'
byte
will not be compared; all others will be compared
a special sync byte
is
is
sent and result reg full
to
the sector buffer no further
is
encountered, no
set in the result. After
is
set.
is
written at the
14
6,2,9
Search
Data
Equa!
and
Special
Special data will also be compared.
6.2.10
Search
Data
High
or
Equal
A comparison where data on the disk
will satisfy this search.
6.2.11
Search
Data
High
or Equal
and
Special data will also be compared.
6.2.12
This search is satisfied
Search
Data Low or Equal
if
data
on
the
memory.
6.2.13
Special data
6.2.14 Verify Data
No
the
6.3 Control Read/Write
6.3.1
This command
to
Search
DMA transfer
Data Low or
is
included in
of
data will occur, however, data will be read
Equal
the
and
search.
CRC checked for errors.
Read
Diagnostic
is
used when an ID field
the
specified track and sector then skip over the ID field, and transfer the data field
memory.
is
of
greater binary value
Special
disk
is
of
lower binary value
Special
is
unreadable. When issued the controller will orient
or
equal
or
into
to
that
in memory
equal
to
data in
the
sector buffer and
to
6.3.2 Write Buffer
This command provides
equal length sector
memory. The sector address specified
The write buffer command writes the present contents
on
the
system with the capability
the
same
or
different drive without transferring
in this command will be a physical sector address.
to
copy a sector
of
the sector
sector. The sector buffer may be filled with a read data, write data
7.0
COMMAND
The controller operates
where all 4 drives may be seeking. In general
sequence
located
of
at
the CPU.
A) The CPU sets
B)
The CPU
the controller in
C)
The controller will read
D)
The CPU will
mand. Each time a parameter
the controller reads the parameter
PROCEDURE
on
one command
at
a time except in
the
following description gives
events for a command. The controller is designed
up
then
its DMA logic for
checks
turn
the
status reg for a zero condition and initiates the command,
sets
the
the
then
send
the
command and reset the command full bit.
required number
the
transfer
of
data
if
command full and busy bits in the status register.
of
parameters for the particular com-
is
sent,
the
parameter full bit in the status
it
will reset this bit.
the
to
the
case
be
on
one drive
data
through
buffer
or
to
the sPecified
verify data command.
of
a seek
to
the
used with
DMA
logic
command calls for it.
is
set. After
an
15
E)
When
the
last parameter
transfers data
set with
mi~roseconds.
F)
After
DMA
if
required, or if an error condition occurs before
the
result. Minimum time from last parameter
transfer is complete the controller sets an interrupt after loading the result
reg and setting the result full bit.
is
read the controller operates
on
the command and
DMA
to
DMA
transfer
DMA
an interrupt
is
100
is
G) The interrupt is acknowledged by
the
resets the interrupt.
H) When
8.0 OPTIONAL
The
4600
In addition there are 4
The data bus option
state data bus signals from even pins
the data bus
through 34. See Figure
8.1
The
DMA
directly to host
There are two jumpers
the
CPU reads the result, the command busy and result full bits in the status will
be reset and the command
has
HOST
cut
trace options
CPU
INTERFACE CONFIGURATIONS
jumper
is
accomplished by cutting 8 traces
outputs
Rand
W Jumper Description
request and
to even pins 36 through 50.
6.
(Also see Appendix BjSchematics).
DMA
acknowledge along with read and write accomplish data transfer
CPU memory
(R
as
and
is
complete.
that
provide a separate 8 bit input bus and an 8 bit
options
that
20 through
described in Section 4.0 and timing diagram, Figure 5.
W)
on
the SA4600,
acknowledge are the only signals required
host
CPU
is
enabled during acknowledge and data from the host CPU
controller on the trailing edge
of
acknowledge.
CPU
by
reading
the
result register which in
output
provide different DMA
that
34
and adding 8
Input
data
is
that
when removed, the request and
to
transfer data. In this case, data going to the
data
transfer techniques.
remove the bi-directional tri-
jumper
now received
plugs
that
on
even pin 20
is
latched in the
turn
bus.
connect
,----'-----
GROUND
J6
Figure 6. Optional Host
19
49
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
-DATA
-DATA
-DATA
I I
-DATA
CPU
I nterface Connection
IN
IN 7
OUT 0
4
6
OUT 7
o
1
2
3
4
5
6
2
3
5
16
8:2 RQ and A Jumper Description
There are two additional jumpers that provide further interface modification (RQ and A).
In the normal configuration data transfered to/from the controller
edge
of
acknowledge. (Refer to Figure S.)
is
latched on the trailing
The data being transferred may be accomplished on the leading edge
cutting the trace underneath the RQ and A jumpers and installing the jumper plug in the
alternate position. (See Figure 7 and Figure 7.1)
8.3 Jumper Description
Jumper F must be installed for proper operation.
9.0 SA4000
To
achieve proper operation from the SA4000 interfaced to the SA4600, certain jumper
options on the
9.
1 Control
9.1.1 Drive Select
The Jumper X must
be
jumpered.
DMA
REQUEST
DRIVE
SA4000 drive must be set. They are
PCB
DS
OPTION DESCRIPTION
be
opened and one
I corresponds to the controller drive
of
the four drive select lines
as
follows:
O.
of
acknowledge by
(DS
I,
2,
3, 4) must
~~-----J1
DMA
ACKNOWLEDGE
~,---_I
__
---JI
DATA
BUS
DMA
REQUEST
DMA
ACKNOWLEDGE
DATA
BUS
Figure 7.
Figure 7.1 A Jumper Option Timing (Write Mode)
RQ
Jumper Option Timing (Read Mode)
'
______
f
_I
_-----II
15
15
NS
MIN.
NS
MIN.
17
9.1.2
Byte
Clock/Sector
Mark
Jumper
ST
must
be
jumpered.
SC
must
be
jumpered.
BC
must
be
open.
9.1.3
Miscellaneous
Jumper
RY (ready) must be
jumpered.
Jumper
IX (index)
must
be
jumpered.
Jumper
T
(bypass
warmup)
should
be
installed.
Jumper
D must be
jumpered.
Jumper
E must be open.
Jumper
C (seek
complete)
must
be
open.
Jumper
S2 (index delete)
must
be
jumpered.
Jumper
S I (index
add)
must
be
open.
9.1.4
Sector
Counter
Options
The
SA4600
has
three
possible
formats
which
are described in Section 10.0
(format).
Depending
on
the
format
selected
by
the
user,
the
sector
counter
option
must
be set
accordingly.
Use
the
following table 8
to
select
sector
size.
Table 8. Sector Counter Options
32 SECTORS
20481024 512 256 128 64 32 16 8 4 2 1
MSB
IXIXI
IX)
IX)~ I IX)Xl~1
LSB
60 SECTORS
MSB
IXI><I><I----..-------
I><J
LSB
104
SECTORS
MSB
1Ir'~----:I
__
~
___
"'"
X =
JUMPERED
9.1.5
Cable
Termination
Description
In a multiple drive system, only
the
last drive
on
the
J 1 daisy chain cable should
be
ter-
minated. A
220/330
OHM
terminator
pack
is
located at location 3H. Removal
of
3H
unterminates
the
drive. In a single drive system,
3H
must
be
in place.
9.2
Data
Separator
Board
Jumper
C (sync
up
on
O's)
must
be
jumpered.
Jumper
D (sync
on
l's)
must
be open.
All
other
jumpers
must
be
configured for
the
host
system's individual requirements. Refer
to
the
SA4000
OEM manual
part
number
39005.
10.0
FORMAT DESCRIPTION
As
mentioned
in
the
introduction,
the
SA4600
is capable
of
formatting
four different
formats.
Only
the
three
formats for
the
SA4000
will be discussed.
Each
track
is
divided
up into
data
block
or
sectors. Each
sector
may
contain
128,
256
or
512
Bytes. A full
sector
buffer
is
provided so
that
the
host
interface
may
transfer
data
at a rate
compatible
with its own timing requirements.
Each sector
(Data
Field)
is
preceeded
by
an
identification
field (ID Field). The ID Field
contains
four
Bytes
of
information.
The
first
byte
is
a flag
byte
which
contains
a defective
sector
bit
(LSB)
which
is
set
by
the
host
system
when using
the
write ID
command.
If
a
sector is read
with
this
bit
set,
bit 0 of
the
result
byte
will
be
set.
(Refer
to
Table 5.)
The
remaining 7 bits may
be
used
by
the
host
CPU for special purpose flags.
18
The 2nd, 3rd, and
the controller
CPU
by using the read ID command.
At the end
of
4th
bytes are cylinder, head and sector bytes, These bytes are used
to
verify correct location
of
the data field and are also available to the host
the ID Field and Data Field, there are two bytes known
as
CRC (cyclic
by
redundancy check). This 16 bit binary number is a polynomial generated from the contents
of
the ID field
or
Data Field and
is
used
to
verify the data during a read.
At the beginning
is
used to flag the beginning
of
the ID field
is
a unique character known
of
the ID field and data fields.
as
a sync byte. The sync byte
It
is
also used by the controller
to align Byte Boundries.
A gap
of
15
bytes
of
zero's
is
placed between the end
the data field to provide a VFO lock
only the data field
Two types
of
is
changed-
not
sync marks are used
the
to
normal sync byte data pattern. A Hex
of
Refer to Figure 8 for a layout
the SA4600 format.
on
area since when a write data operation
ID
field.
flag the beginning
'DB'
is used
of
the ID field and the beginning
is
performed,
of
the data field. A Hex 'DD'
to
flag special data fields (user defined).
is
of
the
~~------------------------~~
OB
7
* = USER
= SPECIAL
DEFINED
DATA
Figure
8.
SA4600 Format
ii.v
ERROR
RETRY
The controller will retry certain error conditions two times before posting an error in the
result register. The types
A) Any
B)
C)
CRC error on an ID or data field.
Unable
to
find a sync byte for an
The imbedded seek on read
of
errors are:
ID
or data field.
or
write operations where the ID field must be read. The
retry may be inhibited with a bit in the command.
12.0 PHYSICAL DESCRIPTION
12.1
P.C.
Board
The SA4600 will control four SA4000 fixed disk drives and four SA800/8S0 floppy disk
drives, and consists
Connection to the disk drives and the
19
of
a single 12.5" x 18"
CPU
PCB.
is
made via card edge connectors.
12.5"
I
DRIVE
R/W
DRIVE
R/W
DRIVE
R/W
DRIVE
R/W
4
3
SA4600
2
1
CONTROL
(COMPONENT SIDE)
UNIT
OPTIONAL
FLOPPY
CONNECTOR
J8
TEST
MUX
4000
MUX
Figure 9.
P.C.B.
Physical Layout Drawing
CPU
J6
INTERFACE
12.2 Connectors
Three types
of
connectors are required: A 50 pin edge connector, a 20 pin edge connector
and a 4 pin plug for power.
12.2.1
50 Pin Connectors
50 contact edge connectors are provided for the SA4000 multiplex cable, the SA800/850
interface and the CPU interface. The dimensions for these connectors are shown in Figure
10. The pins are numbered 1 through 50 with the even pins
is