Sharp SM5M2 Datasheet
SM5M2
- 1 -
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etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
DESCRIPTION
The SM5M2 is a CMOS 4-bit single-chip microcomputer operated on 3.0 V single power supply.
This microcomputer integrates 4-bit parallel
processing function, ROM, RAM, display RAM, 15stage divider, 2-kind of interrupt and 4-level of
subroutine stack. With a built-in LCD drive circuit
for a maximum of 136 elements, a 2-mode standby
function, voice synthesizer and a melody generator
circuit in a single chip, the SM5M2 permits the
design of system configuration with a minimum of
peripheral components. It can be used in a variety
of products from handheld equipment to electrical
appliances, such as hand held games with voice,
and also achieves low power consumption.
FEATURES
• ROM capacity :
3 072 x 8 bits (For main program)
64 k x 5 bits (For voice)
256 x 6 bits (For melody)
• RAM capacity :
130 x 4 bits
(including 34 x 4 bits
display RAM)
• Instruction sets : 51
• Subroutine nesting : 4 levels
• I/O port :
Input 1
Output 6
Input/output 7
• Interrupts :
Internal interrupt x 1 (divider overflow)
External interrupt x 1 (INTA)
• Built-in voice synthesizer circuit (APCM) :
Number of phrases : 256
Voice ROM : 64 k x 5 bits
Bit rate : 25/35 kbps
Number of coded bit : 5 bits
Sampling frequency : 5/7 kHz
Generation period : 9.1 to 12.8 s
• Built-in main clock oscillator for system clock
• Built-in sub clock oscillator for real time clock
PIN CONNECTIONS
• Built-in 15 stages divider for real time clock
• Built-in LCD driver :
136 segments, 1/2 bias, 1/4 duty cycle
• Built-in melody generator circuit :
Melody ROM : 256 steps
Generating time (at 32.768 kHz) : 32 s (MAX.)
• Instruction cycle time :
25.9 µs (MIN.) (at 70 kHz ± 10%)
61 µs
∗
(TYP.) (at 32.768 kHz)
∗
When using the clock with the system clock.
• Standby function
• Supply voltage : 2.4 to 3.3 V
• Package : 72-pin QFP (QFP072-P-1010)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
(NC)
S
25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
16
17
18
39
38
37
S
11
S10
(NC)
19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
72 71 70 69 68 67 66 65 64 63 62 61 60 59
58
34 35
36
57 56
55
GND1
VOA
RESET
V
DD2
CK2
CK1
TOSC
S
0
S1
GND
S
2
S3S4S5S6S7S8S9
(NC)
VOCS
OSC
OUT
OSCIN
VDSP
H0H1H2H3
GND
S33S32
S31
S30
S29
S28
S27
S26
INTA
(NC)
P0
0
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
T
F
VOICE
VR
V
DD
SM5M2
4-Bit Single-Chip Microcomputer
(LCD Driver)
72-PIN QFP TOP VIEW
SM5M2
- 2 -
BLOCK DIAGRAM
RD
PC
B
SB
P0 P1 P2
SR x 4
RE
RF
A
CC XC
HC
RAM
96 x 4-bit
ROM
3 072 x 8-bit
DISP RAM
34 x 4-bit
ALU
LCD DRIVER
VDSP
VOA
H0
S0
H1
H2
H3
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S33
GND
V
DD
VOSC
T
RESET
CK1
OSCOUT
OSCIN
INTA
F
P2
2P21P20P13P12P11P10P03P02P01P00
BLEEDER
MELODY
CONTROLLER
MELODY ROM
6 x 256-STEP
INTERRUPT
CONTROLLER
OSC
VOICE ROM
5 x 64 k-STEP
VOICE FLAG
EXPANDER
D/A
CONVERTER
5 to 8-bit
VOICE VR
DIVIDER
RC
P33
HARDWARE
RESET
CIRCUIT
OSC2
FOR LCD
REAL TIME CLOCK
OSC1
FOR
VOICE
SYSTEM CLOCK
CK2
VOICE ROM START ADDRESS
TOSC
IFA
IFD
Nomenclature
ACC : Accumulator
ALU : Arithmetic logic unit
B : RAM address register
C : Carry flag
HC : Common signal generator circuit
IFA : External interrupt flag
IFD : Divider overflow flag
RC : Voice starting address
OSC
IN,
OSC
OUT : Oscillator for LCD and real time clock
P0-P2 : Port registers
P3
3 : Voice flag port
PC : Program counter
RAM : Data memory
RD, RE, RF : Mode registers
ROM : Program memory
SB : Stack B register
SR : PC stack register
X : X register
CK
1,CK2 : Oscillator for voice and system clock
SM5M2
- 3 -
P00-P03
PIN DESCRIPTION
PIN NAME I/O FUNCTION
GND, VDD, VDSP, VR I
Power supply pins. The VDD, VDSP, VR pins apply a positive supply with respect
to the GND.
T, TOSC, VOSC I
LSI chip test pins. Cannot be used by the user. Connect T and TOSC to GND.
Connect VOSC to VDD.
RESET I
Input pin with built-in pull-up resistor. Hardware-reset the LSI chip when a Low
level signal is input. Normally, a capacitor is connected between it and GND to
form a power-on reset circuit.
OSCIN, OSCOUT I/O
I
O
Crystal oscillator pins. Connect a crystal oscillator accross [OSCIN-OSCOUT ] to
form a clock generator circuit.
RC oscillator pins. Connect a resistor across [CK1-VDD ] to form a clock generator
circuit. CK
2 is used to test its clock out.
Voice output pin. Output the contents of a voice ROM.
F
CK1, CK2
Voice
O
Melody output pin. Outputs the contents of a melody ROM with standard 12
musical scales (555 to 2 114 Hz) in two octaves.
H0-H3 O Pins for the LCD's common signals.
S0-S33 O Pins for the LCD's segment signals.
INTA I Input pin for external interrupt. The IFA flag is set at the rising edge of INTA.
O
Output ports. The P0 ports are an output port. The accumulator ACC can be
transferred to this port by instruction.
P10-P13, P20-P22 I/O
P1 and P2 are I/O pins which can switch to input or output pins in 4/3-bit units
by instruction. They can be used as output pins when configured for a key
matrix. The SM5M2 is forced to hardware-reset when all of P1
0-P13 pins are High
level. (By mask option)
SM5M2
- 4 -
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage VVDD – 0.3 to 4.0
Input voltage VI – 0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Source output current for each pin
IO1 2 mA 1
IO2 2 mA 2
IO3 2 mA 3
IO4 2 mA 4
Sink output current for each pin
IO5 2 mA 1
IO6 100 µA 2
IO7 2 mA 3
IO8 2 mA 4
Total source output current IOH 10 mA
Total sink output current IOL 10 mA
Operating temperature TOPR 0 to 50
°C
Storage temperature TSTG –55 to 150
°C
NOTES :
1. Applicable pins : P00-P03
2. Applicable pins : P10-P13, P20-P22
3. Applicable pin : F
4. Applicable pins : H
0-H3, S0-S33
NOTE :
1. Use the crystal oscillation circuit
RECOMMENDED OPERATING CONDITIONS
Oscillation Circuit
OSCIN
OSCOUT CK1 CK2
Crystal
C
1 C2
R
OSCIN
OSCOUT CK1 VDDCK2
Crystal
C
1 C2
NOTE :
Mount the R, C and crystal as close to the LSI chip as possible to minimize the effects of stray capacitance.
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage VVDD 2.4 to 3.3
Instruction cycle TSYS
Crystal+CR 25.9 to 31.7
Crystal 61.0
µs
Oscillation starting voltage VOSC 2.0 V 1
• Crystal oscillation (frequency = 32.768 kHz)
• CR oscillation (frequency = 70 kHz)
NOTE: In case of using RC resonator, crystal is also required.
Crystal : 32.768 kHz
C
1 = 15 pF
C
2 = 15 pF
Degree of fluctuation frequency : ± 10%
(V
DD = 3 V, TOPR = 25°C)
C
1 = 15 pF, C2 = 15 pF, R = 1.0 MΩ
SM5M2
- 5 -
DC CHARACTERISTICS (VDD = 2.4 to 3.3 V, TOPR = 0 to +50°C)
PARAMETER
SYMBOL CONDITIONS
MIN. UNIT NOTE
Input voltage
VIH1 0.8 x VDD VDD
V 1
VIL1 0 0.2 x VDD
VIH2
V
DD
–0.25
VDD
V 2
VIL2 0 0.25
Input current
IIH1 VIH = VDD 30.0
µA
3
IIH2 VIH = VDD 30.0 4
IIL1 VIL = 0 V 25.0
5
10
11
-IOH1
IOL1
VOH = VDD – 0.5 V
VOL = 0.5 V
VOH = VDD – 0.5 V
VOL = 0.5 V
500
1 000
500
25
1 300
2 000
1 300
90.0
980
740
200
µA
6
-IOH2
IOL2
Output current
IO1 D= 1FH
7
IO2 D= 0FH
IO3 D= 01H
8
IOP11 CRRUN1 120 150
IOP12 CRRUN2 110 130
9
ISt11 CRSTOP1 15.0
4.00
3.00
50.0
40.0
30.0
26.0
26.0
4.0
15
30
40.0
15.0
13.0
100.0
80.0
60.0
52.0
52.0
15.0
Supply current
ISt12 CRSTOP2
CRSTOP3
XTALRUN1
XTALRUN2
XTALHALT1
XTALHALT2
XTALHALT3
XTALSTOP
VDD=3.0 V
VDD=3.0 V
µA
kΩ
ISt13
IOP21
IOP22
ISt 21
ISt 22
ISt 23
ISt 24
DCOM
DS
NOTES :
1. Applicable pins : P10-P13, P20-P22
2. Applicable pins : OSCIN, RESET, T, INTA
3. Applicable pins : P2
0-P22
4. Applicable pins : P10-P13
5. Applicable pin : RESET
6. Applicable pins : P0
0-P03, F
7. Applicable pins : P1
0-P13, P20-P22
8. Applicable pins : VOICE, value of external resistor = 2 kΩ
9. Measurement conditions in detail are mentioned in the
tables next page.
10. Applicable pins : H
0-H3
11. Applicable pins : S0-S33
VDD
VOA
GND
LCD wave form (EXAMPLE)
MAX.TYP.
Output impedance
SM5M2
- 6 -
STATUS
CRRUN1
CRRUN2
CRSTOP1
CRSTOP2
CRSTOP3
0 1 1 0 ON ON ON ON ON ON
0 1 0 ON ON ON OFF ON ON
0 1 0 OFF ON OFF OFF ON ON
0 0 0 OFF ON OFF OFF OFF ON
0 0 1 OFF ON OFF OFF OFF OFF
0
1
1
1
CR + X'TAL Standby Mode
STOP P33 RF1 RD2 CR X'TAL CPU Voice LCD Divider
STATUS
XTALRUN1
XTALRUN2
XTALHALT1
XTALHALT2
XTALHALT3
XTALSTOP
0 0 1 1 0 OFF ON ON ON ON ON
0 0 0 1 0 OFF ON ON OFF ON ON
0 1 0 1 0 OFF ON OFF OFF ON ON
0 1 0 0 0 OFF ON OFF OFF OFF ON
0 1 0 0 1 OFF ON OFF OFF OFF OFF
1 0 0 0 0 OFF OFF OFF OFF OFF OFF
Only X'TAL Standby Mode
STOP HALT P33 RF1 RD2 CR X'TAL CPU Voice LCD Divider
NOTES :
• When CR = OFF, CPU and Voice are OFF.
• When Divider = OFF, neither LCD nor Melody is in operation (undefined).
• STOP = 1 stands for executing STOP instruction.
• HALT = 1 stands for executing HALT instruction.
NOTES :
• When CR = OFF, CPU and Voice are OFF.
• When Divider = OFF, neither LCD nor Melody is in operation (undefined).
• STOP = 1 stands for executing STOP instruction.
SM5M2
- 7 -
SYSTEM CONFIGURATION
A Resister and X Register
The A register (or accumulator : ACC) is a 4-bit
general purpose register. The register is mainly
used in conjunction with the ALU, C flag and RAM
to transfer numerical value and data to perform
various operations. The A register is also used to
transfer data between input and output pins.
The X register (or auxiliary accumulator) is a 4-bit
register and can be used as a temporary register.
It loads contents of the A register or its content is
transferred to the A register.
When the table reference instruction PAT is used,
the X and A registers load ROM data.
A pair of A and X registers can accommodate 8-bit
data.
7
3
0
003
EX instruction (swap)
SB register
BM registerB register BL register
Fig. 1 Data Transfer Example Between
A Register and X Register
Arithmetic and Logic Unit (ALU) and
Carry Signal Cy
The ALU performs 4-bit parallel operation.
B Register and SB Register
• B register (BM, BL)
The B register is an 8-bit register that is used to
specify the RAM address.
The upper 4-bit section is called B
M register and
lower 4-bit B
L.
• SB register
The SB register is an 8-bit register used as the
save register for the B register. The contents of B
register and SB register can be exchanged through
EX instruction.
Fig. 3 B Register and SB Register
Fig. 2 ALU
The ALU operates binary addition in conjunction
with RAM, C flag and A register. The carry signal
Cy is generated if a carry occurs during ALU
operation. Some instructions use Cy : ADC
instruction sets/clears the content of the C flag;
ADX instruction causes the program to skip the
next instruction. Note that Cy is the symbol for
carry signal and not for C flag.
3
A register
3
X register
0
0
EXAX instruction
4-bit data 4-bit data
ALU
Result of operation
Areg
c
SM5M2
- 8 -
Data Memory (RAM)
The data memory (RAM) is used for data storage.
The RAM capacity consists of 130 x 4-bit (include
34 x 4-bit display RAM).
Display RAM, which outputs data to an external pin
for driving the segments of the LCD. Therefore, by
writing data to the display RAM, the LCD can be
driven at 1/4 duty (1/2 bias) to enable automatic
display of the LCD.
As shown in Fig. 5 the display RAM is connected
to segment outputs port from S
0 to S33 which
correspond to the LCD common outputs H
0 to H3.
Data M
0 to M3 for one column of the display RAM
is output pins as a LCD drive waveform which
corresponds to outputs H
0 to H3. As a RAM, the
display RAM operates exactly the same as other
RAMs.
0 1 2 3 4 5 6 7 8 9 A B C D E F
0
1
2
3
4
5
8 S0 S2 S4 S6 S8 S10 S12 S14 S16 S18 S20 S22 S24 S26 S28 S30
9 S1 S3 S5 S7 S9 S11 S13 S15 S17 S19 S21 S23 S25 S27 S29 S31
A S32
B S33
Fig. 4 RAM Organization
∗
The area surrounded by the thick line represents the display RAM where S
0 to S33 corresponds to the segment
output.
BM
BL
SM5M2
- 9 -
Fig. 5 Relationship between The Display RAM and LCD Segment Outputs/Common Outputs
H3 H2 H1 H0
M3 M2 M1 M0
(RAM bit)
BM = 1000
(Register)
BL = 0000
BM = 1001
BL = 0000
BM = 1000
BL = 0001
BM Register
BM = 1000
LCD
Segment
S0
S1
S2
drive circuit
Common outputs
BM = 1001
BL = 1111
BM = 1010
BL = 0000
BM = 1011
BL = 0000
S31
S32
S33
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