Sharp PC-7200 Service Manual

SHARP

PC-7200

SERVICE

MANUAL

CODE:

OOZPC7200SM-E

PERSONAL

COMPUTER

MODEL

PC-7200

~-------------------CONTENTS--------------------~

CHAPTER 1 SYSTEM SPECIFICATIONS ....................................................

1-1

CHAPTER 2 THEORY

OF

OPERATION ......................................................

2-1

CHAPTER 3 FLOPPY DISK DRIVE UNIT ....................................................

3-1

CHAPTER 4 HARD DISK INTERFACE .........................................................

4-1

CHAPTER 5 HARD DISK DRIVE ..................................................................

5-1

CHAPTER 6 ADJUSTMENT ..........................................................................

6-1

CHAPTER 7 DESCRIPTION OF

LSI

.............................................................

7-1

CHAPTER 8 CIRCUIT AND PARTS POSITION DIAGRAM .........................

8-1

PARTS LIST & GUIDE

SHARP CORPORATION

I

PREFACE

SCOPE

This

manual

contains

the

theory

of

operation

for

the

PC-7200

microcomputer

system,

and

is

primarily

intended

for

service

technicians

working

in

the

field

or

in

repair

centers.

In

addition,

the

manual can

also

be

used

as

a reference document

for

technical

____

personnel

__

requirjng-

__

knowledge-~of-this-

-cdmpliteCTfis

co-il-f8i1fs-of

this

manual

are

as

simple

and

clear

as

possible,

however,

users

of

this

manual

shOUld

be

899uainted

with

computer

hardware.

About The Manual

This

manual

is

divided

into

seven

chapters:

CHAPTER

1 PRODUCT DESCRIPTION

Provides

general

information

on

the

computer

such

as

specifications

and

external

and

internal

configura-

"

tions.

CHAPTER

2 THEORY

OF

OPERATION

Describes

the

logical

and

electrical

functions

of

each

cirCuit

block.

CHAPTER 3 FLOPPY DISK DRIVE
CHAPTER

4 HARD DISK INTERFACE
CHAPTER 5 HARD DISK DRIVE
CHAPTER

6 ADJUSTMENT
CHAPTER

7 APPENDIX

NOTES: The 7200

Manual

is

generally

concerned

with

the

PC-7221

product

configuration

which

includes

the

high

density

(2HD) floppy disk drive and 20MB hard disks drive.

PC-7201/720217221

are

common

except

the

difference

showed

by

the

next

list.

The

difference from PC-7201, PC-7202 and PC-7221

PC

7201

PC

7202

PC

7221

FDD

1 x

FDD(2HD)

2xFDD(2HD) 1

xFDD

HDD

none none

1

xHDD

FDD,HDD

FDD FDD

FDD

Indicator

FDD/HDD

FDD

HDD

SPECIAL SERVICE TOOLS

PARTS CODE

PRICE

TOOL NAME

BANK

1

UKOGM2018CSZZ

_.3~

...51

(CPU.B0286)·extrac1ionlool

2 DFLP-10B3ACZZ BF

Diagnostic

media

3

DFLp·1084ACZZ

BF

Aging

test

media

1. UKDGM2D18CSZZ

o

o

2. DFLP-1 D83ACZZ

3. DFLP-1 D84ACZZ

CHAPTER

1.

graphic character fonts.

• Standard 640K·byte O·RAM.

-

PC-7200

SVST-EM-SP-E-GlF-ICAT-ION~-

1-1. FEATURES

----

--.

-Reaf-time--eleek-{-R:r.c} . ..which storss-Jnformatioo related to the

The

PC~7200,

provided with numerous special features and

functions, can be used as a single·user or multi-user computer. It
is a powerlul office tool that can satisfy the diverse demands for
high-speed data processing and large-scale memory management

for

the

high-end personal computer

and

low-end multi-user

configuration.

80286 Microprocessor

The computer's central processing unit (CPU) has an 10MHz i6-bit
80286 microprocessor, permitting upward compatibility with 6088/

8086 processor operation. It performs versatile data processing at

a faster speed than the 8088/8086 processors.

Memory

The computer has 640K bytes of Random Access Memory (RAM)
and 64K bytes of system Read

Only Memory (ROM). ROM contains
IPL, BIOS, and diagnostic programs as well as graphics character
fonts.

LCD

Display

A large-capacity LCD with 640 x 200 pixel configuration.
Features a backlight and adjustable tilt feature for better visibility.

Built-in Interfaces

For the input/output

of

data to and from the computer, various

peripherals have been provided, including a

5-114",

high-density

floppy disk drive, a built-in

20M byte hard disk and hard disk controller
(PC-7221 only), and a RS-232C interfaces, and a Centronics-com­patible printer interface.

Functional Expandability

Besides the standard features above, the functions

of

the computer

can be expanded by mounting optional devices such as the

80287
Numeric Processor Extension, or by installing any of various option
boards in the internal options slots.

Modem Card

Designed exclusively for the PC-7200, and directly attaches to the
main board.

Operating System

A DOS (Disk Operati,ng System) allows the user to communicate
with the computer and its peripheral devices, performing data
transfer and managing the memory resources of the various
equipment.
In

the single-user system configuration

of

DOS, MS-DOS version

3.2 is used. This version permits use of a wide range of commercially
available

application programs. The computer can also be run under
XENIX 286 Version (multi-user configuration) and GW-BASIC,
version 3.2.

IBM Compatibility

Most of the application software, peripherals and options designed

for the

IBM PC,

Xl,

and

AT

can also be used with the PC-7200.

1-2. SYSTEM CONFIGURATION

Figure

1-1

illustrates system architecture. As demonstrate, the
system's main components include the system unit and the keyboard
unit.
The system unit includes the main PCB, floppy disk drive, hard disk
drive (PC7221 only), and optional adapter.

The System Unit

The main PCB is composed of the following components:

• 80286 16-bit microprocessor

• Control Circuits

• 64K-byte (two

32

byte chips) ROM which contains the power-on

diagnostic program,

BIOS, initial program loader (IPL), and

1 ~ 1

system configuration and updates the date and time even if the
computer power

is

turned off.

• Keyboard interface

• Centronics-compatible parallel printer interface

• Floppy disk interface which can control up to

two

double-density

(20)

or high·capacity (2HO) floppy disk rives.

• Asynchronous serial interface which conforms to the EIA
RS·232C

standard.

• One options slots - This slot can use both IBM

PC/XT

compatible,

B·bit type. and IBM AT compatible, 16·bit type.

• A large-capacity LCD with

640x200

pixel configuration, as a

standard feature.

• Modem card designed exclusively for the PC-7200 directly

attaches to the main unit as

an

optional device.

A high density (2HD) floppy disk drive is installed as a standard
feature.
Mounted

at

the center

of

the chassis is a 3.5 inch hard disk drive

with storage capacity

of

20M~bytes.

The power supply unit has six levels

of

power output:

+5V,

-5V,

+12V,

-12V,

-15V

and AC120V. Because these voltages are

stabilized with

the

switching regulator,

the

power supply takes less
space and is light in weight.
Inside the system unit, there is a Ni-Cd battery. This battery backs
up the real time clock, permitting it to maintain information

related

to the system configuration, and to update the date and time, even

when the power is down.

SYSTEM CONFIGURATION

<

SYSTEM

u'~"CC"':....

___

~=====,--;~~-:-:

I

'.

__

•••

;1

. .

: 80287 :

L_~

_ow,

.

~

4.61'115: ',,"0"1"

~

,",e,.

0,

r===;:~~$~~:;===1

IBM

CARD

[

2"

16

b"

lull

size slots

1 " 8 bit

lull

size sici

L_-'

__

...l.

__

.L_....J

1" 8 bU

hall

size

slCI

Figure

1-1

The Keyboard Unit

The keyboard is connected to the system unit using a 6-Pin Modular
jack connector with a

coiled cable. A one chip microprocessor is

used as an interface with the keyboard unit and

the

system unit.

When the power

of

the system unit is turned on, the processor

automatically checks its

own

RAM and ROM

by

executing

the

self-diagnostic program.

~

~~~~~~~~~~'~

..

~~~~~~~~----------------------------------------~

1·3. MAIN COMPONENT FUNCTIONAL:DESCRIP.

TION

VI;''.

-

<!

;:))'1->.);,.;.

i""';

');;

J 1

~I':

:)

)ri':

Sl

~~::~'

,;;)";

;i'·,

':-;'.-;1';)11';;

~:\:'-~'h

J'.,-':","

..

.1,

--;\

~;~'~'-'"

~~~:;

j.

__

o_,q

;J

crTh,ls,

;se~JqR

q~S_CIJQ.es-

tt"!~,

fui1GtjQns'

of

Jhe

tWd

main

~compon'ents

_

,

sySt6rri

~nJt'!inCt'

key[)oara:'1

!"),-

';

..•.

-

,;.'~;

,.'

.,'

:"-:

.. 1

;',UiJ_

,:i.;

-;;

I~:',

1

,:l-:j

-'\1"'>

•

_.

;,'),-'

-;~

L,!IJ',-~ii10;_\

,'/i3 -

'-r'):':;

··~.:n.-,.'l'-)\I

(1) LCD

,Jfr;<

-4

D:)

@i{ID

'-';:L~;XJir@;:;i_~~J~'~::);;~~;;~

:::~1:~\\:;".~~'~\

~'

-'::_-=.~~'..!J~

®1r'''

'11['

'"")

I

".J

,I_~

JJ ' I

'>®_'~I"':

<

n"*tlllr+~Jlh.:-:e-;:-j,."*l',~::::;;~::;:,,

,

;11Ulf381

.;;f1.

'~J

®,

i-'

h-d1"'''0,1

• _

".

-<,.' ,-.11".,

i-.')

'(I"

'~;~!,:;

'\;;;,'JJ

~~~b2,g=~7':""":~~l'i';~~;@._:~J""

:-1

"

Figure 1-2

(2)

Display

standby

indicator

This indicator is I

used

to

indicate that

the

EL

backlight

is

out

during

time:

out or

CRT

mgde,

(3) POWER

stalus-

indicalor

(4) FDD

and

flDD

51alus

indicalors

When

,the

computer,

i3

y

cesses' the floppy

disk'

or

hard

disk,

the

~el~vant-,in~ic_ator

lights

~p-=-

___

.

(5),t:CD'C~-~fri.~t:a(d~~t:knob"

I - J

This

knob

is-proilioed

-to

adjust the LCD contrast

to

afl

optimum.

(6) EL

backlighl

brig~lnass

COnlrol

k~Ob

• . - ,

This

k_fi(jb,-i~:ptovid~~

to

adjust the bfightness of

the

EL

backlight.

Normally, set

to

the'

iniddle'position. ' ,

,

..,

l l

(7)

Display

background

select

switCf1-'_'l',

~:,,:

"<,,,_,

_<',1

~',_''':

:,,,,.,Th[s,switch is

provided_

to

select the'Lco"bacK'grourid

'mode;

·;~"-'\NbRriAA(~r"REVER~rE.

';':

_'-J'_':~:-!j':'-j;',

:::~-',

:-""".1"

,.1,

':,-~-;-,',.J::,;:~:;;

i:".'

_,;:'J.'.

,,:,

,)--,

',:I:-'!'

:'1',"

;r,F

(SIleo

iui"'a~~

,!

',.

•...

....,',

.......

.'",

'-';

:"

."thf~

,~'n¥

sta.i1dJ~

',-provid~~i,

to

1dj~'st

'tK

e

;kngi~

'df

tli~

dfs~i~y

:,,,

"'sC-r~eii

to'~~n'bptimuh~:;angl~

jtd:~y~

~'osIt-ibh:,-1

_

':':1'",;1:-;0,'

-,-;,}

I::.

"11':

,;"

'

,',

d'-k~

1

=2

(9)

Keyboard

cable

compartment=-'

'\

"_

~

---'~',

The

keyboard -

cai)!,$.j

is-

hOJ:ised

-'in

thig::6c1mparjmep!-when

the

keyboard

cable-js-~notj

inl

use~!

!

':;;

,J,

,-

;j

~:~~i~'---;~~

,j~

:'(.10)~Option'card:5!ot,~;!-11'.1"i;jn

,:,',',

h.;''-:''J-

,;,_)~;

)'-1

Ji!-:

!!

'1':'liLThecIBMd?.G/Ali

ioptior.r'card~

is,:mounted-Jn

thrs,sJot.,~,

,;j!!

-,

" I

-1~'1

,~b;-;:;;;i.-J;)

,)-':-

)\/!;)

,l,;;

l/>'L.:i:='

li.-)

h;:;

:

~');

;-\,ti':" iU:!8';v,X!

J:l1

i

1;):Keyboarctlatch :;,,!

--'~-J,;_)i

'---Jf,

-;

i;'ll.-:'!,"

,1VFl

>i;"i-,

iJ'3~)q,~

rt!:

;)'::'

i

':Used

'f€JI:-latch

tt:'l'el

keyboaJjdl.fO

tHe,mainc,uniti.l

l-fo9"

I

:,i:r

i

(12)

Floppy

disk

drive

a 1/3-height, 1.2M byte floppy

disK;dri~e'isomou"iell.;;~c;,).,i

j'

;-{-;i

:;,:-L'jf~)'

;'1

;~;,r~

,1

j!'i;)\

itr1!!

~''-w.~?':lJ'Y

':'Jrir1-.i~

J1'.Jj'iLifT~':n

'JI:"

'(13)

KEVBOARD~conneClio~;j@Cki"""

."".

_ ..

,_

.....

33SJ3

t~

_-,?,;i

Connec;:t

';3,

cOile'd,:'cableJ,with,p!ug

,fr.om,th~..:keybQar.dj''ilrtitlrirr:lto

this

jack.

'~D~">'J:Jo:ij

D,~31>;',,;,7-:)(J':l

-d.'

~l'~J'~i

I~)--'\l;

YI,',~_::

(14)

Keyboard

cable

This

cable

is

used

to

interface

the

keyboard

with

the

R:C£72€lO;~:i

;!1,

..

:-)1'"

--,-,,~,

',);'"

S'·,,'

:'l!J:-'

':::;i';'-i

/ifj,;,,J

c,;:j.-!

1-,

'''-I'';;J

'ojl'·'

,"'i'(~5):Keyl:ioarl1~j(J,,-!;

',,'1I'lFi.')i\;i

'/rl'-)

i;.-,),,'

11

I',

,,::-.j

'-,'wi

)iXj

twc

-.1.;::;)

~.;I:;fliil')

.c-,

l;":'j

',:'

Cill-J'!

'')11_'

":-,lL-],J'

:-"1-1;0'

:,:<;j,:3

fi,

(16)

CPU

clock

select

switch

",In'

This

switch

is provided

to

select

the

CPU

clock

speed;

6MHzl8MHzll0MHz.

(1:)

0'

'--'iii:~l'i:;:'"

,;,'

"_'_J---'

~~'i',.J

,rr'

:,1,)"

,'"

;'1--'

I':~C

(17)lDisplay):inode;'seleCt:switch":;"~

'~'l

",]1.::

i-,i'~

b,'

'11,i

This

switch

is provided

to

select

the

display

mode;

CGA,

MDA,

or

other.

In

the

case of

other,

use

of

th:e:'display:opti6F1n~arcf

is

,requiredJ1:

i!J:"'i!

'J'),

!',,;:

(18)LCDICRTselectswitchc]

c,

'i,

.,;

Thisswitch.isiprovided

to

serett

thedisplaYldevic,e;'lCD_or

CRT.

(19)

Sound

conlrol

knob

This

knob

is

provided

to

co~tro~:intermat'~p-eaket'NoIUme-~

\,(20}SU'Pply-voltage;select-sWiJcf:t!:"J' i

,'j:

(',

j;-~')

)'j

•

.

-~

This

switch,

is

praIJ.ided

:to

select

the!power.--s,upplyl

voltage;

,100

or

200V. .

-.:1"';

:'~,;i-_1t'l'

"jJ.-r

(21) AC

power

outlel

:-,;

i.;

'"

)')),';

j

PlugJ8I

po...ver

cord;of,

a'

petipherals;unit

eto.,_iotd

this

:outr.e.k.:1fbis

outlet is controlled

by

the power

switch.

When

the

'power"switch

is

turned

on,

this outlet is

powered,

and

when

the

power

switch

is

off,

this outlet

is

not

powered.

This,"Qutlet

hahdles!AO current

'in

a--rnaxitnum!of

O:4A.'-!8'e

_careful',ribt-to1exce:ed

this~yarue'

When

;~singJthiSl

outlet· ',i:' '-;',

.. "

(22) AC

power

inlel

"Insert

'AO,

paW€H"l

cord,

with:

j;3.ck

,jnto;]thisIQutle.t.

,-,I' li:--;' ,

(23) ColorlMonochrom<\,CRTccanneclor

0,

. ,

Ccirinettr:a

9.,.pio

__

plug' ,with

'cord

'suitlllble-Jor-,this

!connector

to

make

a connection

between

the

computer

and

a color/monoc-

hrome

CRT

monitor.

(24):Pdntel",c;onnector:

'>

"1

.

J-

J

j':

, To print

oUt;data,',infoiTna:tion,

or,programs/cohi;1ecl-1a,printer's

cable

to

this connector.

..

i~:(~6)jMhdEMA'ElEP~'dN~:~l~c;~<_~i',j,

.'~':,

":::~;

::r,:_',',,:l',~

"",;"

'_'"

:,l

'"

1'--1,'

,,!..,

,,,,,,,1.1,,)

,)

'_J

"'::'1,;

""'\"--ji

--J,;1

ThIS

Jack

IS

connected

to

the telephone jack,

when

the

modem

card

option

is

used.

I~

.'(;,

,:qU,)

:iri',;,

i'..J"~;:

I,-,q,;,'"

;ij',:':

~,~

):/,)

:l>c!

"'J.,

",1

I--';-j'--,-,: iiE,,'),m;

i.,;;':-~l

~~nj,':::

'1],,1

:i,"

;1:,::)I:(1

__

;(~

(28) Power

switch

The POWER switch turns the computer

on

and off. When turning

on

the

-system, itlm--the136wef-of--f.hei3er.ipR&r

...

li.---OD-fjrsUben

___

_

turn on the computer power.

(29)

Cooling

fan
Prevents the computer against excessive heat generated during
operation.

Do

not block this ventilation opening by positioning

the computer too close to a wall etc.

Keyboard Layout

EXP: USA·English

110"

III'"

III

FS

III'"

IIE~LF6

:::]

~

110'7

IIIFB

III'"

IIIFlO

III

Fll

111m

II

I

Crt

-<

r-

P"j

H=

En~

Figure 1-3

1-4. SPECIFICATIONS

The specifications below apply to the system unit and keyboard unit.

1-4-1. System Unit Specifications

Main

Logic

CPU

Processor

....

80286

Clock frequency ...

6MHzl8MHzl9.6MHz

MPX (Option)

Processor ... 80287

ROM

Element ...

27256 EP·ROM

x2

Capacity ... 64K bytes
include

IPL, BIOS, diagnostic program and graphics character

fonts

RAM

Element... MOS

LSI

256K x1

bitD·RAMx16,

64K

x4

bitD·RAM

x4

Capacity ... 640K bytes

OPTION

Element ... MOS

LSI

256K

x4

bit D·RAM

x8

Capacity ... 1 M bytes

Clock/Calendar ... HD146818 (MC146818 compatible) battery
back-up
DMA

... 7 channels (8237A·5x2)

Interrupt Level ...

15 (8259x2)

1-2. Specifications
1-2-1. Physical specifications

The physical specifications for the PC-7200 are shown below.

• Main

unit

(includes

keyboard)

(1) Dimensions

Width: 410mm (16.1")

Depth: 160mm

(6.3')

Height: 243mm (9.6")

1

-3

PC-7200

(30)

Expansion

connector

Used for connection of the expansion box.

1-3-2. Keyboard

Figure 1-3 shows the keyboard layout

forthe

PC-7200. The keyboard
has the standard QWERTY layout with 10-programmable function
keys, numeric keypad/cursor movement keys and special keys. The
three status indicators show the

ON/OFF status of the Caps

(Capitals) Lock, Num (Numeric) Lock, and Scroll Lock keys.

Page

UF

rail;]

Down

=

N=

I

,/

Lock

)--

r,-

Is--

H~

J-'-

,""

5

-

, ,

End

j

JI:"

]

(2)

Weight

Net:

7201

8.Skg (18.8 Ib)
7202 9.3kg (20.S Ib)
7021

9.Skg (21.0 Ib)

(with the keyboard)

(3)

Power requirements

• 100V type
9Q-132V AC SO/60Hz

1.0A (includes output for CE·700P)

0.8W ":l

z.

""A

T,

• 200V type

'14,.-

'if)

lulfrr

18Q-264V AC SO/60Hz

• Cable length:

2.0m (78.7")

(4)

Environment

Temperature:

•

;-

S

~

6

~

~

t;j

10 to

35

degrees C operating (50 to 95 degrees

F)

-28

to 60 degrees C storage

(0

to 140 degrees

F)

Humidity;

-

+

I-

Enter

20 to 80% operating with no condensation; up to

90%

storage

1-2-2. Component specifications and characteris-

tics

The PC-7200 consists of the following components, whose
specifications and characteristics are shown below.

• KEYBOARD
(1) Unit dimensions

Width: 4fOmm (16.1")

Depth: 182.Smm

(7.2")

Height: 37.Smm (max.) (1.S")

(2) Unit weight

1.0Skg (2.4

Ib)

(3) Coiled cable

Diameter: 1Smm (0.6")
Length:

270±10mm

coiled state (10.6±0.4")

1,500mm

stretched

state!

(4'11")

Weight:

SSg

(1.94 oz)

(4) Style

~--

.

• Low profile

• Cylindrical key top

• Step sculpture

.

(5»

Keys , ,

,

"102keys(Lncludingthree

keyswitl)

L~P»)

;

(6)_Layout·

.~.

'"

,!,

J,'

• I "

. ,.) See

FiguJe~_t~3.

(7) LEOS

'>"

Color: Green

Key name:

U,Y,H

SW.X

F

I

I

I

B

I

,1'1:;

"Caps Lock" Maj Bloc Mai Shift Lock,

.~-l·Numi::ock"

Verr-Nu~

BlocNum

Nurii[oc~

,_

i '

____

~·~crOIl,~?Ck'"

Arretdefil

____

BI?cScorr'

~cr911

Loc/{

, (8) Rollover

N_-key

rollover _

-'('g).

Key

sw,it~h-operaiing'-fO:rce:

--

'S'Q.±30:g

: '

60±25

gc

i

--'.'

6~±25'g

• '

(10)'

KeytopPulLfoice

'I,

k!f":

,'''-~:;'

..

(11) Lifetime . .

.

3J]OO;QOO

op~ratiqns

(keys with LED)

10;000,000 operations (keys without LED)

(12)

tiitadjustment

3-6-9-

degrees-

(13)

~Iectrical

characteristics

Power

reqlJirements:

1aOmA

+ 5V

DC

'Signal

level'

TTL

•

LCD

(1)

Unit dimensions

Width: 282.5mm (11.1'1
Depth: 142mm (5.6")
Height: 9.3mm (366 mils)

(2) Unit weight

325 g

(0.717Ib)

(3) Backlight panel

Dimensions

Width: 276.5mm (10.9")
Depth: 131mm

(0,2")" • '.

Thickness: 1.3mm

(rrlax.)

(51

milsy

Weight: 55 g (1.94 oz)

(4) Effective

display size

Width:

239.96mm (9.4")

Height: 104,96mm (4.1'1

(5)

Graphic fbrinat 1

'.

Horizohtaf:

64D

dots

Vertical: 200 dots

(6)

T

exf

format

Row: 25 lines

.

6;J!'urrin::'

80·-t:har~cters/iihe

Character:

ax8

dots

(7)iCd

cohnector

20

pin

2.S4mm'-pitch'

connector

(9) Backlight connector

4-pin,

2.S-mm

pitch nylon connector

(10) Electrical characteristics

Power requirements:

0.1

mA

(max.)

130V AC (max.)

• FLOPPY DRIVE

Refer to CHAPTER 3 (page 3-1).

• HARD DISK

Refer to CHAPTER 5 (page 5-1),

, '

,

1-4

•

R$-232C,

,(1)lnterfa~~,

, .

EIA RS-232C (voltage

interface)

(2)

Transmission

method

• Asynchronous only

.'

,Fu!!_:or:h~lf:duplex"

(3) Baud

rate,

,.

.

.,

..

.

....

.,'''',

110,150,300,600,1200,2400,

48000.r

~600

(4) Data length

7

or

8 bits

(5)

Parity

"

.~-

None, even, odd

(6)

Stop bit

- :

~·--+or

2 bits

, '(,7) Connect";

25~pin

YiY

-type'

shei1)iial~

pqnnect,or

,

(8)~EI~ctri0al·characteristics

_=.§lgnaJ.level: ~ _._

,_."

...

VOL

'=

-~5V

to' -

15V

> •

VQH

T

+5Y

\0

+)sV

VIL·~

-=-3V

to·-15V·

VIM ~ ,,3\1

to,

+15V

Sf"le:

'-'-

l

te'vel

.

Data

I

VOl,~ll

)

I

VOH,

VIH

0

•

PARALLEL

INTERFACE

(1) Interface

Centronics-type interface

(2) Connector

-"

I

Congition

,

Mark'

SpacJ

2S-pin

"0"

type shell

female

connector

(3)

Electrical characteristics

';

!

Signal' level: TTl:

VIL ~ less than 0.8V

VIH =

more

than

2.0V.

VOL ~ less than

O.4V

VOH = more

than

2.4V

• SPEAKER
(1)

Size

Diameter:

29mm

(2.24")

Thickness: 6.8mm (0.74"

(2) Impedance

81l.

(3)

Variable frequency

670-3,OOOHz

(4) Input

pQwer

Rating:

O.

I W

Maximum: 0.15W

• CALENDAR
(I)

Functon

,

Cont.wl

OFF.

ON

, ,

c..',:

,co

;

• Counts

and

presents

year,

month,

date,

hour,

minute,

s~cond,

and

day

of,

the.

week

'

• Automatic correction 'for

days-per-n]qff~h

,.

•.

A.u~o.W<?Ji.c.

_I.~ap-:y~~r

90r.r~ctiqn_.,

•

BatterY

backup

-,

,

(2)

Accuracy

Mean

monthly error: ±45 s

(3) Battery

Type: 3-51 FT

',.

,.,.

Enclosed type Ni-Cd

re,c~a(gea~Ie

battery

Capacity:

..

qOm..;\H

,_

..

,. ":',."1:,-' -

.-"

Celi:

three'celis'(:i.6v) . "

Charging method:

ContinuolJ~.

,trickl~:_c~~rg~,

(4)

Charge/backup characteristics

-.'

-'

'"

-'

-/

.'

Charge

time:

SO

hours

(0

to

100%)

Backup

time:

500

hours

(approx.

20

clays)

I\l

I

MAIN BOARD

HD

I/F

BOARD

~

~

~

roME

~

,---------

-----

-,

I

~

.-----------'I

MO~~

B D

§~

~

\

r--v1

(HAYE

pa~.)

0

300

bps

~

~

( 82P.36P

IBM

18

bit

BIIS

Slot)

( SZP.36P

mM

18

bit

Bus

Slot)

( 62P IBM 8

bit

Bua

Slot

)

(

62P

IBM 8 bit

BUB_

Slot

(hall)

)

I

SYSTEM LOGIC

<J[

I I

I
L

BOOB6

>or

H a

~

'bids

~

l'i

~~A

"oW>

"'''

""'"

..

,"

;--

;M/IO

6/8/10

MH,

cg~

IDGH

D"TA

BUS

..-

,

l'EAilK

015

~

~;"'f

1iUSY281 0'1

''''''''',''

"""

WI

~

110281

~~

~,~

JL

00

HOLDA

OLK

CLK286

r

~b'DY

~

~

00--"

SYSTEM

CONTROL LOGIC

8237)(2

"'"

""'"

LS612

SC4751

M-"

QIO"

fltl~

RAM

(64KB)

"",.,

DB_IS

00-7

ADD

BUS

ADD

BUS

mUH

OAT"

BUS

LOW

DATABUS

COMMANDilUS

~f-H--

'~

00--1

00--1~

M">--.

CASL.C"SHI

WE.OE

"0-8

- -

;~

,----IIF

~

i-

-

--l

_.

n I

I

3~'

~

§

• I

~

L_

,

a ...

F,a.

e1'·

...

If---

EXPANSION

BOX

T -

DiSPLAY

INTERFACE

LoGlC-

- - - - - - 1

I I

I

I

";l, I

CRTJ1:CD

I

"-'

'"-./

CRT/LCD

I

~

~

___

,

~=i)

I

I

I

,--,------fTTl

I
I

I

I

I

I

I

I

CLRIGM

110

CONTROL LOGIC

I'

PD765

ClK24M

8259)(

2

I
I

r;:::J.-",~CLK19M::

CLK14M

~

r'

I

I

I
I
I
I

I

I

I

I
I

I

""

L_

,

I

UM/seaK

I I LCD

1-

______________________________________________________

I FDD

Figure 2-1. System block diagram

I

~

go

~~

-n"'D

'-1

c:l>m

"tI::D

~~

~

a:>

f

N

,

~

,

~

!II

-<

!II

-!

m

i!:

I

m

r-

0

0

;0;

C

;;

Gl

:II

:I>

;:

~I

0

·'"

,:i

,"--

~.

"~',

--I

-

"-

-

I ,

"

~i~--,'-

~

,.

__

:!,l

-.

;,;

'-

..

,'

_ i

;

I,

. i '

·000000

I

09FFFF

640KB

standard

RAM

on

main

board

System Memory

,

OFd~o~ ! 64~B:

,!

:'

:

i:

64KB:BioS_Ro'M_on,main

board

-

-;

'.!,

-

1'--" : ',--

B/~S'"B;o-~(-

~,Duplicated'~c~de

assignment

at

OFFFFF-

.~.

address

FFOOOO

100000

_T~

II~-

--

•.

-'

i

,

lFO.oOO
200000

I I

FD5FFF

'

FEOOOO

I

FEFFFF

·lMB

R~M

,

14MB'

R~~

61KB

'

~~~

'I~'

E~'pansion.

RAM

on

main

board

(op~ion)

Optio'nal

RAM

area

ion

I/O slot

Reservd

for-RAM

on

I/O slot

2-1-3. 1/0

Mapi'

,',.,

'!

:;

..•

;,'

!

IJ~',"

The

CPU

:cohtlr6l~ithe--;-iIO.(ad&ess,

spCJ,pejh~~:gh"wi1ic~:

t~e

C!?V!

-;

1

-<*>

~Dn,ly,\one

i,Vi-MMI

~all

be

enabled

bYIH/W

sWitch

selectIOn,

accesses

IId~ort~:bf

~ict~rhJI

d~vl¢~s.JB~-~e!arei64K"(;i'scre~e

8~b:it

:

ports

in

this

i/o;

cidtlresel"area,

and

any

adjaCent!

two

...

p-otts-can

be

:

-,:

,:;e,XG:e'pi-.op~O~:::b~a~d+·.~~

.'

~'-:~-l

used

as

a,

1e-~il

P~rt.

Table

2-2

shows.

the-.I/O

map-:"

'.

: '

-~r1~bl~

'2T?

;/O:~~~

110

Address

0000
0001
0002
0003:

0004
0005
0006

'
0007
0008
0009
OOOA
OOOB,
OOOC
0000
OOOE:
OOOF,
0020
0021

!

I:

.

,I

__

._

.•

Write

:

CHO

base,

curren~

address

:

CHd

base, curren(W:ord:

count~

;

CHI

base,Olcu-rrenf:

.;ddress

I

'~Hl

base,

9urre~tl

word count

:

t~2

base,

¢~t,r~mj

address

!

Ctb

base,

turrrent

word count

i ' I

1..

___

-'

____ . _

,.

QH3...bas.e

..

current.addiess_

--

cH"f

base

,currenf-warp 'count

, ,

Command register '

~

~,

Request register

:

Single

mask

register

Mode

register

, : !

Clear

byte painter

flipLflo~

Master clear "
Clear

mask

register

All

mask

register bit,

ICW1,GGW2,GCW3

JCW2,

ICW3,

ICW4,

OCWI

l.~",C":'

i,

'(j

I

,-

I'il

--'1

' ••

Cl;lo'

,9Ll(~ent

la~dress!

"

/,CAO'

~~i~ent

!~orcrt:6Lnt

,

:_~~t'Hl

qJr~enf

aQdress

',.'

,---

"CH'~

~~rr,eAf:$-9Jd

CO~IJ't

: ' 1

_c~:

c~rr:ent

!a~dress

I

CH2

cyr~ent

,~ord

count:

, J ~ " _

CH3.

.current

~addres.s_

'

CH3'c~r~enl

i\fora-

cou-rii' -

Status i !
X

...

~.

·X-~~

~,

.. ··,,,,'X·

" ,

X;

i

,~'

i

T'~mporary

)I'

·x

--

-

IRR"ISR-/IAter~upt

·Ievel

IMR

OMAC

#1

,"

---,

I/O

Write

_

Addr..ess_

0040

Counter

#0

load

0041

Counter

#1

load

0042

Counter

#2

load

0043

Control word

0060

Data

write

0064

Command

write

0061

Port B write

0070

(NMI mark register)

0071

Data

register

write

0087

DMA

channel

0

0083

DMA

channel

1

0081

DMA

channel

2

0082

DMA

channel

3

0088

DMA

channel

5

0089

DMA

channel

6

008A

DMA

channel

7

008F

Refresh

OOAO

ICW1,

OCW2,

OCW3

OOAl

ICW2, ICW3, ICW4,

OCWI

OOCO

CH

base,

current

address

00C2

CH

base, current word count

00C4

CH

base, current address

00C6

CH

base,

current

word

count

00C8

CH

base,

current

address

OOCA

CH

base,

current

word

count

OOCC

CH

base,

current

address

OOCE

CH

base,

current

word

count

0000

Common register

00D2

Request mask ragister

0004

Single mask

register

0006

Mobe register

0008

Clear

byte

painter flip - flop

OODA

Master clear

OODC

Clear mark

register

OODE

All

mask

register

bit

OOFO

Clear math copeocessor busy

OOF!

Reset math coprocessor

00F8

Math coprocessor

I

OOFF

01FO

Data ragister

01F1

Write

precomp.

01

F2

Sector

count

01F3

Sector

number

01

F4

Cylinder low

01F5

Cylinder high

01

F6

Drivelhead

01F7

Command register

0020

I

0207
0278

Parallel data

write

0279

X

027A

Parallel control

Counter

#0

read

Counter

#1

read

Counter

#2

read

X

Data read

Status

read

Port

Bread

Address

generator

Data

register

read

DMA

channel

0

DMA

channel 1

DMA

channel

2

DMA

channel

3

DMA

channel

5

DMA

channel

6

DMA

channel 7

Refresh

JRR,ISR/lnterrupt level

IMR

CHO

current

address

CHO

current

word

count

CHl

current

address

CHl

current

word

count

CH2

current

address

CH2

current

word

count

CH3

current

address

CH3

current

word

count

Status

X
X
X
X

Temporary

register

X
X

X
X

Math

coprocessor

Data

ragister

Error

register

Sector

count

Sector

number

Cy1.nder

Yow
Cylinder high
Drive/head
Status

register

Parallel deta raad
Status

register

Parallel control

2-3

Read

PIT

-

PC-7200

Keyboard

I/F
(8742)

Port B

RTC(NMI

mask)
DMA

page

register

PIC

#2

DMAC

#2

NPX

(Option)

HOC

(option)

Game

1/0

(Option)

Parallel
printer
port

2

(Option)

, .

I/O'

"

-

~-,-_

:

Write

.-

Read-

.,.

;

i

_1_-":,

'\1

Address

. '

02FO

-

f~

-

b-uffer

-

-

,

RX

5UII.,(0)*

.

Serial

..

':

i

"

!

I,

',',1

02FO

Divisor

latch

LSB(O)

*

•• , "J

,pivisor

latch

LSB(O)*

po~t

2

02F9

Divisor

latch

lSB(

1)

*

;

piyisor

latch

LSB

( , ) *

.'

(fa:ctory

02F9

Interrupt

enable

register(O) *

,Interruupt

enable

register( 1) *

~ption)

,

i

'olFII'

:]IJi.errupt

fD

register--

:-r-rffettupt-ID--register

,

"

i

;'11

02FB

Lin,e

control register

,

.'t,

"

: line

control

register

02FC

'-'~1Abem

control

register

Mc;ldem

control register

om)'

.

Li.ne-statu's·

ragrster

,

pr)e stetLis

-registe-r

!'-

OlF~:,1::

,--;M9,dem

status register

---_.

-

~ode

rTf

'statITS-register

i

02FF

! R,eserved

Reserved

-,

*A

-nurriber -enclasecf"in(

)shows the divisor

r~-t'~h-_:a'~ce~s

'bit.

0300

,-,'

J

:.-.

,

:

Proto

I

type

'"I,

'

031

F

,

,'.I:

'

bQard

,

,

(Option)

0360

,

~eserved

I

"

, ,

036F

, -

0310

' "

~aralJel

data write

....

,

~,P-aTallel

deta

read

Parailel

0379

X

,Status register printer

031A,

'

~arallel

control

Parallel

control port 2

0380

SDlC

I

bisync. 2

030F

(Option)

03AO

Bisync. 1

I

(Option)

03AF

,

03B4

68845

inbex register X

CRTC

,

03B5

68845

deta registre

68845

deta register

(mono-

03BO

CRT

control port

X

chro'me)

03BA

X

CRT

status port

03D4

68845

index register X

C~TC

03D5

68845

deta register

68845

deta register

(color)

03DO

Mode

contrl register X

03DA

Color select register

X

03DB

Reset light

pen

latch X

03DC

-~ ,SE!t

lignt

pen

latch

X

".

.

03F2

.JFgital output register(DOR) X

FOG

and

03F4

Command register Status

register

FDD

ifF

03F5

Data

register

Data

register

03FI

Drive control register(

DCR)

Digital input registerCDIR)

03FO

IX'buffer

RX

buffer(O) *

serial

om

"'

-Divisor latch

LSB(O)

* Divisor latch lSB(O) *

Portl

03F9

Divisor latch

LSB(

l)

*

Divisor latch

lSB(

1) *

03F9

Interrupt

enable

register(D) *

,Interrupt

enable

register(1) *

03FA

Interrupt

ID

register

[nterupt

tD

register

03FB

Line

control register

Line

control register

03FC

Modem control register

Modem

control register

,

03FD

Line

status register

,Line statas register

OltE,:

....

,';§toaem-~stiifus

re-gister

~odem

status registter

,-

J,""

03FF

,B~served

~eserved

. .

*A

numbr enclosed In( )shows

the

dIVIsor

latch access bit .

g-4

2-2. MAIN

PWB

OPERATION

The main PWB whose dimension is approximately 11.8 inches x 15

-inches

is

mo-unted

on

the

cliassis-

onhe

system-

Urii[ Figure

2:-r--

shows a functional block diagram of the main PCB.

2-2-1. LSI Circuits (Figure 2-1)

The

LSI

circuits

used

in

the main

PCB

are described below.

(Abbreviations are used

in

the remaining section of this manual

when describing these LSI circuits.)

• Central Processing Unit (CPU): 80286
A

16~bit

microprocessor that can directly access 1 M-bytes of

memory address

in

the real mode, 16M bytes in the protect

mode, and 64K bytes of

I/O

address.

• Numeric Processor Extension (NPX): 80287

This optional

LSI

circuit

is

a coprocessor for performing arithmetic

operations. The 80287 can

be

installed into the internal 40-pin

IC

socket

on

a user's request.

* SC4751

The SC4751 has the following functional devices:

•

8237A~5

Direct Memory

Access

Controller

(DMAC)

Controls data transfer between

1/0

devices connected to the

DMA channels

and

memory without a CPU intervention.
The computer uses two DMACs and they are connected in
cascade.

• 82288

Bus

Control

Unit (BCU)

This chip generates signals necessary for controlling

1/0

devices

and memory

by

receiving the

SO,

S1,

and

MilO

status signals

from the

CPU.

• 82284

Clock

Generator (CG)

Generates clock and reset signals necessary for the CPU. The
82284 also controls the

SRDY (Synchronous ReaDY) signal and

ARDY (Asynchronous ReaDY) signal to

be

sent to the CPU.

• LS612

Memory

Mapper

High order address register file for DMA which is used to expand
the DMA address space from 64KB to 16MB.

•

System

Control

Logie

(4K

gate array)

Controls the system memory (ROM, RAM), memory refresh, hold
conversion, and 8-bitl16-bit bus conversion.

* SC4752

The SC4752 has the following functional devices:

• 8259A Programmable

Interrupt

Controllers

(PIC)

Accepts interrupt signals from the

1/0

devices, and gives

priori~

to one of them. The interrupt signal selected by the 8259A

IS

sent to the CPU. The system employs two PICs, and they are
connected in cascade.

• 8250 Universal

Asynchronous

ReceiverlTransmitters (UART)

Controls the RS-232C interface. Parameters for communication

such

as

baud rate, word length, stop bit, and parity can be

controlled by the

CPU via these

LSI

circuits. A second UART is

available

as

a factory option.

• 765

Floppy

Disk

Controller

(FDC)

Controls the built-in floppy disk drive.

•

8254~2

Programmable Interval

Timer

(PIT)

Generates

an

interrupt signal when the predetermined timer
becomes active, and determines the frequency of the signal to
be sent to the speaker. The 6254-2 also generates trigger signals
for DRAM refreshment.

• Other

110

control

logic

(3K gate array)

Controls the printer, 80287, and display time out.

2-5

PC-7200

•

8t42

Keyboard

Controller

Controls data transfer between the CPU and the keyboard.

• 1288 LCD/CRT

Controller

Controls the video memory data to display on the LCD

or

CRT.

• 1294 CGA

Controller

Controls. color display mode in conjunction with the 1288.

• 1292 MDA

Controller

Controls monochrome display mode in conjunction with the 1288.

• 27256 Read

Only

Memory

(ROM)

The computer uses two PROMs whose storage capacity is 32768
wordsx8

bits. They contain the power-on diagnostic program,
BIOS, 128 character dot patterns in graphics mode and the floppy
disk bootstrap loader.

• 27128 Read

Only

Memory

(ROM)

Contains the character fonts for CGA and MDA.

• 41256 (41464) Random

Access

Memory

(RAM)

A 640KB RAM area is provided on the main board, which consists

of 16 chips of

256Kx

l·bit

dynamic RAM (DRAM) and 4 chips

of

64Kx4·bit

DRAM.

• 41464-10 Random

Access

Memory

(RAM)

A 64KB RAM area is provided on the main board for the video

memory.

A 48KB RAM area is not used.

2-2-2.

CPU

(Figure 2-2)

The computer uses the 80286 microprocessor. Figure 2-3 shows
pin assignments for the

80286, and Table 2-3 lists pin descriptions:

CAP 2

ERROR

ausy

N.C.
N.C.

INTR

N.C.

NMI

V

..

PERE(l

READY

HOLD

HLDA

COD/INTA

M/W

AO

AI

A2

eLK

v"

RESET

A3

LOCK AI3

Figure 2-2. 80286 pin assignment

015

-00

'I

l')ili'!Ii'l

,-

};;'~l:-r,

.'

.- -:-:'11,-,1'1

\~(

'_i~iQOJ',ti~!:Ii~c!~~;(

fi1

c~:)il

ill"'l!;

;i

,~il

ij)']';

i

j.

iJ

9H~r~ti,~.I?)

8~

Itry\t3f.~~386

begins after

,a:~fnGf'P~tO)Qr([)W}fransitiOf:i'O'f.,.·RESEl':)

;::Th'eii

HIGH

j

foJ

l:OWi;ttansiti6n

.'l~jQt

RESJ;:,Ti

:mu§tl

~;~,.~ynchronous

to

inEi'r-~¥st~iTP

cr8clf!'

1Appfoxrm~h!lyr'50'::sys1e'm

~'adCkjcYcles·

-are':requli"e-d

by

the'

CPU

for interanl initializations before

the

first

bus

cycle to

fet~R'-b;-~cba~Ef':Hm;

th-e

tp3iw'~r-'::i:in

-:

tin)

1i!'Jr"

;;-:':exec'U'ti6fii1tBcfres'S\''is

performed.

14.

Ji'"j

·)n;.;

/\.o;J )

l~YI

~tf1oj

: -)j:/V

~C6\v

1'ti

'

FifGF·fr'fr~l,sition

of

RESET

synchronous to

the

system clock will end a processor"·.c.ycle,.at

I

~

'_'">s.'&

(;\,;;

tj'"

'r;,')~;:-~~

'>.o-xni,

i"ij

:';"Ji-~~~:

~;~~~~'i~'~'~~~jJO

~OW

transiti~n

of

the

C!OCk.

·lh"~~:~-?;~:·t~

"I;l\~.Ij'

~f.'!r.~mo.n

..

~,f]1~"~-,S~T2!P;!l;}l-:P.~i:

,~

",'"

lJ

' ;li1;J.i":

,'j,]

~~',-;:T',

-,'.j;-

~:f)

;=-1nVT(

,~,a.~~~_~~~9~9~-tJ~\!r,t,

system clock,

however,{:._J[lltBiS)

casecJthcaonoJ::be~_p(e~ejer"mrne9':'Y",hl.ch;p.ha:~');!';'Slf

:;,)

':J:;;

li',";/";'

LJ)

;\',

\;-;

'j.

E ,1:-,

~)

j; --•

A9~>.pmc~~,~F!rj

QJC!c~'Jwill

occur

durinItJ,tHe':ne~f\-systeiir:clbtj{.!·per'iod}'.;Sy(rChtdr:lCiuSi

-lOW.;

to

.HIGH

,tran'sitidns

;·,q~;ij:£S;~T

:

ar~

l

,re,Q!"!!red

only for syste

ms

wh'ehjYtPle!~~roc-~:s)sOr

~'ero~l(':iri

us:tl

b'E!'

'ptia'se;,'gyrl'chrono\fsl,-to

ClK

\J"

;'-a1:-

.,'"

: ' I j ) 1 f;,

"-1'-:

~~,.

015 00

-'

51

36

'"

'

i-"

,7.:"?':

)1

1 0

-18

~

1-~.3,4-'

4, 5

another clock.

'i

b'!!:-'-l,---;, , ,

-->:'

,'J

--'<i.'\;"1:<;

L':J)

<:H-':J

~:)jj)'ilf:n:'

J:-I'

!.;

~;.,

]3:;

~~):

;\

Sys:fem~

olobk':ProYides:'the fundamental timing for

80286

systems.

It

is

divided by

two

inside''t'ri'e'

'CP'U

;

;~r

.

,i;~"'i

,-:,~

::,::;~0'~~,~,~~r~,t4

'~e,)!d,l::essor

clock.

The

internal

divide-by

two

circuitry,:-,s~9.:,qe'I~~YDch5q~i~~~~;

tp_ja_p

&Jt_e~qal

l'

-;

,:

'cloCK

)gerieratclr'jj"y a lOW to

HIGtLtr;~F);;;jti91l

.9nli,tJ1!L~~S,~)LiIlPJ-!t-..n)d

_+--,r:j;L:~

,3-)i.,j'; -"';:'

1 ,:

I/O

o

'.

Q ,

o

Data

Bus

inputs data during memory,-:I/O.' and interr.tfpt 'acknoWledge

r.ead'

cycles;,,0l:ltputs:,da_taldurjng

1

~;"D0~~

~nd

1/~"wr~~

cycles.

The

data

bus

IS

active

HIGH

and

floats to

3-state

OFF

'during!

blisnold

ackno,wle,dge.

IBlIS-'Hi~\rEnable

indicates transfer

of

data

on

the upper bytes

o't

the data bus. 015 08.

Eight-bit

.-_,1

;'

.'

,~,

__

oriented-

dev:ic8$-,

assigned to the upper bytes

of

the

data

bus

would

norn;rclUIl,:_!.l.se-'.BHEjto~con:.dition

chip

selec~,

1u,I'

nctidns.

BHE

is

active;

LGW

ahd'-floats ,ta,

3'''-,st~te

OfFliii:lurihg.

:'b~~,

·h~ld'-~~Ckri~,~;e:<;1~'~.

'o"'!I'"

'::"1--,,

" .-"n" .

I::,

1

BHE~--V:alue

" ,

'l

L

L

L

L
L

L

H
H
H

H

H

H

H
H

M/iO

L

L

L

L

H

H
H
H

L

L
H
H
H
H

BHE

and

AO

Encodings

'~);'

'J,lWord

transfe',,', ' '1:

>'"

"')jJn,~:

H Byte

translEWbn'i,upper;'h~lf

of; dati

-bus,

W1-5

~:D8'¥;

,

L Byte transfer

on

lower half

of

data bus (07 -

DO)

H Reserved

S1

so

Bus

Cycle Initiate-if"

,:J,

t

,'J

L L 1

~

h;

}')j';';

.ID~~!,r;~p,~,:..ctqMo;~}~.q,~~

J)

ld~_

':,;' ,

;. \ ..

hI!

L !:i

-IIH;

'i,'11

,R,e,~e.~v-!;!,d\"T;J"-·

H'
H"

L

L
H
H

r:_~

_'l'.d,;_

"H

Re.s,erli,ed,,1(;i

,.:;;,-.):

I!

;Ii':

,:~j:-,:

'i.l,

i

l'

',)

None,~)rrib'twa

tshitos:"cycle-"

H:;

"

"!'-::J

!~'(

I).,::

If

A 1 = 1 then halt;

els'e,Js'h'ut'doWHl

s

'~.iJ

J1J.si:,,\.---

Memory data read
Memory

data';JY{~ji.W'I~:;:\:'

'~:l'~:';it~:

:: , ..

",

::·~,;j],::./Ti

None; not a status cycle

L

II

117:1:

H

L

H

L

Res~'~'l'9]9

i~,

,!,

I

'-:,'n":>h;;

')]:j:

':,Itrj:;;~']f)~q

.l-

),B~'-;

')Hl;n;l~;tlOijr~adrjJ

JjJ~I'/v

,_;l,I,j,'

'lj!!,.',i,:

'J,'

,;'<','

)i!'JU

fPi

;,:r;'.11.1:.

'-11:J

)cll/.O-,w:r.itel'l)

;:U

",;'1.j,r:');'J:J

;;,1:.,

,lV!};-:

,_»ITHJyj

Hi

'.

p;

-'

~r

i,.'I;~,

NO'n'e;:j-rIM"ai'staiti~',;'dycle

;1.

:-,-r

':V;)

,)J

J:

'.J

-.

.-j

L L Reserved

L H

H

H H

Signa!

Pin

No.

I/O

_---MJ.J1L-

0

CODIINTA

66

0

LOCK

68

0

READY

63

0

HOLD

64

I

HLDA

65

0

INTR

57

I

NMI

59

I

PEREQ

61

I

PEACK

6 0

BUSY

54

I

ERROR

53

I

CAP

51

I

-

PC-7200

Name

and

Function

M.eJn.Q.r.Y.::l1~_.dls.tiugujsh~

~mQ.a_--,!ccess

frolT!

1[0

~c9.es:s.

_If

HIGH.during

Is,

a memory cycle

or a halt/shutdown cycle

is

in

progress. If

LOW,

an

I/O cycle or

an

interrupt

acknowledge

cycle

is

in

progress.

M/TTI

floats

to

3-state

OFF

during bus hold acknowledge.

Code/Interrupt Acknowledge distinguishes instruction fetch cycles from memory data

read

cycles,

Also

distinguishes interrupt acknowledge cycles from I/O cycles. COD/INTA floats to

3-state

OFF

during

bus

hold

acknowledge. Its timing

is

the

same

as

M/iTI.

Bus

Lock

indicates that other system

bus

masters

are

not

to

gain

control of

the

system

bus

following

the

current bus cycle. The

LOCK

signal may

be

activated explicitly by the

·LOCK~

instruction

prefix

or automatically by

80286

hardware during memory

XCHG

instructions, interrupt acknowledge, or descriptor

table access.

LOCK

is

active

LOW

and floats

to

3-state

OFF

dUring bus hold

acknowledge.

Bus Ready

terminates a bus

cycle.

Bus

cycles

are

extended

without

limit

until

terminated

by

READY

LOW.

READY

is

an

active

LOW

synchronous input requiring setup and hold

times

relative

to

the

system

clock

be

met

for

correct

operation.

READY

is

ignored during bus hold

acknowledge.

Bus Hold Request

and

Hold Acknowledge cOntrol ownership

of

the

80286

local bus.

The

HOLD

input

allows another local bus master to request control

of

the

local bus.

When

control

is

granted, the

80286

will

float its

bus

drivers to

3-state

OFF

and

then activate

HLDA,

thus entering

the

bus

hold

acknoVlledge

condition.

The

local bus will remain granted to the requesting master until

HOLD

becomes inactive which

results

in

the

80286

deactivating

HLDA

and

regaining control

of

the local bus. This terminates the bus

hold

acknowledge condition.

HOLD

may

be

asynchronous to the system clock. These signals are active

HIGH.

Interrupt Request requests the

80286

to

suspend its current program execution and service a pending

external request.

Interrupt

requests are masked whenever the

interrupt

enable bit

in

the flag word

is

cleared.

When

the

80286

responds

to

an

interrupt

request,

it

performs

two

interrupt

acknowledge

bus cycles

to

read

an

8-bit

interrupt vector that identifies

the

source

of

the interrpt. To assure program

interruption,

INTR

must

remain active until the

first

interrupt acknowledge cycle

is

completed.

INTR

is

sampled

at

the beginning

of

each

processor cycle

and

must

be

active

HIGH

at

least

two

processor

cycles before the

current

instruction ends

in

order to

interrupt

before the

next

instruction.

INTR

is

level sensitive, active HIGH,

and

may

be

asynchronous

to

the

system

clock.

Non-

Maskable

Interrupt

Request interrupts the

80286

with

an

internally

SUPPlied

vector

value

of

2.

No

interrupt acknowledge cycles are performed. The interrupt enable bit

in

the

80286

flag word does

not

affect

this input. The NMI input

is

active HIGH,

may

be

asynchronous

to

the

system

clock, and

is

edge triggered after internal synchronization.

For

proper recognition, the input must have been previously

LOW

for

at

least four

system

clock cycles

and

remain

HIGH

for

at least four

system

clock cycles.

Processor Extension

Operand Request

and

Acknowledge extend

the

memory management

and

protection

capabilities

of

the

80286

to

processor extensions. The

PEREQ

input requests the

80286

to

perform

a

data operand transfer

for

a processor extension.

The

'PE7\'CK

output

signals the processor extension

when the requested operand

is

being transferred.

PEREQ

is

active HIGH and floats

to

3-state

OFF

during bus hold acknowledge.

PEACK

may

be

asynchronous

to

the

system

clock. PEACK is active

LOW.

Processor Extension Busy and Error indicate the operating condition

of

a processor extension

to

the

80286.

An

active

BUSY

input stops

80286

program execution

on

WAIT

and

Some

ESC

instructions until

BUSY becomes inactive

(HIGH),

The

80286

may

be

interrupted while waiting

for

BUSY

to

become

inactive.

An

active

E"R"RTIR

input causes the

80285

to

perform a processor

extension

interrupt

when

execution

WAIT or

SOme

ESC

instructions. These inputs are active

LOW

and may

be

asYnchronous

to

the system clock.

Substrate Filter Capacitor: a

0.041

,uF ± 20%

12V

capacitor must

be

connected

between

this pin

and

ground.

This

capacitor filters the output

of

the

internal substrate

bias

generator. A maximum

DC

leakage

current

of

1 uA

is

allowed through the capacitor.

For

correct operation of the

80286,

the

substrate

bias

generator must charge this capacitor

to

its operating

voltage.

The

capacitor chargeup time

is

5 m!lliseconds (maximum) after Vcc

and

CLK

reach their specified

AC

and

DC

parameters.

RESET

may

be

applied

to

prevent spurious

activity

by the

CPU

dUring this

time. After this time, the

80286

processOr clock

can

be

phase

synchronized to another clock by pulsing

RESET

LOW

synchronous

to

the system clock.

2-7

~------=p~72a~~=·'----------~------------~----~------~----------~------------~

2·2.a; Clock

generator'(Fig.2·3,.,~-'n"

~'"

. ,,,'

:-Fi~~2,~~",s~9~s.

t:~e~~ir~(J;~9t.t.h!1:_-~PC-7?,Op

RI99,~-

g;~~~~~t?r;Jw~,i~[

,i~

- - .

'c~nt~n~d·,i~"t~~;~.q479t,t",_,,_,_

,._~.

,;,

... , -;-,:

.

-:i-,

-:

',,'\

Clock- 'ihpur-to·-the'

SC47Sf'

internal 82284 logic, 'is selected

to

.

.19.2MHz._J

6MHz~

or12MHz _

by

:tfie:'-s'jgnal

recei~ec'-.frodi'Jhe_CPU

i

016bl{,

select

'switch,'(S1)':

';A

:24~H_z:

clock"

is' ihterrially"diviaecFffito

:one,half.

,The)

'ciock,Jnput',isiinverted]i:1Side

the)82284-

to!

sl:.IjJprred'

1

)-_".'

as CPU clock, PROCLK, '

".

','

PROCLK

iodivided

;nto.'1/2,.1I4,01101716'

.by

theintafnal

frequency.

divid~r:to

bes~pplied

a~SYscU<'

PM;"CL~,

~nd.

SDCLK

. ,

,Sync,hr()nization

i,S,_atta'I,n,ed

with PROCLK:by the,signa!'

8_1'

~rom'

the_'

: CPU;' at' the firs't-'cycle- immedii3teiy

'after-_reset.

:

i=i~f

2-4

~h0WS

it~'

'timing~__

'J:"

,.

',.:i'·

, "

,(-,'

, 82284

LOGIC,

,

f---'--'+----'--'--l.

AI.

J

_,

.'

:,

I ,.1;

+2

_

A2

y

f----l

EFI

>-'0-1--

PROCu(

ose;:

§T

(from CPU)

DIVIDER

'-*2'

L'f---'r-1':=-.:....._t_.

SYSClK

SD,CLK

,DMA9,LK

Figure 2-3. Cleek generator circuit

PROCLK

,.

SYSCLK

SDCLK

c~~~

'FiQure'.2-4. Timing

~hai1

of

cibck circuit

,

J!

-,

",

:

-J.

:_"

-'

,,"

' , ,

~-2"4\;

Reset Circuit (Figures

~"5,

2"6'and~~7)

; Figure

2.,.5

'is'

,a-

block diagram

of:the~,reset

circuit,

'a:ncf

Figure, 2-6

show~,-,~

timing -chart

for_

this,

,circuit. There

a~e

two methods

in

resetting the computer:

-.

,--Sy~tem.-R'1~et",

.

);

:;"

,,:,

.,'

,

'.

I

This

r~set,i,s

p,erlormedbY,'fhe

,RES!:!

an-d

RES~Tsignals.

The

RE8E{kig~f,d

'is''6btaii1:~cfby

synchronizlng'this purse

sigmiJ

with

the system clock at the 82284 LOGIC. ' .

Oiimeotherhahd,-siriCe

the

'SC4751·erilitS·the CPU

HESEl'

"signal: atthe;-receptibrr-of the

RESET"signa~

';the--entire-system

- iocl!-jding

tJ;Je

_;C,PU

iSJ

reset., 1 '

,-

I

••

CP~

RE?s~t.

'J,),'

~.

J

,"

','

,

••

. This reset state is controlled

by

the CPU RESET siQnal. This

reset signal is emitted

when'a

CPU shutdown occurs,

or

when-­the RC signal from the keyboard interface controller (8042) is
output.

The

shutdown state occurs when the CPU detects

an

internal error that prevents the execution of an instruction. If this
happens, the CPU denotes this state to the reset circuit making

the

SO

and

SI

signals LOW, MilO signal HIGH, and

AI

signal

LOW.

The RC signal is generated by the keyboard interface

controller on

the

CPU's order. This RC signal is used

in

the case

when the CPU changes

its operation mode from the protect

mode to the real mode.

-----

- Whefr-tne-CPV-is'

Fe~et,-iJ:first

tiegHJs

f'ft"

.execute1fjsfruC1iOffS

in

- ---

-~~t~~~~e,al

,modEl.:,~efore,

the-

q~u-

execuie~'lth'epbwer-O.O,

di,agnostic

."

progr~m:,

,it

re~dE/the

shutdown

st~tus

bYte

located

at

tile

addr~ss

. dFH

irithe

Ihlernal RAM of the RTC, Then tne CPU checks the

,:

reason~JQr:tbe':shlLtdbwn.

__

alld

__

Q~gilJs

_ procss_sing

__

13_cGQJ(Jjng:

to

-'"I

ttlei,irifOi'hiatioJi'written

in

the shutdown staius·

bYie.,

Tti&

CPU

i

~

RESET signgl;is':butput for the period

of

at

least 16 bus

cycli3s.

Fig.ure:;2:-,B.-s~ow~lthe

timing chart for the

CRU

reset.

------:-~-

52284

LOGIC

I

'",

"

..

,

, .

~ER

---f.-"---"--'~~--j

,

,(FROM

P~!

)-,-f-'-'

RESCf'U

SC4751

Fjg'ure 2-5.- Reset circuit

" .

_

~+~5~V~

__ --______

~~

+5V

':\:>_'---

GOOD

~

______

..J-----!!~_

..

POWER

POR

__________

-I----~!r!------,,_

(SYSTE

:~~i~~'

--"-'--~---~'-----!I~.--

RES

CPU

!~'h

Figure 2-6. Timing chart of reset circuit

CPU

RESET

S~U,T_

oo.WN

(SO·

$I.

AI_

0,

M/iO·

II

OR

RC(RC

-01

,,~Qyr~:?-7.

Timing chart of CPU reset

'1-,

~·~"5.

NMI.and

INTR

ContrOl Circuit (Figure

~·8)

,The.-8,Q286"has nyo.'interrupt terminals; one is the Non-Maskable

Interrupt (NMI) and the other is tffeTnterri:.ipt. HOwever, in

tills

system,

the NMI signal is masked by ·the NMICS, ENAIOCK (Enable

110

Check) signals, (Refer to Figure 2-8.)

The

NMI terminal is used to detect a malfunction of

110

devices
connected to the optional slots.
CLRNMI signal is output from the 4-bit latch addressed at

061

H,

and the CS70H

Signal

addressed

at

070H is output from the

110

address decoding circuit

in

the SC4752.

The INTR signal is controlled

by

two PICs (PIC MASTER and PIC

SLAVE)

connected

in

cascade. The INT terminal

of

the PIC SLAVE

2-8

-

PC-7200

is

connected to the IR2 terminal of the PIC MASTER; therefore, the 2-2-6. Bus Construction (Figure 2-1)

PIC

MASTER acts as a master PIC

and

the

PIC

SLAVE acts

as

a There are two buses

on

the

main

PWB;

one

is

the address bus and

---slave1'te:-when-the-BP~-+.t-inteff~;>te<l

.... t-t"e-nlj:r.R-ter"'i"al,..ill-t

----tile

otio8f

is

the data bus. These.buses

canJulllleJ

bl1.

dil'i.del!h..-

__

_

returns the interrupt acknowledge status

to

the BCU

in

the SC4751 their functions. They are the address bus, data bus, and the data

by setting

MiiO,

SO

and

81

terminals

to

LOW.

When the

BCU

conversion circuit that controls these two buses.

receives this status,

it

recognizes that the CPU

CQuid

enter the

interrupt acknowledge cycle, and the BCU asserts the

INTA signal

to the master

PIC. The PIC sends the preassigned vector address

corresponding

to

the

110

device to the

CPU

via the data bus. Table

2-4

lists the assignments of the 100 to IR15 signals.

Table 2-4.

Interrupt priority

Level

Function

PIC

#1
IRQO
IRQ

I
IRQ2

IRQ3
IRQ4
IRQ5
IRQ6
IRQ)

f

,-

.-

,-

;-

,-

,-

PCHSE
PCHEN
SCHSE
SCHEN

FOSEL

,

-

tRa9

"

"

'"''

IRal

,

•

,

PIC

#2

Timer

output 0

Keyboard

interface (output buffer full)

Interrupt from

PIC

#2

IRQB

Realtime

clock

interrupt

(RTC)

IRQ9

Software

redirected

to

IN T OAH

(lRQ2

)

IRQ

I 0

Reserved

(option slot)

IRQII

Reserved

(option slot)

IRQI2

Reserved

(option slot)

IRQI3

NPX

IRQI4

HDC

(option slot)

IRQI5

Reserved

Serial

port 2 (UART)

Serial

port 1 (UART)

Parallel

port 2 (printer

I/F)

FDC

Parallel

port 1 (printer

I/F)

""'"

"

..

,

'"

0

""""

"

"

'M'

C~'M'~

~

tnt

MASTER

I-

'"'

,-I--U--

'"

'"

,m

''''"

INTERUPT

~

'"

SELECT

'"

LOGtC

~

'"

'"'

r--

tR7

'""

~

SLAve

'"

""

c:::;

'"

-

'"

,

,

,

'"'

~

'"

cm

co,

'"'

'"'

'"'

'"

'"

-

""

'"'

~

,.

'"

'"'"

-

"""

5C4752 504751

Figure 2-8.

NMI

and

INTR control circuit

C'"

2-9

2-2-6-1. Address Bus (Figure 2-2)

This bus

is

classified into 3 categories of functions:

1.

LAO

through

LA23

These bus signals are directly output from the

A1

through A23

terminals of the

CPU

to

the memory address decoding circuit.

The

AD

signal

is

used by the

SC4751

to simulatively assert the

lowest bit

(AAO)

when the CPU performs a word access to

an

8-bit device.

2.

SAO

through

SA

19

The

SA1

through SA19 are obtained by latching the

A1

through

A 19 signals with the ALE

Signal sent from the SC4751 at the

latches. When the

O-RAM chips are being refreshed, the SC4751

outputs the refresh address from its internal counter. The

SAO

signal

is

obtained by buffering the

MO

signal. The

SAO

through
SA 19 Signals are used to address the V-RAMs on the main PCB
and

memory

and

an

1/0

device located on an option board. If

there

is

an

external microprocessor on the option board, the

processor

can

handle resources on the main PWB, provided that

the processor outputs addresses

to

this bus.

3.

ELA

17

through

ELA23

These signals are obtained by driving the

LA

17 through LA23

signals at the buffer,

and

they enable the 16M bytes memory

access by the CPU

in

the protect mode. These signals are sent

not to the devices

on

the main PWB but to the option slots. If
an external microprocessor on the option board utilizes the
resources

on

the main PWB, the processor outputs address

signals

to

the

LA

17 through LA23 and

SAO

through SA 16 address

buses.

2-2-6-2. Data Bus (Figure

2-9)

Like the address bus, the data bus can be classified into the following
five categories: (Refer

to

Figure 2-9.)

1.

LOD

through

L07,

XOS

through

X015

These data bus signals are sent directly

to

the CPU and NPX.

And

XOB

through XD15 signals are provided for odd address of

the D-RAMs and

ROM.

2.

SOD

through

S07,

SOS

through

SOlS

The

SDO

through

8015

signals are usually obtained by driving

the

DO

through

07

signals at the bi-directional buffer.

When the CPU reads data from

an

8-bit device

or

memory, data

bus signals

SOO

through

S07

are latched at SC4751. This is for

maintaining the first data from even address

until the CPU read

the next odd address.

In

this case, the swap-buffer transfers an

odd

address data output

to

the

SOO

through

S07

bus lines to

the

SOB

through S015 bus lines. The operations mentioned

above are controlled by the data conversion circuit described

in

Section 2-2-6-3.

3.

XOD

through

X07

These bus signals are used by

1/0

devices on the main PCB

except for the

FOC.

;

,:;';-;,:-:

8,);1,\

,IYOJriJ.

';": 1 f

ni.

'rJ

'oJ13

,~:~ifk)

;\:1:;;·-:

:j

';r!j nxP?

.;';:Jr!'(;lRAM

~"

'"h'''''

- -

"-'i".~~)~,

_'~"~'~"'_'_'~"X70~'_:""~"'-',i!~'~"_"\_'_-~"~"'v'li'

-0;'

'-:ROM

J"i:ii.;'_)1rij

Qr\8 :-l;;T

..

ii;'~:;

04;'\

-")fi!

:,:;r·!j);-,~;:r:

\('-~

l),o.l'i!;,t;-ic,i

~!

1,;jr(tl,ighByte)

r\Y1

n::;ill

_J;1l

:1')

-3.

'/],- ,;! ,\,I

;-)rii

"~d:-rJ;,)b:-'i

'J:

j~)GU

,Ii:-,

,-"i;~:

l~J'~

'-'

i ,

II

'}b

:{l

nniU;"

fir

nJ

:n-,"--;:c':;~

~;'::::'::::';

':>1

.'F'

jnt:;

'nol:"h'0~'~

.

...,.""--

";

':,

~:~~:~;

;~~~,:;~,:;.~

~o~~~;~;;~:,I,'.;:,;;,·;:;,~~£:'.

::);~~iM

;:,., ,

__

' .';")

;-~_;'iIJ~

)-!~

R~M

.:'

','i)~

,

r,

,!j':.ji' ,viJ iiJd

FJ';-.r'.

ni.s,-,i

::Jf:;-

'-IQ

_:::'!:Jl'd;_'

!,l,

,',-):;;:I;:J

'.

i

,CO)

lFigt.irE!'2-g-~JD.ata

-bus

Dp-er~tioh,;

L'

' -r)

'!lpV>'Byte)

~}-'-i~!;:";

,~;I',V

,-.,,,

'j:>}:-'-1

::-i:

-','J;

iljc,fTl

,:"it

'1--:'

c!-)-j:')

r")

~Z-2l6

..

3i/'D~f~

'e:b:nV~'rsidH~circuit'~;:U

'j

II))

-'[-;;-'1,""

Fig,2-10 shows the concept of the data conversion circuit'c6ris-iSling
of the SC4751, and Fig,2

i

1)1,{,shQ~~_

~:t~ll]ipg~~,ph'?rt.rela!_~ct

tQ

_.t~e

circuit 0 eration for an

8-llif

manic

·.J'--~rJliO"device:--'

_'J,

.~.

'I..'

-'"

--,

'.lT~~J~~t~hbriljJt~f6~~gi~b~urtiM~_rt~:t6·%p~r~te

~h~~lthe

C?ti

d6~e's~-es

an

odd number word

~,a,t~,of,:~.~~,g~~ir'~~~jce_:~"l

;:

i

-~:,),~:;~"':~'1

1 )

:';,'

"Yt1~9"

th~

·l?P~?~1

.

r~fqg,~f~e:~:~h·.~a_~c"e~$s

J]

~r:i;8~pjt:-d,~viq~,

the

~~I~;;i,~,

~ep¥~~edS~t9"_

t,~f)~r~~Ef~

,dJ~~~;'~v.11.n~n~~-njg:~'r:p~~,~np

odd

rllimb'ei(byte~

B~da(i~je

-tiie-

CPU'

i~:

in'

i'-dr

re,ady'

stat¢:'u:ritil

the

end

of the second cycle, it

operq!e§,a~,if,m~~,e_two,~~c)~(W~'

j~-O~,e:I!¢YCI~.

~'-.J~,),

"_"JI

__ ' ",,-,

'~".I

.. , ..

,,,)11..

",L~,

•

;

)'1IJ~{,~nci"J~Ic(r~;ad"trdrrtJa';

!;a-bli

id~vit:Erih~b~;~w

3d3ojt

'i1

i

(1) At

th~

'e~~ri

'riuRurer

ii

bY,i1

:r~kiF

.:.!6ie:;(first

h

~I~r,~'~lafa-:

r~c

..

i~ived

'~','

'f'r_-r']

'-~~"'~"""I"'-'-)---

,-,-,,9Y.,,\

,---,,,y'YJ'--

'~"-"'I'

.

d~_"

JrtJiifbus.

XOtr..:.::t-aJ~'

ia~cn~djii

tHs'-SC475L,.''-',

11,) , ,-"

.i:(2r:11(t)'ri~

,~~~~~{,mb~t~~~

~~~~:

f~~j~

~(~~q8.~:6Y,t,~~~'~~at~i~beived

"

',-,

"from' bus

"XOO":';'Tare

:sent'

onto

b(]s"JSOe~15"an'd~",atJthe

same

,1:;

"tTIfle-/'t"n~

~Q&i1i~§iErdiii~JMCfMd%

tf,lSC4151-are,'se'nt throu h

::,t

,·~tGs:xb6\:;.;7.

:'h":)-:.-,:?,,:-,,

-~r,)

:);}

;".!i~~~'

:"::'

"';:~1;~':

':,

';j;~

9

:.~3)

An_~'~

11re)-t,~WI.~-gOjK~~fterd,;~~t~

JW~~~~,h'

(0,

b~i

_~'~·~~~D~;-j~,

the

."

CPU

erminate::d:lccessin'g:"'"

.-'

"',

'''-'--, ..

, ,,'

.,

.

,:~

-i ~ - 1,

-J

i)'

, ;

2.0dd

word write

to

an a-bit device

throl,lg~

l;nt~)'Xp,O,",,!?:

-j(HAUhe

,,?,,,en

,nu!T:!I;l,!9Lbyt~

write"~gy;cle:,-(fiE§t:

~YGfe);_

!=I~ta,;,on

bus

LOO-7

are

sent through XOO-7

to

writ~;j'

,,":)

1

~-)

J'_i''-}-r.',-,

(2) At the odd number byte write cycle (second cycle), data

on

bus

X08-15

are

sent through XOO-7 to write.

3.Even word read from an a-bit device through

bus

SOO-7

(1)

At the even number byte read cycle (first cycle), data received
from bus

SOO-7

are sent onto LDO-7 and internally latched.

(2)

At

the odd number byte read cycle (second cycle), data received

from bus

SOO-7

are sent onto bus

X08-15

via the swap gate

and,

at the same time, the even byte data latched in the

SC4751

are sent through bus LOO-

7.

(3) After receiving the word data, the CPU terminates accessing.

4.0dd

word write

to

an a-bit device through bus

SOO-7

(1)

At

the even number byte write cycle (first cycle), data

on

bus

LDO-7

are sent through SOO-7 to write.

(2) At the

odd

number byte write cycle (second cycle), data

on

bus

X08-1S

are sent to SOO-7 via the high gate and swap gate to

write.

1

;\),11

::

j,

\()

T

iii

1
1

Iii
II:

II~

--

1s118yte

----

2nd 18Vle

CONTRLOFF v-'-AO

Figure

2-10. Word read

~peration

for'

e~erlial

8 bit

devi~es

PRO

ClK

TI I TS I TC I TC

I

T<f

I TC J

TC I TC

I TC 1 TC

-(

TC J TC ! TC

Ii

TI

I

SYSClK

I _

,_

~

iIDiWR:----.

EVEN ADDRESS! r--:-"J

~

___

ODD

ADDRESS

I

r--

ARDY

-----.I

DATA

CON\(--'

ARDlf

EN:~

END

CYCLE'

CONTOFfi

AO

,~

DATA CONY:ERSION:

"I

I

-~

--

__ : __

,

r--

Lf..J;

L...--l

--

'--,

~i

2>10

-~-.

-Byte-Bos-flyeIe

--

CPU

Even

Memory

Read

Odd

Memory

Read

Even

Memory

Write

Odd

Memory Write

Even

I/O

Read

Odd

I/O

Read

Even

I/O

Write

Odd

I/O

Write

Even

Memory

Read

Odd

Memory

Read

Even

Memory

Write

Odd

Memory

Write

DMA

Even

Memory

Read

(lOW)

Odd

Memory

Read

(lOW)

Even

Memory

Write (JOR)

Odd

Memory

Write (lOR)

Even

Memory

Read

(lOW)

Odd

Memory

Read

(lOW)

Even Memory Write (JOR)

Odd

Memory

Write (lOR)

MASTER

Even

Memory

Read

Odd

Memory

Read

Even Memory Write

Odd

Memory

Write

Even

I/O

Read

Odd

VO

Read

Even

I/O

Write

Even

I/O

Write

Table

2~5.

Bus buffer control

-i."W&I,-E-

-HIGH&I,-E-

-6WA~".f

H H

H

H H H

L

H H

H

L

H

H

H H

H H H

L H H

H

L

H

L H H

H

L L

L

H H

H

L L

H H H

H

H H
H H H
H H H

L

H

H

H L

L

L

H

H

H L L

L

H

H

H

L

H

L H H

H

L

H

L H

H

H

L H
L

H

H

H

L

H

2

-11

--IlIR.1-1i--

L
L

H
H

L
L

H
H

L
L

H

H

L
L

H
H

L
L

H
H

H

H

L
L

H
H

L
L

Remar-k-s----

Memory

on

the

main

PWB

-

PC-7200

B - bit

j/O

on

the

main

PWB

B bit

memory

on the option

slot

I/O

to/from

memory

on

the

main

PWB

I/O

to/from

8-bit

memory

on

the

option slot

Memory

on the main

PWB

B - bit

I/O

on

the main

PWB

-',

-PC~"7200

'"

2-2-7. Memory

As a standard

configuratiqn-!-

16,-chips

of 256KMbitx.1--.DRAMs

and.-4

chips

of

64K-x.4--CMMs-are-'jhlfJle

rTl

ented

td

constitute the

memory

size of 640KB. AS'there 'js'a-

space'o~\listalling'extra

8 chips of

256K-bitx4 DRAMs

as

an

option,

it

is

possible

to

expand

to

1,664KB.

Two

chips

of

32KB ROMs are

on

the board.

2-2-7-1. Memory address decoder

is

employed to decode memory

ad~ress.

Address is

address A16

10

A23,

AD,

SHE, jumper S5, and

i'nternaIlY

__

generated

in.

the SC4751. Refer

t6.

Tabf~

2M6

for the SC475FouipufsignalS. '1,-,1

.j

ROMCS
ROMCS

is an output for address

OFOOOOH

Iq

OFRFFFH

and

FFOOOOH

10

FFfFFFH:rel!,jf~le~s,

bphel

'swilen

55

POsilion,

CASL

1.

Jumper

55

al

"1-2"

CASL

is

an

QulpJJ1JI'Lhen_data.

oj

an

_even

address sjde

J~

aca8'ssed

for address

OOODODH

tb09FFFFH

andlOOOOOH to 1FFFFFH;

2.

Jumper

~5

al

"2-3"

CASL

is an 'output when data of

an

even address side is accessed

for address

OOOOOOH

10

07FFFFH and 100000H to 1 FFFFFH.

",J

CASH"

1~

J_umper

85

at-'!1--2!':,-

_

:'11

'

.",~.-.-;-

------:-

~_'~-,

CASM'ls:an-output

when:

data-'of

an"

odd adqress-side

is

accessed

for address

OOOOOOH

10

09FFFFH

~~dlbdiJoOH'IO

1FFFFFH.

"

'J

2.

Jumper S5 at "2-3"

.;,

,

CASH

,is

an

output when

data

of

an·

odd

'address

side

is accessed

fqr aaqress

OOOOOOHto

07FfF'fHano,iOO,OOOH to

iFFFFFH.

RASO

",

Regardi,ess

of the jumper

85

j~J~itio'n,

'RASQ-

is

an

output for address

-0000001'1-10

7FFFFFM.__

""'.""

','

c·,,,

..

RAS1':

'''''';

"" , ..

""

..

1l

Jumper

85

at "1-2"

),

:'.;/

-'u

'-J'"i

~AS1

is an Qulput for address

o.aQOQQH,

IQ

09FFFFH.

I

;'/,

) I '

-,

~

2,.

Jumper S5 at "2-3" ,

..

,

RAS1

is

not

an

out~_yt.

,

"'i

Regardiess

Clf

jum'periSS'positioh,;

RAS3"I!:;

an output for address

100000H to 17FFFFH.'

RAS3
Regardless of jumper

S5~

RAS2 is an

outputfor

~ddres5

180000H

to 1 FFFFFH.

,'

...

NOTE: When REFRESH is at a low, RAS1, RAS2, RAS3, and

RAS4 are issued.

Table 2M6.

SC4751 address assignment

Input

Output

BHE

AO

A2l

A22

A2l

1120

AI9

A18

All

A16

S5

REFRESH

CASl

CASH

RASO

RASl

RAS2

RASl

ROMCS

x

x x x x x

x

x x x x

0

0

0

1

1 1 1

0

REFRESH

0

0 0 0 0 0 0

x

x

x x

1 1 1 1 0

0

0

0

OOOOOOH

....

07fFFFH

word

0

0

0 0

0 0

1

0 0

x

0

1

1

1

0

1 0 0 0

080000H-09FFFFH

word

x

x

0 0

0

0 1

0

0

x

1 1 0 0 0 0

0

0

0

080000H-09FFFFH

any

x

x

0 0 0 0

1

I 1

1

x

I

0

0

0

0 0 0

1

OFOOOOH-OFFFFFH

any

0 0 0 0

0

1

0

x x x x

1 1 1

0

0

0

1

0

IOOOOOH-17FFFFH

word

0

0 0 0 0

1 1

x

x

x

x

1

1

1

0 0

1 0 0

180000H-1

FFFFFH

word

x

x

1

1

1

1 1

1 1 1

x

1

0

0 0 0

0

0

1

FFOOOOH-FFFFFFH

any

0

1 0 0

0

0 0

x

x

x

x

1 0 1 1

0 0

0

0

OOOOOOH-07FFFFH

odd

0

1

0 0

0 0

1

0 0

x

0

1 0 1

0

1

0

0 0

080000H-09FFFFH

odd

0 I 0 0 0 1 0

x

x

x

x

1 0 1 0 0

0

1

0

JOOOOOH-17FFFFH

odd

0

1 0

0

0 1

1

x x

x

x

I

0

1

0

0

1 0

0

180000H-IFFFFFH

odd

1 0 0 0

'0

0 0

x

x

x x

I 1 0 1 0

0

0

0

OOOOOOH-07FFFFH

even

1

0 0

0

0 0 1 0 0

x

0

1

1

0

0

1 0 0 0

OSCOOOH-09FFFFH

even

1 0 0 0

0

1 0

x x x x

1 1 0 0 0

0

1

0

lOOOOOH

....

17FFFFH

even

1

0 0 0 0 1 1

x x

x

x

I

1

0

0

0 1 0 0

180000H

....

1FfFFFH

even

NOTE~

1: The above table applies to memory read and write.

NOTE-2: The jumper S5 is

"1"

for

"1-2" and 0 for "2-3".

2-2-7-2. RAM addressing (Figures 2-12 and

2-13)

Two chips of 256K-bit (32xB-bit) ROMs are mounted on the main

-

-boardas a ·8TOBtmM.

-----

Fig.2-12 below shows the block diagram and Fig.2-13 the timing

chart.

S~'.'5::===========~~~'·'5=:j.

oo,W·"oo".,

__

--'\

.,~

7 XDo·,5

H'OA

__

~

SO,S!

MilO

SC"5'

1l0lMCS

Figure 2-12

Ao,~l

:=:::X=============::JxC======

ROMes

____

J-------------,

__

_

•

--

,:=

:=

-

V

!iii

~

~

I 1Jl1'2
I

OLYl

~

L-

AA.

~,

..

"

SC41~t

"~,

~

""

CASH

L;--,

-

PC-7200

"'"

"~

,-----<

""

OO,.,ODIHI7FFFEH

~---aT~

""

""

OODOO1H.cl7FFFH

'"

STANCI.RDIODD)

'"

"

tJBOOOO1H'IIFFFEH

..

"

STANDARD

(EVEN)

:::fJ,----

I=:rJ,-

"~

~

IlIiOQQOH.oIIFFfEH

f--n,-

'"

1-<'"

STAND~AD(ODIll

~

"~

"~

HIOOOOH·I7fFFEll

""

'"

OPTION

(EVEN)

"~

'"

HIOOIl1H·17FFHH

"'

'"

OI'TKlNIDODI

'"

ox

ISODOH·'FFFFEH

'"

'"

"O!'TION(EVENI

"~

"'"

,~

"

I8ODOH·'FFFFEH

~--------L_

________

-'----

'00"'

_________

---<=====::>--

___

_

Figure 2-13. Timing chart of ROM addressing

2-2-7-3. RAM addressing

As

a standard configuration,

20

chips

of

DRAMs

(16

chips of

256K-bitX1 DRAMs and 4 chips

of

64K-bitx4

DRAMs) are mounted

on the main board, and,

it is possible as an option to implement 8

chips of 1

M·bit DRAMs

(256K-bitx4

DRAMs).

Fig.2-14 below shows the block diagram and Fig.2-15 the timing
chart.

The RAM areas are divided into eight groups.

CD

OOQOOOH

through 07FFFEH having even addresses

® 000001 H through 07FFFFH having odd addresses

®

OeOODOH

through 09FFFEH having even addresses

@ 080001 H through 09FFFFH having odd addresses

®

10DaOOH

through 17FFFEH having even addresses

® 100001H through 17FFFFH having odd addressses

o 180000H through 1 FFFFEH having even addresses

® 180001 H through 1 FFFFFH having odd addresses

CD

to @ are the standard configuration RAM area and ® to ® are

option

RAM area. Each group is selected by CASL, CASH, RASa,

RAS1, RAS2, and RAS3 sent from the SC4751.

.•

2-13

..

,---<"

'OPT~N(OOO)

---\

1

-I

•••

,~

I>

Figure 2-14. RAM addressing

~.

~~==============~x~=======

________

,--,L

____________________

__

-=~~~

I

,oonS

R,OJ,IfL',S I

r-

7OnS--j

r-~--I

=====X

ROW

X

CATAOIJT

_____________

--(=:::;""~~"""~;;;:"=:::>_---

DATAIN

WI1ITEOATA

>---

Figure 2-15. Timing chart

of

RAM addressing

2-2-7-4. D-RAM Refreshment (Figures 2-16 and

2-17)

Refreshment for D-RAM chips is performed

by

the

refresh address

counter and the

hold control logic inside

the

GA1. D-RAM

refreshment starts on a

clock signal sent every

15

microseconds

from

the

OUT1 terminal

of

the PIT. After the OUT1 terminal becomes

HIGH, the

GA1

sends the CPUHRQ signal to

the

CPU

at

the second

falling edge

of

the DMACLK signal.
When the CPU receives the CPUHRQ (D-RAM refresh request)
signal, it returns the CPUHLDA signal to

the

GA 1 at

the next CPU

cycle,

and then repeats the hold cycle.

At

this time, the REFRESH

signal

become LOW, and

the

GA 1 makes

the

simulative memory

read

signal MEMR LOW for refreshment. Then

the

GA1 outputs a

refresh address to the

SAO

through

SA7

address bus, after it counts

up

the

refresh address counter inside it. Therefore,

it

requires 256

x

0.015 = 3.84 milliseconds to count up

256

row addresses

.

(256K-..bit-Er-RAMs);

1.92

milliseconds

to

cQunt

up J 28-row

addresses

(~4K~bit

p-RAM,rFlgure2"16

showsi

D-RAMfef;estiin~n1,

and

Figure,2-17

shaws_]the;

D-RAM--refresh~ent<ttrping,

chart)

.1

'CF'UHlCA

,1'°'-0

'fiiC-v~

-

sYsco."··

·co

,-,·r-"Lrll

,,-

••

,r-U"""L--,",-r,--,,

''-_'"L

•

DMACLK

~,

~<

~,

~,

~,

CPUHRQ

-I,

Figure

2-17.

Timing

chart

of

D-RAM.refreshment

:,i

,.:",,)\'.1.,

,'j,,-"':"

,',

2-2-8_

1/0 Address Decoding Circuit (Figure 2-18)

This

circUIt

is"j'nclJded'lr,

'the

8C4752

as

shown

in

Rgure

2-18.

The

role-,of

this

circuit-·is

tp

outp~t

the

chi~

_

select

si~nal$

to

·ei;l,ch

related

Circuit

a:ccofdi~g

to

Uie

a:adress

signals

XAO

fhrougn

XA9.'However,

an~enable/disable'

status

and

channel-

select

status

of

t_he~following

interlace

-arcult

is

selected

by

DIP

switches

84-1

through

84-5

as

shown_table.2~7.

.

Floppy

di~k--drive

interlace-

circuit

Printer

inteMace

circuit'

Serial

interlace

The AEN.signal,

ob1ained

'by

ANDing

1he

HLDA

and

MASTER

-

sjgi1~ls.'ii').Qic:at_i;i~';tn~tJlje

C~U-i~_'~xeputillg

hqld

cycles.

This

signal

is

emitted

on

these

conditions:

DMA

operation,

refreshment

for

D-RAMs;

~md'

accessln~r-of

the

resources

on

the

main

PWB

by

an

extenw,J

miQrQP_JQ~e$SPI,

When_the

AE;N

signal

becomes

HIGH,

the

I/O

decoding--circuit-ts~deactivated.

Tablei

2-8

shows

the

relationship

betwe~~t~~_lVP;~Rgr~~~:jand

the;H:f:1,jJ?;s~lr~

sjQ~~h

,J,

.•

,'.

,,;~,

1_

--j

~. ~'

__

j.

L..-

'',.'.'

;,-1

,""

",',

'"

"I,;"

'.;]

,:.,"'):'

:

,~

-;

~1,:'

",.

:;)~

J'

)

i-I

,1

;,

IIJ1-

)~'

J, i ;

~j'j;'

II

'j

lJ,·

1

,,/:t).

J '

,,'

~)

..

I"

j·~l.)

;,;.j

'.

,"

:'j!

j

;,-)

I

,r:~>

-.

"

II

iii·

'-'.'"

i-·l;

'I!)

II

Eo")·,

di

,:; J "

','

:]

4

r

:r~~:'~'"'"~'"'~

:o_F

i"

,)';,

;>-.1,

',>j

,i " :.'

MN1292

MONO

ADAPTER

MN1294

COLOR

ADAPTER

i!

Internal

FDC

ON

,':.L.

'.,.3F"a.~._

.•

3,F7,.

,.',

Add[ess.:..~~I_~~t,.

" '.

'--,

,-

;"t,r;;)I;'

'I

W2F,B,72Ff

.,

Internal

Parallel

Port'

L:m

-37

A _

......

H. : ..

2,.7."B -..

".2

... 7 A.

.

Addre,s.s,

Select,·· :

:f~'Y:

: 1:,,)

Signal

Name

Address

R/W

Device

CSB042

60,64

R/W

Keyboard

Interface

AS

70

W

RTC

Address

Strobe

CMSSEL

70

W C

MOS

RAM

SELECT

OS

71

R

RTC/C

MOS

RAM

Read

R/W

71

W

RTC/MRS

RAM

W,i1e

CSNPX

FB-FF

R/M

B02B7

NPX

CSCRTC

JBO-JBF

R/W

Monochrome

Adaptor

(MONO~LOW)

JOO-30F

R/W

Color

Graphic

Adaptor

(CllA~LOW)

10SI

R/W

This

signal

lOW

indicates

CPU

or

MASTER

Device

accesses

1he

device

in

the

SC4752.

2-2-9. Ready Control Circuit (Figure

2-19,

2-20 and

2-21)

ThIs-clrcutHs irTcfuded-;n---se47''51 ,

-and-"'Controls-the-t1mif'lg~-tne

READY

signal

to

be

sent

to

the

CPU.

The

READY signal

is

used

to have the CPU continue the bus cycles until an actually accessing

lID

device

or

memory becomes ready to be written/read data.

When

the

READY

signal

is

HIGH, the

CPU

senses that the

110

device or memory is not ready

to

be accessed, and it repeats the

TC

cycles. When

the

READY signal becomes LOW, the CPU

terminates its bus cycle. The

'REAi5'Y

signal

is

synthesized from the
SRDY, SRDYEN, ARDY and ARDYEN signals at the internal circuit
of the CG. The

SRDY

(Synchronous READY) signal is sampled by

the

CG

at a falling edge of the phase 1 clock

of

the

TC

cycle,

provided

that

the

SRDYEN

signal

is

LOW.

The

ARDY

(Asynchronous

READY) signal is sampled at the beginning

of

each TC cycle,

provided that the ARDYEN signal is

LOW.

__

In this computer, the SRDY signal is connected to the

OWS

(Zero

Wait Cycle) signal sent from the

1/0 device on the option slot, if the

110

device does not require a wait cycle. Therefore, if the

OWS

signa I

is

LOW,

the

CPU does not insert wait cycles.

The

AROY signal is controlled directly by the lOCH ROY signal sent

from the memory

or

I/O device on the option slot.

In

conjunction

with the ENDCYCLE signal, the

AROY signal controls the TC cycle

(wait cycle) when the CPU performs the following operation:

~

6MHz/SMHz

9.6MHz

operation

8bit

I/O

4wait

if

5wait

OM"

16bi!

I/O

1wait lwait

Shit

Memory

4wait

~

5wait

16bit

Memory

(O-IFFFFF)

lwait

lwait

16bit

Memory

(200000-FFFFFF)

lwait 2wait

8105-

ROM

lwait

lwait

lSbit Memory

(80000 -9FFFF)

1wait 2wait

(IOOOOO-IFFFFF)

The ARDYEN signal is used

to

concatenate even and odd addresses

when the CPU performs a word access to an

8~bit

memory

or

I/O

device. (Refer

to

Section

2~2~6~3).

Therefore, when the data

conversion operation is performed, additional waits are inserted

to

the wait cycles listed above.

__

_

Figure

2~19

shows the ready control circuit. The IOCS16 signal shown

in the figure is sent from the option slot to the

SC4751, and becomes

LOW when the 1/0 device is a

16~bit

device. In other words, when

this signal is

LOW,

the ENDCYCLE signal becomes LOW after

one

wait cycle passes, resets the

flip~flop

A

in

the

GA

1,

and

makes the

ARDY

signal

LOW.

The FSYS16 is an ORed signal

of

the MEMCS16 signal sent from

the option slot and the chip select signal sent from the

ROM and

RAM decode

logic in SC4751. When the FSYS16 signal is HIGH,
it indicates that addressed memory is 16·bit. The RAS signal is
obtained

by

NORing the MEMR and MEMW signals. The RES/OWS

signal is available by NORing the

OWS

signal from the option slot

and

RESET signal from the CG.

The ready control circuit also inserts a wait cycle

to

the DMAC when

in

the

DMA

operation, using the DMAROY Signal at the flip·flop C

and D in the

SC4751 Figure 2·19 shows the timing chart

of

a word

access

to

the

16~bit

memory

or

I/O device, and Figure 2·21 shows

the timing chart of the DMARDY signal in DMA operation.

-

PC-7200

~

""",-=a.J-

:::::::~-

""""

-.

-

lOCH"'"

-

;o.c

-

~"'''~

,""1""0'

"

r-'

"

"'

,_o-

m

p--r"

PROCLK

SYSCLK
JOR/IOW

RDIWR

SC47s1·Q1
ENDCYCLE

-

-

l ,.,,",

"'

,

l;.

I

l!III;rr

I

-,::L>

~

-l-

~

,00,,"

'---

~

,""

""'n

>

t;n~~-"".~

""""

.""'"

Figure

2~19.

Ready control circuit

Ts

Tc

Tc

I

Ts

SC4751·ARDY

READY

Figure

2~20.

Timing chart

of

word access

SYSCLK

81

DMACLK

XIOR

(IOR/:"DM"'A"M"'E"'Mo'R)-----.....J

L

FFc·a

FFC·Q

________

~~L

__________

_

L-J

FFD·C[

DMARDY

Figure 2·21. Timing chart

of

DMARDY

signal

2·2-10. DMA (Figure 2-22 and 2-23)

Two

DMACs are utilized to provide fast, efficient transfer

of

data

from

the

I/O devices to memory,

or

vice versa, without intervention

by

the

CPU. (The CPU is held in the hold cycle while the

DMA

operation is performed.) The

DMACs

are linked in a master/slave

relationship, with the master

and

the

slave, by connecting the hold

request (HRQ) terminal

of

the slave

DMAC

with

the

service request

input

(DREQ4) terminal

of

the master DMAC, and the hold

acknowledge input (HLDA) terminal

of

the

slave with the

DMA

acknowledge (DACK4) terminal

of

the

master

DMAC.

(See Figure

2·22). The master DMAC controls

DMA

channels 4 through 7,

and

the slave DMAC controls OMA channels 0

through

3. Channel 4 is

used

to

connect the slave

DMAC

in cascade.

The

master

DMAC

is

used

to

perform a

word·by~word

data transfer,

and

the

slave

DMAC

is related

to

a byte·by-byte data transfer.

Table

2·9

lists the

DMA

channel assignments.

2

-'5

Table 2-9. -OMAC channel

as~iQI'),rn-eotS

l '-_ -:-.::...

____

'_.J

Channel

-

'--~

C,Qnneqtion

...

~.-

Master

r

qp_tion

slot

'2

FOe-or

option

slot

3

,opt

jon

siat

4

Cascade

for

slave

9ption slot

G 9ptjon

§i/ot

,>

:'-,-1,

n;',

F;i,~~,F?1~-~~;

19M~,

,0'p'er~t,i~_r

) i ,)1

'i

'"

..r;~UH~

~

i-'

DMA

operation is performed by the OMAG after making the CPU

~o'ld~j:lS~~_g;

't~e

:CPU,~R9

signa:I.'

th~

s~q:ue-~c~

for

the OMAC

operation is "described

b"elow.

(Refer

_to

Fig,ure '2'-23.)

1.

'A

DMAC

servicf3i request is

~upplied

by'I/O

d~vi~~s

by

Jising"the

corre,sponciing-ORO irlPut to

_HIGH.

2.

~

The

'[)MAC

d-etermines -the yalidity of

Jh!3:

r~q~~st,;al1d,

_output~

an active HIGH HR01 Signal which is latchett"

'at'

'HOLO

}\RBI-r:ATI()N

L()Glg

by

the'DJ'AACLKsignat..

'.

....

3.

T~e

La.tche'!.~ign~1

LHRQ

issenU,o.Jh_e.~g.4?§1

a~pjY<1ges

whether the

O-RAMU:!?f!~_~;

circuit in the 8C4751 is active

or

not. The refresh circuit makes the CPU hold with the CPUHRQ

-sfgnaC----

,"---

-,-

--.----

._..

,

j'-l".,

4.

WB~_IJ_~~e

__

¢-pjj

receives

th~

GP_l!tiB_Q..f?!g.nal,

it

ent~rs_,i,n,

the

hold state

aft~,r:..§L9..u!rt:!nt

g.!J~

cycle is completed. Then the'CPU
makes the impedance of the control lines and bus lines high,
and

retur:ns'the :CP.l!lHtOA1sfgnai,to:the

;S-C4751,;i

5.

The

SC4751

judgeswhether.the.CPUHLQ/!. signal.sent from

the

CPU is a hold'"

~cRn6Wi€dg,~-:msigrial:,.Jfb('thef"

il1'te'm~1

j

o'~R-AM

,,' 'refresnlfle'nto"f'for:ther:O'MAitsert If'it:i1n6hhe

:DMA'6hhs

f10l0

r:.

"; , ARBITATION: LOGIC:Qutputs'the

i

HLIDA1

,-sigil'al!'to-the) ElMA0 in

\\:,'

_ 8C4751./.'

:l.j':'

<I:" '.;i·! ,:, !:i-xl ,"!

lJ;;']~j

':-}Ii~)

!

..

;:-::'-~

j,;.l

<

.;',6:' When 'the HUlA

nnpUt

'is'HiGFi:l~~

bM~Cgains'i:oilWdr01I1he

)1'~,;

b-U's

:'and-!

dutputs

HIGH

'le'veP

'AEN~'si~inal;!td;'putqlie:~'ffie(n'6ry

I'"

)!'j~)addres'S1(bli,

:the,'bug,;'-,Sinci;Vthe:"CiMAC'-can""outptlt1biilyUf6':bit

':',:m) aCidress ;signals;-'the

-S-bff

page -register.

th~tt

outputs-ani;u~pper

r\

-"

':

,~;

_ S;bit

addres's,-iS'._

provided:

irfUie

~~ySierh;;

fhl~:~_Qa~Jes'

~ddYessTng

J~;

:,j!-Up)'ta,:16M~bYte

:mefiiory:areas';-'

';,nl-~:

; ,-').:_)'\' ']

',n-~,-,i';i

Ii

~",

-,'

'),1,

When-;lhe'DMA·tfah"sfeHis

ao\fte-by'byte'

oaSis/SHE

is'LOW,

'1

" i"proviCfed,th-aUtie·SAO

is-HIGH'(O'd~::~dCtressr)ln;'the'word~by';wbrd

'1'

'-tr'anSfer;:ttiis)6j'rcui(fdi"ces'-b~th'the

8'Ao'-:aii(j:

BH~

,slgnals'lb'w.

:

)f\('1]i(Refer-'to~F.igore'-2'':2S--6n--this

pointy

,j-,:

:7;,

:0,

,,:

;,),

-;,

i'

u,,)·

~:J

7.

The

DMAC

outputs

tlie'I}AC~sfghajt~seleiifihe

riic(lfiisiing'liO

device.

_"'j"1·>;;.i;~i_::--:;,,

I'·)jlr",i'lt) X',;(:

-)(Jj

,OJ_'-'::

:-;

_;

'1;;';,;,

8. The OMAC activates the MROC line to read data from memory
and load

it

into the

1/0

device, or activates the MWTC line to

read

data

from the

1/0

device and load it into the memory address.

9.

The end-of-process (EOP) Signal is output

at

the completion

of

the DMA cycle.

'2-2:11."

P~int~r

'In.te"ai:~

.aridSYst~ni;$t~iti,~;:~~rt

,]

],,'3)/']

,C:1r,Cl.ut

(FI!ill!r'i'2-24.and,~-25)."

',,"

,",:

"I

',)1

i~i,~~,~~.,~~:S~,s~~-~~

_~,

!~n,~io~c;tl)

bl~8~

9.iagr~f119qhe,

~~i~~~.~:~~rrt~ce

;;,;.9

i

!.?_ui!.,

"~i,~,

,?i_~cu}t

.~_C?~,s!~t~

,~f

,!~~

,pri~t_"

clCJt~,

re~is~er"

~PIt~trLS,~\'us

port and printer

cont~p:t,~e,~\~~er:_IT~~.;,p~ir:ltA:~t~(.~!:g!.~~~I\)Y'~~F~1

is

,,,~~si~n~~

,.~t)~~:

1'"11

.~?~rr~s,3,~~11

c%

2781;1(s~l~ct~<!'~Yo;pm~w

r;.,Yt?l_

,~t~r~~

_~a1a

;t~:,

~~

:~~n~;,!o_')t~'r

J)r~~t~r:.l~~~;~~~eu~

Rfo,~is

):,~~~I~!~r

'9~~"

q~"

r~-~~c

~Xi

~hr

_-9~U_;~~

t,h,~:

__

I.{p:

f1~q~e_~~

>~?a!:liJ~i1Jli\,the

biJffer_JhE!.p~inter;_stat.us

port reac!s.status-informatiorl

se~tfrom,

the

"(-"-)'-~-')

'lil.,,-

':),

'-"I)

""';,jo)

i'

'--;',)

,_'I.,

'.'OJ

:,-,

i--";'-'j.J

d.:u.',

printr. This port is assigned at the

flO

address 379H

or

279H (selected

by

DIPSW

S4-2)

I

• " I

'1',:')

,

The

pnQ~er.

~o.ntrol:

regIster stores ,control cbdes to be sent to the

printer.

Ttlis' register

i~dis'sig'ne'd

at the I/O

ad~r~~,~

~~,AH

~r

27 AH

(selected

by-

DlP~W

84-2). Bit 4 of-.this register-determines whether

'.

the~_ACK

.'siQIlaF'trom the',pri'nter

r-Oakes

enable

_dr

disable as the

CPU _ inte,rrupt

sign~1.

Whe,i"

this.

~it

IS

HI,GH,'

Iniefr.i.lpti9[1_

i_s

~isabled,

The contents

of.,.th,is

register can be read,by,the,CPU at the

1/0

ad!1ress; Figure

2~28-shows

the timing

chart~fo~r

pri(lting.

t-"VI i '

,-

,

System· status port

The-system-status'port is a register

provtde<:fto>',~llow

sedsing the

present system status by

means_of

sottws.r~;_lanct-is'mapped

in

the

adcjress same as

thE;!

printer port.

8e~

Tabltf2qO·'forlbit'assig~ment.

Two signal'Jitles are allocated to each

I::jjt~

'and-altefn'ately 9

hanges

(toggle) each time the address 379H/279HI-is

.read:,

'It is possible to

know by

intert6gatiii~"f

the bit 7 wfiich status is being cfiecked.

To know the correct status, 379H/279H must be read fir$t, then

, 37AHJ20-rA':shbulcrbe a'ccessed-lb -dfecl(! ttle-'bit' 7;id'kh6iN which

status

:rs!bein~ychecKed.

'-'

-,'

,-

;',"

'fTj

ii;;

i

"i

: j- •

:;!

,,, I,

-,

• .', ,_ i

-L ~ ,

,;

_1j.:.

I,'

'J!;i~"

,j-i!

" J,:;'

',;"

-ilL".'! 1 'I.:'

:li

n;",")f)

,':("]-,"

)iV~~)'

;,

~''-:

,,]i.

I'

:/,_

:_-'

;n,-;

,:

0

'(:-111

'

:-);)

',';'-:':;

L"I'-;;:'

;;j

':'~j:'T;;-';1

:'!,i

Jr-,),'

':,1,I.:r.;,

18

~I

I:

'-,.

--;

1

)'1.,

\1-',_"

i,jj

r-W'-l~

"j

';:',;1,"

:.":!

:ri::-j ,;i

:.>.1:)1,·0

,,)];-,',:)

'-'Ii_:

I;,g'-'/';

-,'

-I

-.,\,

.

')r)

j

.,h"21?

',:-)".;j":l'.'}

''-,r-;:-:

-

':'1'

--

---<'.

c·':2,-','.;l·;;1

:':)~:'j.:Jd:..;

',I.:; I ')/1';.-;

-"):~;

,I

J,'

;;-;r:j,.~,~

,'·;1,'/0

"::iiJ

;;,']H()~':

I,; ):'-;':;j.,'';,

~i

;!--;I1'"

,:.1;)

);,)

<J!'

:~i

'-;'1:_;1'

'Ti~

-jH

:

)1],

..

\;.

-'.'

..

':;

;,

:1'>1'

L;'

]"1]:);

I

:"1.~

.,):);'1

;:-)

\;

) ],.! \(l:)r;'1

;,:i

J"J,,::;,

'Jill

:.~i

,.~?,

:n:-;

~'1

'.:1

~

1

;".1' • .):]

(Ii

I;:rli!

..

",

l'):l'\;'v;!'

'1;jj

:i>

;'1;:;(---;

:,p;r,nj

':;Hi;

SC4752

r--

:~~

===~';;;'l';-~'

~

~-;:======:::t~~~

r--t~,~,,~",9··

:

'"

,

"

,

,

,

,

BUSY

DATA

,

t;~

,

BUFFER

"""'"

""""

mIT

"""'"

c_.

---_."

,

lKSEL1

;

,

,

,

""'~

,

,

SCHSEL

,

,

Sl'CLR

,
,

,

,

DSEL

:

,,"'"

,

- -

---

,

, '

,

,

ccr

,

,

"

""

,

BUSY

,

,

____

.J

Figure 2-24. Printer interface circuit and system port

I~

----+----i~------

r+--,~

---7--

-~

CN10

·SUB25P

Approx. 5)Js
Approx. 7)Js

O.5)Js

(MIN)

O.5jJs

(MIN)

O.5)Js

(MIN)

Figure 2-25. Timing chart for printing

2

-17

--II'O-Addr

......

378/278

liD

Address

379/279

liD

Address

37

A/27

A

-

PC-7200

Table 2-11.

110

address definition

-131

WI:

O_.n

0

Print deta O(LSB)

Print deta 0 (LSB)

1

2
3

4

5

6

7

Print deta 7 (MBS)

rint deta 7

(MSB)

Bit Write

Read

0

-

CLKSELI

SCHEN

I

-

CLKSEl2

SCHSEL

2

-

MONO

DSPCLR

3

-

ERRORP

4

-

SLCTP

5

-

PE

6

-

ACK

7

-

BUSY

Bit

Write

Read

0

STB

STB

I

AUTOFEED

AUTO

FEED

2

INITIALIZE

INITIALIZE

3

SELECT

SELECT

4

ENABLE

IRQ

ENABLE

IRQ

5

-

eGA

E/L

6

-

FDSEL

CRT/LCD

7

-

0 1

----~~B~------------------------------------------~------------------~

2-2-12.

Seriarfritei'faceCircuit'(Figure 2-26)

-The---cop~~~teF-

is.-eq~ipp~d

'.wl~~~:~f--seri~J-

i:"te~~c~--~;f;i~~!~~~\~rd!

_ feature.-I/naddressesassigned:forthese-interfaces are as

follows:---~

.:';,?,.1;

G

,;:-;;[1

flldl

:

(j·~1)O

Gf..:ll.!

)(;11':::;

i

i)

'

6\;',\1;"

,

I I

Ii!

i

; • Standard', interface:i 3F8H

thro~gh

3FFH or

2F8~

through

2FFH,

II

I I j i : '

I I

+5~

1.6432MHz i '

..

!=~N.SIW

::=ITITIT:r=j

L"-"lA:as

;lj"j'-E'J

X~?I

\F,R----p.,j

xDii'.-.~--M

IOR~

:~]~'-,

----+--1

lowc:I~',,"'----'-I

X1

fl_oD;--

OUT2

ATS

INT

ITm

XDO

-SIN

XD7

Rf

(;TIl

DISTR

DSA

DOSTRA[SD

-----XAB

-_~:-_1C".'!;--'==-+"i

'0---:)-:-1

;;;;'

-------XA1

...

" A1--

rJ1",J

XA2"

A2

e~rt"n':j'.

CS,'11<Ti'

1':'.

.~-;:

:r\(,

f;:;j

,I

;:--JT'

~,'

~,"'-;717.

-----'-->\MR

f~~T

~

__

,~8g50:l

H ',iL:

~',

I

r,.

--.J' I

DTR ,

RD

CI

CTS

pj.1489A

D·SUB25F

~

,".

~

-1-).F-;igU~!3

2-26. Serial interfact;'! circuit"

: The :serial interface

ci~cuit

con~i~ts

qf

trarasnjitte:r

1LA:1488,

reQeiyer§..:

·~1489A-

iiiiCf-the--UARf-(8250):

The

"A1488

convert

TIL

compatible signals sent from the UART to

-12V

to + 12V signals

conforming to the

EIA standard, and output them via the RS-232

connector. The convert the EIA level reception signal to the TTL
level and send it to the UART. The functional configuration of the
UART

is

programmed by software via the data bus.

The UART performs a serial-to-parallel conversion of data characters
received from a peripheral device or a mode,

and performs a

paralle-to-serial conversion

of

data characters received from the
CPU. The CPU can read the complete status of the UART any time
during the functional operation.

Status information includes the type
and condition of the transfer operations performed by the UART,

and provides error conditions (parity, overrun, framing, or break

interrupt),

The UART includes a programmable baud rate generator. Also the
UART has a complete modem control capability and a processor­interrupt system that minimizes the computing time for handling the
communications link.

When the CPU assigns one of the addresses 3F8H through 3FFH
as

an

1/0 address, the LOW level CSSIOAA signal sent from the

1/0 address decoding circuit

is

emitted to the UART. The UART

then selects the internal register to be

ZORC connected to the data
bus according to the state of the DLAB (Divisor Latch Access Bit).
The DLAB is bit 7 of the line control register. Table

2-11

lists the

states

of

registers indicated at each 1/0 address, and Table 2-12

lists

the bit assignment of each register.

Table 2-12. Register status

1 - - - - -

--

1/0

..

fil

r-

-AaXIORc

XIOW

DlAS-

;A-ddr-ess

" ,

I:

3 F

8',.,

__

'e

__

L

'I

~ i :ti~_

[ l -

---"11 ---

~

>i

R'~ceiie

Duffer

r'eglsfe{'l

3F8·:

~'.

i~

I

---i----H--

-L":

-lx

-

'frn~S~it

hading-r;gist~~'

3F8

: l

:....J

Ui

L *

*,

,--

~9~vioriJatc~LSB

3 F 9 . l

~

! H *

*:

1-

-

-D,)v~IOr

!,Iatch

LSB

3F9

L

~:

H *

*1

--:

0 _

1~t!!iruPt

en~ble

register

3FA

~:

L *

*L

IX~:~-I~t~~'ruftidettifiCation

! ''-1"' ,

:I~glster

:

3FB

L _

A~

H * * X

Line"corilrol-r:egister

,

:·JF~

_

JH

:L~

--

'l'

~

~L-

"

*-

:_j'~~.,-:-

~~odre~

control

register

3~~-

":H

iIf-;-""-H-------~:,

-~-?

:i~,-:

jL~~::~t~tusr~gister

'3"E

-;

-H

H'

---l-·

-"*'

_.

-*,.

hi

X,,:

..

"od'llI

slat"s

register

i

,L

, ' 1

,,'

_.,

"I , ,

'''l~

.. ' _"_

-,,,

i

_!

i.

-;

! i , ! i

Ll'---:I~~,~~:

i

~-~,

XIOR--6ecameslbw·at-read-oper~hionl.

~-.-:----~

>--

;,,'

XIOR-beeomes low at write

dJ?e~ation

-,

] !

*~;,:,,~OJ-~~_~!~C~~:[~j,;

.!~_=--~;)

L.~~:

.~:

"

L:~,

,':j

>

Ta6Ie"2~13.i

Regist~r-5irassignm~hts

ii.._'q

11'--~1!!

:

J:;

---'-:''''''',1

IICY·','

>

_~~!f:~

'. --i'

J

:-De.s.c~i_~t~on

..

>

'-

-l--

>

,

Address-:

' I

I -

1

..

: i

i_'-~:

t

--j

3F9~.':'rll_

.. : !o

,_

'fiJnable,

d,et','::"'::-',

'

"

Ii

Interrupt

1

..;

H-:EhabJe-TX

hOldin-~

register

emptY

interrupt

enable

2

,-

H:_fnaple

nicehce

line"st~ttrs-

interrupt

register

-

3

H-:-Enable-moQen:r'status

interrupt

,

4'-7

Always

lOW

3FA

,a

,

H:No

interryPt)e~;ding

,!

Interrupt

1 Interrupt identificati9n

bi_~

Q

identification

'2

,

Inrelrr~P\

i1~.~_~i~c~_t~0~.~~it

')

:

,

register

3:-7 '

-Always

~OW

_ " I

3FB

0

Wo-r,d

len'gtli

-ser~crbft

0

_,J.-J

Line

I

Word

length select bit

1

control

2

Numeer

of

stop

bit

register'

3

' '

parity.!'ertaflle'

:~,

:; :

4

Even

parity select

5

Stuck

parity

6

Set

-break

-".

,'.-

7

'~i~i~or

latch

access

bit

(DLAS)

3FC

-

-".

~.

>

Data

te~f1inal,.readY--(DTR)

M~·-'

,

1 Request'

to

send

(RTS)

control

/

2

Out

I

register

f

3

Ouf

t

4

loopback

~'"

.

5-7

Always

LOW

1 , ,

3FD

I 0

Data

ready

(DR)

line

'.1

,1

~

.overrun-

error

(OR)

status

' '2",:1

ParitYl error

(PEl

register

:'3

1

;

..

"

'Ftafrilhg

error

(FE)

4

Break

interrupt (BI)

'''5'''

:',,; ,:;-,1:' ',;:':11;

.;, . .-,

"',,-,' ,

Transmit

nolding

register empty

(THRE)

6

TX

Shift empty

(TSRE)

7

Always

lOW

3FE

0

Delta

clear

to

send

(DCTS)

Modem

1

Delta

data

set

ready

(DDSR)

status

2

Trailing

edge

ring

indicator (TERl)

register

3

Delta

data

carrier

detect

(DDCD)

4

Clear

to

send

(CTS)

5

Data

set

ready

(DSR)

6

Ring

indicator (Rll

7

Delta

carrier

detect

(DCD)

-

PC-7200

2-2-13. Timer and Speaker Driver Circuit (Figure 2-2-14.

Real

Time Clock and C-MOS RAM Circuit

___

2-27) (Figure 2-28)

Figure

2-2"7~sh~o~w;;;s"'th;;:e:-t;Cim=er;-;;an;;:d;n;b:;-;u"'zz;;;e'ro"nvcce'"rccc"I"rc"'u"II-,

"'1

h"l~s~c"',,"'c"'ulwl

------r:JrnLm'tVlloes U

Ie

F\Te"'(

1"4'581"8,

ael

as

a leal:ttime-clock;-truil"t

itit-ll

...

as.._---

has

the

following functional features: a 64-byte

RAM

backed

up

by the battery.

The

CPU

can

access the

* Generates

an

interruption signal when the

predetermin~

timer
becomes active.
Determines the frequency of a signal to be sent to the buzzer.

(Counter

2)

These operations are based on 1.19 MHz of clock signal which is
obtained by dividing 14.31818 MHz signal into 12 at

SC4752. The
PIT has three 16-bit counters. The QUTo signal sends an interruption
request toi the CPU via

PIC

when the predetermined timer counting

has been completed. The

QUT1

terminal is not used by the system.

The QUT2 signal and audio frequency signal to the speaker

according toi the requirements of the software. This signal is
NANDed with the signal sent from the

PORTS, and then drives

transistor

Q2

to sound the buzzer.

Command signals related to the speaker are output by writing data
to the latch assigned at the

lID address

61

H,

called PORTS.

Similarly, these states can be read from the buffer assigned at the

110

address

61

H.

Table 2-14 lists data loading and reading for each

counter.

Table 2-14. Counter assignments

I/O

A1

AO

RD-

WR-O

Address

0040

L

L

L

H

Read

counter

No.O

0040

L

L H L

Load

counter

No.O

0041

L

H

L H

Read

counter No.1

0041

L

H

H

L

LOad

counter No.1

0042

H L L H

Read

counter No.2

0042

H

L

H L

Load

counter No.2

0043

H

H

L

H

No-operation

(3-state)

0043

H H H L Write control word

---1

14.31818 I

MHzOSC

SC4752

---1

f--

.5V

-ClKO

GATEO_

__

ClK1

GATE1

c-

C,",

GATE2-

XDO

/ \

DO

OUTO

X~7\-

-j

,

Dun

PTOun

07

DU",

No!

used

""","-

~

""

-L/

1.5K

"""'-

-

""

--m-'

lOWC--

-

WR

XAO--

_AO

5K

.~

""-

-"

PI7

C;1:r'R.eS

u

"

IRO_

,j

.5V

-

~

4v;"--:

2QQ.-~

:

SP

:

~

CK

CL

~

--

-_.

0'

CN14

~

2SC1214

"

CSi'SW-

m;m"-

>00

-

~-1-

~

CSPBR

...J ----r-

MSPO
(from INTERNAL MODEM)

Figure 2-27. Timer & speaker driver circuit

-

51:475'

F.om

IIOOROSS

~,~

2-19

RTC

only when the POWER GOOD signal sent from the power

supply unit

is

HIGH, Normally, a HIGH level POWER GOOD signal

means that the system unit is turned on.
When the CPU writes/reads data to/from the ATC,

it first assigns

an

internal address of the

RTC

to

be written/read data

at

the

110

address 70H, then transfers data via the lID address

71

H. When

the

CPU

sends a write command to the liD address

70H,

a short

HIGH

Jevel

pulse

is

sent to the

AS

(Address Strobe) terminals of

the RTC. The AS terminal is used

to

latch contents of ADo-AD7

into the address latch of the RTC.

Then the CPU sends a read/write command to the

I/O address

71

H,
the HIGH/LOW level R/W signal according to the read/write
command and

LOW/HIGH level DS signal are output from the

address decoding circuit,

in

the SC4752. At this time, the RTC puts

the data of its RAM addressed by the

110

address 70H tolfrom the

data bus.

)

A~e";Og

C-MOS

RAM

Accessing RTe

Figure 2-28. Timing chart of ATC & C-MOS RAM access

"\"

m.

SC4'"

.:.

~

~" •

~,.

~

Figure 2·29, RTC & C-MOS

RAM

circuit

Fourteen bytes of the 64-byte RAM

in

the RTC are used for real-time
clock function. Figure 2-9 shows the RTC circuit, and Table 2-15
shows the memory map of the RTC.

-

---=='I'€'"'1200;c=·

------~---------------------~---

t-:J\9,d.r,e;~,~J

,::.JJ')

',J;,'

~;--'-:J-:

.~

2.;

_

~

jJ

·'-Fuqctiqr:n

"l,:.'

~-,;,,_,~,

'r'IC:'j

;,~;.yl

~OO;

_'

;-::;~;;}S

i:":;')

',j-~:

)Seconds:;,:;~-.:J

.:;ri.'

-r:

:-,j;'

)k:

::J

;/i\n

)j'(!l--:-:', '-j

l[l!r·\).~j

~)f:J

;:",),1

'-Seccffii:falarm).:.)

,-j::";',}/,-;,-~

';);ii r:,):jI,'(

fi!:)

J;';:

i:Ol

e

.):'.:'!

c,':,';'.L)

~~-:'?'--'M-j~ufe~

i'~;,:

~;~

;i'~;---

)]::)i;-;

,:;j

Jinu" "'-;:'I!n

-,,-,

"--'1"',"

-"

1.

'" .

'.'

'-~"?

9,-1'

-,--,-"

,-

-J'"

03

Minute"ala-fr'n"'u,""

~.,-,

""")',1_

":_J_.,,,

,-,:,,-,_

..

~

t~,~-)i;:~7

1~;

;~')

J;i!)_

::2-'

:1.

H~Oy~~:~)

~,';)'n::J;.~~_;~~~;:::11\;~~)j,?:~_~'j;,;:.

:,:~~;)

."~~;:

__

)~;::J

-:':'~~

i,O",5

f

'I/\,'

ill''\:

22j";jJ'---;Hgyr~~IW~~b

,:,L;)

~·:i)c,.-

__

-"j

jj)li!'

;'jfr',

-:~o-:~!<-'

,;

RYr!d

.::;

,i '!il\'

;:.:;-,}"!i-:-

!.Oay,·;of,.

weJ~kb;

~:.;rr;rilO:i

<)j:T

..

'.'

;) ;:h:n:: ':Lj,

')

),!;

·1-1),7;;:'_"'.'-ri;;r;

z·:;

(~\:';-.)

];;

~

Datej~tif.;month

,:),;;

~:;

;;';:)~;

,)i

'),;l~_;q

I'"""

,,,--:,j;-]

09

Year

:

~~;ri'J~~

"

;'~:~h

':~'I'~'.~:;

)~~):~\~~~lf~j~~~~~:~';'I;~~~:~~~

1

~~J

~,~;

l8':i~~)-~;'

~~~:;;:

.],1'

);~ll;

,C)q~

fT:c,j)

j:-,,~jl:J

cH~St~;~~_:.:.-re~~:sJte'~)'~'jl

;

i.e::::

)"/jO,J

nr;,,; ·).T'H1f.;,Yl

}~:j

:::ri-i~

J,:i ,

..

Xi';'~

,_;~~,atll\s:r;~~I~!.7E~

C,IH

ili

,1JL;:"-'

j(jib_,:~:

,_,

:_>)li~b.;

.QQ

"'-";-',,);

,'J.-;-,

';.-0;'

~!a,~u~;:r~gi~tlilr.l~c)_o~'

::r),,,

,"I

'..-;

;~l'

"j

",,1.-,;';'

:11

DE

*Diagnostic status byte

_:;.:~j

."j;,,;)

OF

*Shutdown status byte

ji

O

'\_

. .J

.~_.

/DlsK);ri~~u~'~~

___

~yt~\:J!!i~~~

_r~hq

..

'8-

.11

_

Reserved

12

Hard_di,slc.ty-pe.._byte

,-drives C

and

D-

13

14

15

+6-

Reserved.
Equipment byte

Low-'.~base

memory-byte

-

-HigH-

base-me-mor}!--byte

11-

low

expansion

memory

byte'

1 a - - -

High

'expansion

memory byte

19

-20

2E-2F

30

31

32

33

34 -3F

Reserved'
2-byte

C-MOS

checksum

*low

expansion

memory byte

:':1.,

-:

.>?lTJ:U[h,~~x!?a~si9!l

;J;r:l,emo~y

b,vte

*

Date

century byte

*Information

flags-Cset

during

power on)

Reserve

],

G) Similar as the· RTC, the CMOS RAM ishattelY backed up and

can be a'ccessed only when' POWE;RGPQD is at a high.
CMOS RAM is accessed

in

the same manner- as RTC RAM.

The-addresses assigned to CMOS-RAM' are

40h

to 7Fh.

® Six bits

AO

through

AiY

01

the'CMOS

RAM

address lines are

connected to

MA3"'S-of the' SC4751.

In

MA3-8

are latched

XDO-5

when

the

1/0 address 70H

Was

written, and sent out. In

A6-A10

are C6nnecfed with sign'afs

SA10-14

in

which latched

the

addres~

frorri"'the

~PU.

The signal CMSSEL turns high with a

!'O"

'state of XD6 when

the

addr~~~-]9~l"j§

:Y':~l11f:,'i1.

sm.9

:t~rp~.

!~,!,

__

w~~,n,)~D6

is "1". The

CMOS RAM is enabled

to

read and write when CMSSEL is at

:

l:Hbw;':arid~:the-R1'(fban

Eie:

accessechvheii 'it'

is';'~f'

a:'higfl~

,

.~

':'

'Tablei'2~+6.

&~Mo'S:

A~M,:rh~~brYl~r'rt~~piri~;

),

-j

"

1-;

-,j _ •.

_

'i

•

!';

'.'

'1

'i

'",

,');

'il,'

Backed

Up C-MOS RAM information

Address

Description

40

Reserved

41

Cursor type

42

Backlight timeout

43-44

Setting serial port

45

Logical device

46

Internal

SIO'

47

Printer interface

48

Printer style

49

Printer mode

4A

Internal modem parameter

48

Internal modem setup

4C-4F

Reserved

50-63

Printer setup code

64-7E

Reserved

7F

CMOS check sum

2;2,.15; FOO.lnterface

Ciri:uit:(Figure~2'30J

,~J

1,,!>

The FDD interface circuit supports

up

to two

fIQPpy_.aisk

drives.

J

f;=igu

ref)

2~32Yis:~arblock,:diagramj

6t

this-:ciibuit!1

Arr,'

F-DC~;a.PD"l6qf.'iC

(manufactured by NEC) is the-_hea'rt:cifthis,circuit,:,'at1d;Jtinte'rfaces
between the floppy disk drive units and the CPU.

~rrh'ei

comj:mtei"~was~designed'"·sd~,thSltittc-an::re-adl-data

froin:thEnFDD

at three different transfer rates, three of them-250:Xbp-s;,,300Kbps

,'a:n-d::600rKbpslNFOs

:--_la.rel

ioi::luded

irp,thSl,lmeMcliip:t:.SI-:MB4rD7.

The

DIR

(Digital Input Register) was originally

an

BfbitJ:,ead,only

register; however, since bits 0 through 6 of it are used to control

;~ha'rcVdisk,rdrives;-~bnl~

bit:7 is

-used

'for::FDDS'..

Ttr~~DO.R

(Digital

<-:O"utput-

Regisfery:is

a'WrffEr-qnly:r.eg'isler"J

If

seleGtscdrive~··ar.rdl,control

,-th'e-:FD0c;~

.,

"

-~'::~.-:,~

L-,.1

,-W, ;-!

J,)

:~:'i

r .aJ',jJr:'y-x)

):::i-~j

1 a.'ll.-ij

<:;~rl

Tiel

::Thers:' is:

a:DCF.I:.(DrLve..Contro

I :

Regfste'f.,)',

'-pre.:compens-atibtr cirpoit,

an"d~'Glock!jgeh'eratioili.'circujts;as:}btf1Ehi;rnteriface:'t:itquits)

lihe:::DGR,

1

a:-2;.bi~w(ite-orily.,:register,;.sehi;mtS'

thEi~cIQck;

frequency btrttie

FGCK

(FDCClock) andcWCU«Write <!:locl<},andSelects the

V"O~ifc"it)oB

:]'i:jL)

.:-;:);!l

~:;:.'3

,~{:-;::(r:-i

:j;-!j .-,;'):1

j!j-j,,~

:~;;;D!:;

If;)

JdNJ

~)~-)C1:ilA[;1

"

.,,'

,---,

:-;:;~:::'r,-i~

;_:;J:;1i;:,~

::~,~,!;:,,!"~~

.1';":'==:J~==E:3f:;=~:;=;==~~';===:::;T,uJ_i.l:'"-

I'

"~"'"

~==;~"j'rg;

F:igure

2~30.

Block

d[~g!~m

6f_F5o.il]terfac~

_

2-2-15-1. FOe

,

,~

c_

••

'--

The FDC employs the "PD765AC device

in

the SC4752LSI. Using

a data

bus,,\the-E.QC

~ansfers

status

a~d

data corresponding to

t~e

command sent

frorn--.t~CPU.

To

detect the selection by-the-;CPU,

the chip select signali ajld

AO

signals are used.

The FDC has two important

regiS.f~~s:,a

stafu~,r~gister

and a data

register. The status register

stor.e~lt!1t3_:status

information of the FDC

and floppy disk drives. The

E\tatu1s_,

register is ,assigned

by

the

VO

address 3F4H or

37414

and the data rt3gister !s)3F5H or 375H, Table

2-17 lists

th~

fP

__

ioterfac,e Signals. ' -..

FO

Interface

CLK24M .

24MHz input.

CLK16M . 16MHz input.

ENI:lIR

DS1

,

,

;;'Port

~ec~de

~ig:n~1

to read drive

statu~,

?ctive low:

drjv~

1

s~le~,

~ciive

high.:

;,

,:

I

prf~e:2

selec~,

active high.,

DS2

I

_,I

MOTEN ,1 Drive unit;

mo~o~

ehab/e, active-high; . )

...

",

- """, 'ii

HS1

, '

):

'--

-

..

'

Head I select. $ide-1 when

high_.

STEP

Head ,stepping signal, active

hig~.

DIR

Seek -direction signaL

WRTDATA Data write to disk.

'--',i,

l):)l.Oi

-J

WRTEN Write enable, active high.

--

~~-

maexpU1se Input from drlve;-actlve1ow:---

WRTPROT Write protect indication, active

low.

Head

track 0 signal, active low.

RDDATA

Read

signal from

VFO.

WINDOW

Read

data window signal from

VFO.

MFM

MFM/FM discriminating signal (MFM: low).

MINID/STD

Mini floppy disk/standard floppy disk select output

(standard

floppy disk:

lOw).

DA

Output

to

indicate the

MB41

07 external VFO data field.

VFOCLK Clock output

to

external VFO

MB41

07.

FDSEL Internal

FDC

address select input.
03F2H-03F7H: low
0372H-0377H:

high

CLK19M 19MHz input.

CHGFLT

VFO external resistor select signal. Low

in

the 2DD/2HO

mode.

TABLE 2-17.

FD

INTERFACE SIGNALS

2-2-15-2.

DOR

This register selects drive A or

B,

controls the drive motors, reset

FOC

and defines whether

to

permit

an

interruption

of

the

FOC

or

OMA

request or

not.

The

OOR

consists of

16~bit

flip-flop circuits. Description for each bit

are listed in Table

2~18.

Table

2~

1

B.

DOR

bit descriptions

I/O

Bit

Description

Address

3F1

0

This

bit selects

the

disk drive.

LOW:

drive A

(drivel)

HIGH:

drive B (drive2)

I

Low

level

of

this

bit

enables

the

drive select

signal.

1

FDC

is

reset

when

this bit

is

LOW.

3

HIGH

level of this bit allows

FDC

interrupt

and

DMA

request.

4

HIGH

level

of

this

bit

enables

the

drive motor

and

the

drive A

can

be

selected.

5

HIGH

level of

this

bit

enables

the

drive motor

and

the

drive B

can

be

selected.

Data transfer between

FOO

and

memory

is

executed by the OMAC

and

FOC.

The

FOG

sends the

OREO

signal to OMAC when data

transfer to/from the

FOO

becomes enable. This signal delays four

2MHz clocks

(2

ms)

for adjustment of

OREO

timing. After the delay

the signal is sent

to

the

OMAC

ORE02

line.

After passing through the tristate gate, control

is

done by the bit 3

of the

FOO

control register.

When the

OMAG

receives a

OMA

request from the

FOC,

it places

the

CPU

in

hold state,

and

then sends the OACK2 signal to the

FOC

after it

is

ANDed with bit 3 of the

FDO

control register to begin
data transfers.
When the

byteMby~byte

base data transfer

is

completed, the

FOC

sends

an

interruption signal via the IR06 terminal of the

PIC.

In

this

case, if bit 3 of this register

is

LOW,

the

OMA

request and interruption
are disabled.

2-21

-

PC-7200

2-2-15-3.

DIR

The

OIR

was used

as

an

B~bit

read-only register assigned at the

170

address

3f/H

or

377H; however, 7 of 8 bits are reseNea

fbt

hard disk drives

in

actual use. The CHANGE signal selects this

CNG

signal. This bit

is

active unless a disk

is

present and a step

pulse

is

received

when

the drive is selected.

2-2-15-4. DCR

This write-only register

is

assigned at the I/O address 3F7H, and it

selects the

VFO,

and

sets the condition of the FCLK and WCLK

signals. Table 2-19

lists the bit assignment

of

this register.

Table 2-19.

OCR

bit assignment

Transfer

FDC

Write

Applicable Applicable

Bill

BilO

Rate

Clock

Glock

Drive

Medium

l l

500

Kbps

8MHz

lMHz

1HD

1HD

l

H

300

Kbps

4.8MHz

0.6MHz

2HD

10

H l

150

Kbps

4MHz

n.5MHz

10

10

H

H

250

Kbps

4MHz

0.5MHz

10

10

Because the data concerning the disk drive type

is

stored in the

RAM

of the

RTC,

the

CPU

read~

the data before it accesses

FOOs.

Then the

CPU

writes the data to the

OCR

to select the VFO and

to set the LOWDEN. WCLK.

VFOCLK and FCLK signals. A 2HD

FDO

can

also read a

20

medium.

2-2-15-5. Clock Generator Circuit

This circuit

is

included

in

the SC4752, and generates the signals
listed below.
FCLK
A clock signal for the

FOG.

It

is

switched to one of B MHz, 4.8 MHz

and 4 MHz

by

the

DCR.

WCLK

The

FOC

synchronizes write data with clock signal WCLK. The
frequency of the WCLK signal can also be switched to one of 1
MHz.

0.6 MHz and 0.5 MHz by the

DCR.

2-2-15-6. Data Separation Circuit

Using the VFO, this circuit generates the window signal to separate

data bits

and

clock bits from the raw data read from the

FOO.

VFO

used

in

500Kbps, 300bps

and

250Kbps transfer rates are included

in

the one-chip

LSI

(MB4107) respectively. Table 2-20 listes the

assignment of the

VFO.
Table 2-20. VFO assignment

FDD

Medium

Transfer

Rate

ClK

Bill

of

SitO

of

WClK

DCR

OCR

2HD

1HO

5nn

Kbps

8MHz

IMHz

l l

2HO

10

300

Kbps

4.8MHz

O.6MHz

l H

1D

10

250

Kbps

4MHz

0.5MHz

H

x

2-2-15-7. Pre-compensation Circuit

This circuit

is

included

in

the SC4752,

and

advances or delays write

data sent from the

FOC

to the

FOO

according

to

the write data

pattern. The

FOC

changes the -status of the

PSO

and

PS1

signals

in

response to the pattern

of

the write data sent from the CPU.

Figure

2M31

shows the timing chart of this circuit.

Table 2-21. Write data pattern

PSI

PSO

Write Pattern

l

l

Normal

l H

Late

ODD

I

or

110

H L

Early

10000rOli

-,

~------------------------~-~===---=~-~~-

----="R€L';'1-200T'"

PSO

PS1

-",'

I

I

Shift \

"

'"

,-+7''''''---C~..=;~...",.rc.J~n.C·

: n ;'i

~Figure;·2~31lrrriiTling)'chart~of;pre~b0m'pensatfO'ri

cirCui~-;.-;:

'

2-2-16. Keyboardlnterfac&{Figure:!-32 and 2-33)

This_,-.-i~terf~ce-.

circl:dt-:emp1o.Ys--

,tlTe

.

p~e~Ghi~-i~rnJ9r~p-rocEf~"s"Or

8742,

and "is' assigned 'at

1/0

addresS

60H,or 64H. This:processbr.:has a

"

"t

.-

_

'C,

__

;

",;

I

,I;:.,

. I

2KB-

ROM-

ahd

-128-byte

RAM,

and,

[nterfaces,-,between.

the-keyb0ard

an~

tHe,CPU.

The 8042

redeives

serial

key'-scan

:codesico~si&ting

of

~an

8~bit

key code

'arid

-~

1-Qit

paritY

senf:from;thEt

k~yboard.

It

copverts

th~

codes to

la

parallel:

fanTrat

sy,stem

sca~

cdde:to

:be

~ent

to

.the

C:PU.

:The-:80~~

aJsp:receiv~S_',Gom,m_~nds;frqm

,the~CI?:U,

land

se~crs

commanas

To

-tfifi'keyboarCfafter

inte-rpretinglfleri\:-'~---'

"[In

:additiori·~to~

'the:'n:'mctions'

'describe:~I"."

abovepthe ·keyboard-.interface

~

caifmodifyjhe

keybb'ard,

interfaceeprotoC6r'andi

tne

keyrs'Can'cocfes

;

);durfrig·,.power",on-:!

initfaliiing.,·l[jj c;l ;,j','-;')

}ji1

;.;

:);:".'N,

.U:·j;") 'j:':' [

-,

'!;

.

J.Witt:1\

th'e:;

fQ.rrr

outplltderniinars;ah'd"tWQl~iripuet~Hiiji1alsi;

ttie'.'8042

performs the following operations,i;')c,n:1: '1.->1';

,'1

,!_.

'y

• P16 (input)

Detects the type ofaJ!!lisplay-adapter!ce:aaing;Jhe"Stafusof·switch

";-:S:-2.')i:~'

,nw'

i',',

,r)

,'j

I;, !-,,)').I:

• P17 (input)

...

INH '',I:',;

::Read~:the

:sfatus:ofcthalkeylock'.f,on:vSC4752·LSI",'I.fthe keylis

locked, this terminal is

LOW,

If it is LOW.)tlll8!,k'eyboar'crinterface

cancels data from the keyboard,

" P24:(outputl, ,

.•

,;QPT .aUF

~ULL

;

A,

one~byte

data-,senUrom

,the;

kyboard

makes'

this

termil'1al.

a,ctive,

indicating that the output

buffer,

in

the!'i

Keyboa~d;

ineJrfaGe

is

fLi11.

This signal is sent to the

IRQ1

terminal of the

PIC,

requesting

that the

CPU

reads these data.

~

-,

.-',.'

"j

<~,

P2l,{outpu!)· ,,,,A20GATE,,, .

I,

'"

i.""

.),

: 'Whetfthis)

signa.i-:becomes',

LOW,,:the~

A2Q:'signab

cm;.theiaddrsss

:.u:,bus!:iSlforce,d;to--LOW,; dl_:.:;:i-'

;,,1.>

-.;

:i.!'),,:

';;'j~j)n;;:·

:'11;

:,.-~~

p2p),,(o~tPlJt».!.,,~R_C,"\"-.'iJ~-n2.''''

(\~'. '-~\,r

~e~'

.~,

',.-:-,---,

-:\~\i

When the

CPU

requires a change

in

its';'operation.

,mode;

from

protect

mode

to real

mol;!.e,

it

sends certain commands to make

the terminal

HIGk

tke'Rt'~igrla:hs'se;;t'jto

the

SC4751

and

the

- • 1

~RP

~E~~:~~ighar'is

,gener~tecf.

"Ff~~lIy'-:

the'

CPU

Isireset and

thus

return~

to the

real-'

mode:

1

,)

, -

.'

,

""',

'.'

I

•

P23

(output)

..

i.

KEYINt>

si-:'

-r ' i

":

When;

a key depressibri'

Is

s~:n:~edj

a

s'hO'rt

pulse of

IQw

5t~te

is

~enttbtl1e

Sc4?~~,

'.,

i,

..

_._,

<~'.

L.

_ '

'.

The keyboard and

the:_keyboard-i~terface,

are,

relatetl

by

the

KCI:!K

",,~~9

_-'~DA

~A-!ine~_

Before~th'e

"8042

--seri~~-cja!~;~k~l~ay~,

nl~·~e$~i~e

,,~qLI5

!i,~e

HIGH

andKDATA

line~9"V;,

T;h~.key~qeri!;C;HIJ,a[",~ys

',,~?".i~o~;J;h~

..

sJa~lI,S:

9!

,th'~~~:J~~

UP,'1s:-:,If),!h~,)~q;

Ijne:!?ra~e:l

!~':me

\ 9

qn

p

i

t':9,n

;8:~9:v~,.

!~~-;~~ybSl~~,9

~me!1:i

!~je;j~~~aJ~c~ptiQrH')1~d.~.

,:

Them

the 8042

~!9rJg!;La,~"~t,'llr;tb,ik~n

~:,~i,tL~a~~;

<?;'p[l~bit:09q"P'q~iW,

and

a stop bit to the keyboard synchronized with the KCLK signal

sent from the keytioa'r&',i

',i.i0

');::'jj

j

~.,,;

i;·

];'11

Rgure'-2-39"shows, a

-bJoc~di,agram

of this circuit,-

aml,

rigu.re·,.s~10'

shows·the timing cnaitJj'n

data'transmjSSion,;-.~-:-~~

,-

'.'

'

~ESIIT

'""

,

,",

-:--i~~Lg]~

;"

';'1;)11>:i",\:

;!.:

Jj!

I)

2-2-17. Display circuit

General

The display circuit consists of three LSI, CG-ROM,

V--'l~Mdl,nd

]SbinE{~lS:.

'I'

','},

'_,

,.,",

t;·.'

!.l-)j",

';;~i,:J!

!;~'iBl.'8

r)7/

TJ":,:,,;-

It

has three interiaces - CRT (720x350) and LCD'(640x200) -

and

supports five

dlspl?lY1iFT;l~pr;$1~S'I~~lo~.

MTM(text)

CGM(tex.t},

.,,"

,

CGM(text)

4

CGM(grapbic)

,

640

x

2~0

dets

CGM(graphic)

350)(

2QO

dets

,

j'

. Specifications

.;;

"J:,

':

)

1.,C;GMCCaT,

J

..

CQ)'JIVITIIIII

(L.CO)

....

, * Displays

80'><25

or;4b~'2'5~ha:tacters

on

bri'e'screen

* '8x8'-pixel's::f6(cine':ch'aracter, bdx -

: *

7x7

pixels for

one

character

\Wi~.~;

9.~af;"m~~!,~tt!i!?l!l~,!

,'-::

:in,

';j

>.i",

J:

~~)!.

*

Can

display 256

,~i.~,~r!1m

~h,ar;~qt~rs;:l

/,"

~

Video

signa!:

14,31~18MHz

maximum

*AV-syh~dSJgW~I:';'6i:lt~{i':!

!I>

:1',; .',

-';..-h,

'.

":,

• H-sync...signal,-15J5kHz'.

'.,',.

'"

2.;"M1M

,(CRT),' i

!'l

>Jr'"

',.",

!"

:,:.)

:6,s~(~y~

80'j(.~5.~&hkr~bt~'r~'

;irr~nl~':

~6~~~~,~

,'::,:::'

j:

i,

<,

,;

'J)

-,,'J , ',,, \ ,'"

n'

",J

'~-'

."

"-'

."

",,'

..

1;

",-,. " '.' , ..

/ .

,'-""

.,'

,',

J;:) -'.,'."

.

."

9x14

pIxels

fo(one_~h~rl3<?t~~.,~o~):,,;.)

",-1;

~~

·t':~-j

~i'

."

,7)'$91p'?,els.forq!1etcl1~racte.r

,,,,'

,:',

.'

'\

.'."

,,1'

,;1,,:-

*

'bah

drive

'an

18kHz~ni·onbch'rtllneJdisplay

~bhit6;.,

,

,'}'

.

*

Video

signal: 16.257MHz maximum ,),

",j"

i""",

y-sYnc.sig~a!;,72Q:,35Q,(H.XY),

5QH~".

' ,

.,i,

, '.

,','.

'*

H~s'y~c-'~)g~ai:~,1~;4~2ki{t'

",',<

.. ; -',

,'"

-;"H1

!

..

, "

."

"'''','

---',',

...

J

·,11..

.'

".n'"

'-'

'-,

.J!

. < )

,)(!

:

ii.:"

,.

L'

",'

.'

.),;

..

;";

;.),.

"I

',i"1

Vidoo

t

R:G."0

-

I

Hs

IHapi

HOlsP

I

HFP

1

1 I ' I 'I

H-SYNC

----Il

_____

--'nk-..._

I

HO

.,

Video

}

R,G,B,I

VOISP

V-SYNC

VO

HP

HS

HBP

HPISP

HFP

VD

VS

VBP

VPISP

VFP

CGM

64

4 8

45

7

16.5

1

2

II

1.5

loox25

TEXT)

"

"

" "

"'

m'

ms

m'

ms

ms

MTM

54

9

0

45

0

20

I

0

19

0

,s ,s

" "

"

m'

m,

ms

ms

ms

_ . . positive ... CGM

*The

signal polanty IS

negative ... MTM

VIDEO

OUTPUT

WAVEFORMS

Reg.

Description

#

RO

HORIZONTAL

TOTAL

RI

HORIZONTAL

DISPLAYED

R2

HORIZONTAL

SYNC

POSITION

R3

HORIZONTAL

SYNC

WIDTH

R4

VERTICAL

TOTAL

R5

VERTICAL

TOTAL

ADJUST

R6

VERTICAL

PISPLAYED

R7

VERTICAL

SYNC

POSITION

R8

INTERLACE

MODE

R9

MAX.

SCAN

LINE

ADDRESS

RIO

CURSOR

START

RII

CURSOR

END

RI2

START

ADDRESS

IH)

RI3

START

ADDRESS

III

RI4

CURSOR

ADDRESS

IH)

RI5

CURSOR

ADDRESS I L)

RI6

LIGHT

PEN

ADDR.

IH)

RI7

LIGHT

PEN

ADDR.

IL)

-:

Not used the function.

"',""

""

....

c9

'-----'

-

PC-720D

Figure

2~34.

Block diagram of display circuit

2-2-17-1.

Internal Registers

of

the

MN12BB

(Table 2-21)

There are nineteen registers in the MN1288. They are used to define

parameters for the CRT monitor. The Index register which is one
of those registers,

is

used for a pointer to the other 18 registers.

It

is

assigned by the

CPU

at the

110

address 3B4H for the monochrome
board or 3D4H for the color board.
The

Index register must be first loaded with the necessary register

number, and then the Data register

is

loaded with the information

to

be

placed in the selected register.

The Data register

is

assigned by the CPU at the

110

address 3B5H
for the monchrome board or 3D5H for the color board.
The following table shows the value that must be loaded into the

MN1288 internal registers, and Figure

2~35

shows the each value

on

the CRT monitor.

Table

2~21.

Register definition

2-23

Read/

Write

W

W
W
W
W
W
W
W

W
W
W
W
W
W

R/W

R/W

R
R

(NV01

VERTICAL
DISPLAYED
CHARl\CTERS

MONO.

Color

board

40 x 25

80 x 25

GRPH

Item

Unit

61

38

71

38

Nht

Characters

50

28

50

28

Nht

Characters

52

20

5A

20

Nhsp

Characters

OF

OA

OA

OA

Nhsw

Characters

19

IF

IF

7F

Nvt

Characters

Row

06 06 06 06

Nadj

Scan

Line

19 19

19

64

Nvd

Characters

Row

19

IC

IC

70

NV5P

Characters Row

02 02

02

02

-

00

07

07

01

Nr

Scan

Line

DB

06

06

06

Nr

Scan

Line

DC

07 07

07

Nr

Scan Line

-

00

00 00

-

-

00 00

00

-

XX

xx

XX

XX

-

XX

XX XX

XX

-

-

XX

XX XX

-

-

XX

XX XX

-

HORIZONTAL

TOTAL

CHARACTERS

~~~~'

..

,~------~

(1'1,

+

11

.""

,~,

I-+--+--+-----------f----j

~~RESS

HORIZONTAL

OISPLAYED

CKI\RIICTERS

Figure

2~35.

Register description

-

--

____

~_~n~~~~-------------------------------------------------------------

2.2-17-2. I/O Map

of

MTM

"

!he

t:a~Iej,b~I?YfSfl~~s-t:h~-T/2~if~r-e~~~,~SSighm~rt§:'~nlJe]lj1TM;·

c,

i

",:

:',"',.':

,:

',,',-

__

,-

! i

_'';

1-

,.'

I '

Ta51e'-2-22'

1/0

'map of

MT.

M '

>. -..

: ,

" ,

I '

,

I/O

I

' I

",1'

I

D~_!;.!;ri~t~o.~j'--

'C, , _,

..

Addr.

,;=eo--

3B4

68B45

in~ex,

re:grste'L~~

-

3B5

68845

jrata

Jeglst~r

3B8

CRT

Control

regi~ter

c·

.

!

3BA

CRT

Stantus

regi$ter

'*

CRT Control Register i

I

,------------.

__

••

_______

_

This write only register is used -to--control the MTM. _
Table 2-23jrG"Rli control'

regTstEifJ-';ib

~b-\in

i','

li:-;I

'-;-I/7,;O:-:-:)C",r:"~lC~~.

,"';."T~".-j"J"'.7';,':')

-c

__

":-_-:

~-~..,,~.;-,

"'''~;-.'';

,""

-."ee,

n-,",:";

s-·,.....,

-

'~·t

<>~~

Bit

CRT

control

registe~'

2

'--'

Add

...

.

.;"'"-'\

____

.J"

/

"'3-S8

r,,";

--.1":0

T_,i

I

..

0-->'

,'j;"

';)'"

'I,

.,"

,-;;

"'-17!: I

'~'-_;J

J

,;"

_11,;

')

;'l,.-j r

'~n

;;1

T,;~:j;';'/

,::J3j'='3~

;,8;:;'i]

!-i,iT

nl.,u'il

r;'~:'!

.-,;'; :

I,

A;

~,-ji;):;'!:,q

j; . ;';,t;.w;::n

31

,''ll-iiG

i:

iT

,)J

n1;

i:

_,

i

:,'

iy)'!

:_:1

,

''1

:0,

te)

0\:10,fi:J'~:-:~;i,'

;,-ilbi;

,>S>;2'.;3:i.;:-_~;;';'i-.1,~:Ji.,:.!

j:)'-,,:J--'-ji

0-:""',,'::

3

Video

enal;l!e;-;

;'1

;;)1.'," 'i'l1

:.:'.[

f ;':

'-!-

10

':

:

3c!:~y-Jl

(:.

n.~41

';1)

Fkl'll ;)',0.0')1

~--!;,

j'!;

'::I~i

:';{~rJ_

,li

-,

,I

,1

;l;;i:l:y-,li-;i

,-)

]j

I

i~';j

:

'-'SlrriR:

enabT~k:H'11

. ;

iJi

i.,

, ,

~:

! ,j -

'l

i; , ;',

,r:'i

'J',',::

.-

_,:~;)

___

;

!''-;~:,I

1.

'-' _II;;

,,'

-l,"

",'/'1,1_,

J:.,_.,

I.ill

..

,)""

.lrl:

'4~':~~~~~~y~~~~:~?is;

u~~~d;

t~

:ci~~dk

lig~"'~+M:"f-~a!l

i'~,

~~'~J~her

the

H-sync

or

BIW

video

signal

is

output

or

Hot

'dan

b'e"judgscf

via

this

register

:-,;])-:_-:1)

....

Table

6ig4.

CRT

~ta~ya

regisf~.r

---

Bit! .

:,6~s~'ripti6~---

,'11;.,

;1:,,'

1 I

""l

l

-"')~

'-i' 'l,n 2

om'

.,,'

3

,

H.,:

sync,

,

'-,1

,

, ,,- i

,_

\ J :

2;Z17

2

3:'i/o

11118'of

CGM'

Th~:t~bl~j6~:I\b""

~hd2~"t~'e

lib

addre,~s

assighmentS'9f

t~e

¢Grl

I,

.

Tabl9 2·25.1/0 rriap of

qGM

.

,

I/O"

Description

A'ddr::;,J"

,

"

3D4

68B~5

Index,ireg'_lsterl

305

6884,5

Data

~egi,~~er

,

3D8

Modk selectj

Re~1'ste:~

,

3D9

Color

Select;

Re_~iste~

3DA

Stat~s

Register

,

*Mode Select Registel;,

This

__

6~bitwrite

,only-register-is-

used

Jo_

dejem:TJi!le_tb,e_display

mode

·and,brinking

attributeofJheCGM,

"""',,,

I' "

.I'·r:

I

----

. - -

-----,

---~

" j

-T

-,

"T~b1ei2-=26.

-Mode seJect

_[egis.~eJ

,

I/O:

:

Addr.1

Bit

i

Description

3D8

I

0

H:

80 x 25

Text Mode,

L:

40 x 25

TeX:t

',Mo\:le,

I

~:

' .

"

1 Graphics Mode,

L:

Text

Mode

,

'I'

i

2

~~Iack(!~_ite

Mode,

t:

c~lor

_

Mod?

I

I' -

j

H:

Enable

VIDEO·Signal~--C-DisabTe-V.IDEO

Signal

, "

'.-4

H:.

640 x 200

Black/White

Graphics

MQde

I"

.';

- -----

-

-.---.

--------,

-

__

_ , _

_J.'

5

Hi

Chan_g~

-

~,?lckg.round

intensity

to

blinking

attribute

Table

2-27.

Bit

assignments

I

-J~

)

,

0

\

Mode

!

__

'____

~_

...

;:;.=:

Bit

-

--~---

~

b=:::

:-.-_

--5-

..

____

4..-::....:

;:,=i--I--2--__

l--

80x25

(MONO.).'l'''''

0

~I~~,::r

0

1
1

'J,'

.,_(COLOR) 1 0 1 0 0

.

_!Q.,x

25

i

dM.w~L

__

.Lr-.!!.

___

L

-1

...

..9.

(9,OLOR)

'1'"

0 1

],

320x200 (MONO.) X 0 1

(COLOR)

X

0

640X200

X

0

r

)--"

\

-.,

~~.J~

'.

*

Color

~eli;JCt

Register

,

This

6-bil

write

only

register is

used

to

determine

the

selection of

screeh

cblo,rs_foLtbe_GGM

__________

"j :_____

)L',-

L.

U'J

Table

2-28.

Color

select

register

,.J

.. ; __

::

J-

T _'" T-:::':',-,",-::, _:-T _,. • - I

)/d~'

Ad~r.

--:'3'D-9

--

o~" i '·~'ru~

1

e,'

,

'_I'

1,',\1<

c,',

:;--T--~;---,-

;)

--j---~'

-j---:l"

f~--';}f"

"

..

1

1 !

--2-

:

Green

-'Red-

,}'h~s,~,

bits

'.~ele~~,

tre" ,?order colo'r

in

.

--text-mOde,

Jjadkgfound~Golor-in_320-x.200

3

Intensity;'~,'

)~mode

.o~

fo~e~r~~nd,i~ol~~,.ml

~~~:'~lZ00

Select background color

in

text

mode

or intensified

s~t'l'~f'

tdrMilin;:~N~~hi~s)ri,dd.'e.

Select color set 0 or 1

in

320 x 200

mode

When

this

bit

is

set to

1.

the

color

set 1

is

selected.

When

this

bit

is

set to

0,

the

color set 0

is

selected.

Table

2~29J1Ctilor

combinations

,',"

I '

COLOR

:,\i

'.

",

;

~¥j

.:;1-::'"

,

I R

G B

,

BLACK

(,

"

..

0

0

'BliJE'

0 1

GREEN

':,1

,.

0

CYAN

b

0

RED":

_

....

,

-

_~

_1',.'

0

MAGENtA

:?i '.

0

1

BROWN

,

:'/

'0

0

WHITE

j'j

J;',:

!;\

J;,

-,

..

0

GRA'y<

:'.1;

I:',"

,)

1 0

LIGHT

BLUE

,

,1-,

0

LIGHT

GREEN

l' 0

LIGHT

CYAN'c,]' ;

,

',jl

LIGHT

RED>"JN"

"

,

>1

1

LIGHT

'MAGENTA!"

'!~'

:

YELLOW'

-

-;,

j)l'~:,::f.

WHITE

'(HI.cINiTENiil'rvjL

: ,

')-!".

: I

;

i:;

---

--------_.-

Table 2·30.

Colori's'etstaole'

CO

C1

COLOR

SET

0

COLOR

SET

1

R G

B

R

G

B

0 0

Background

color specified by

Color Select

Register

0

1 0

1

0

0

1

1

1

0

1

0

0

1

0

1

1 1

1

1

0

1

1

1