Sharp pc-2500 Service Manual

PC-2500

SHARP

1. SPECIFICATION

o Keyboard

layout

1

0-~

:

1

2 3 4 5

SERVICE

4

-col

or plotter printer (DPG-29

0-rrr:J

)

6

B I:

MANUAL

CODE:OOZPC2500SIME

MODE

~~rn~

7

8

:r~r:JE:JI~Jc:~Jc:J

L

BUSY

TEXT: 24 x 4 lines Graphics:

PRIN

crn::J

r:-

---------------

[IT[]

I

• : ~

L..:

_______

9

0

PC-250

7:1-t

C

APS

150 x 32 full dots

T

~

E=:J rr=:J

____________

-

DEF RUN

(5 x 7 dot matrix)

RE MO

r:n:::::::J

-,

[I:=:J

TE

________

1

:

I

ON/BRK

L __

___

E=i

0

P

RO

POWER

cra::::::J

..------

Ii~

__ J

I

MODE

:

G:J

BS :

~~r

:i

i

I

:

:J

o

Model: PC-2500

o Calculation range: 10 di

(exponential

o Ca

lculating

function)

o

Programming

o

CPU: Cmos 8-bit microprocessor o Syste o Me

m ROM:

mory System Data

only ar

Program/data

Reserve area: 79 bytes

o

Stacks Subroutine FOR-NEXT Functional Data

stack: 8 stages

o Fun

damental calcul

Calculations

Four math rules

part)

method: Formula

language: BASIC

72KB

capacity:

area: About

ea: 208

area: 3102

:

stack: 10 stages

stack: 5

stack: 16 stages

:

17 40 bytes

stages

ator fu

~--

l

D

EJ

D D

l

o DD DD DD DD

L----,

BiD

gits (mantessa part) + 2 digits

oriented (wi

bytes

nctions

:

EJ

L------------------------

I

CAP

~

D

I

th pri

orit

D

EJ

y

D

---------

EJ

Scientific

Trigonometric tions, logarithmic angle solute

Edit

ing fu

Vertical cursor control (~.

Insertion Deletion Backspace

Line scroll (t

Software

o Sharp business software o Table calculation o Graph creation: Bar graph, broken line graph,

o Telephone book

Memory

Battery backup

(The contents

r

etained during power

D

DD

D

CJ

- - ---

functions

conversions, power rising, valu nctions

:

band graph, circular graph

protection

LJ!B!D

~

I

:

functions, inverse tr

e, sign

:

, .).

)

:

of

LJ~D-trDja

0

1·-- '!o DD

r--

J

ENT

ER

functions, exponential

functions,

+--

program, data, and reserve areas are

off

. )

I

DD I EJ

I

li~DDEJ

t..: _____

___

__ - - - - _ _J

igonometric

roots, i

nteger, ab-

and pi

.

)

D

func-

functions

!

i

'

!

I

i

,

SHARP

CORPORATION

PC- 2500

-

Display

:

Liquid crystal display

1.

Text

display 5 x 7 dot Character size:

Character pi

dot

2. Gr

aphic display

150 x 32 full dots di Dot Dot pitch: 0.

Dot si ze:

Printer

:

Printer

type: X and Y axis

P

rint colors: 4 colors

(Op

tion: EA-850C

Charac

ter size: 15 kinds x 18mm Minimum pen Print speed: 7 char printing with Recording paper. Paper roll diameter and 114mm Pen

moving speed: 73mm/second

tions,

103mm/second

Serial 1/0

Transmission only

Baud Parity

Word si

Stop Connector: 15-pin

devic

e Output sig Interfacing signals:

Input Output Others

• Auto

•

Power

•

Power

source: 1

in use)

• Rec o Continuous di

posi

o Intermitte

for provided operation rest of the time (50 min without

o Printer in operation:

digits perature

functions

rate: 300,

check: Odd,

ze: 7 or 8 bits

bit: 1 or

nal level: CMOS level (4 ~ 6 volts)

RD, CS,

SD, RS, RR, ER

SG, FG, VC

power off: About 14.5 m

consumption: 6V

supply: Internal recharge

OOVAC, 50.60Hz, with

hargeable battery operating time:

tions (2 rows) under the temp

nt operation: The r

about 1.5

that cal is

operating the pri

of "5"

of 20°C with

matri

tch: 4.08(W) x 5.44(H) mm (si

space)

size: 0.63 square meter

)

moving di

standard

method: Asynchronous, half-duplex mod

600, 1200 bps

even, n

2 bit

s

connec

CD

splaying: Di

mont

hs,

culator operation or prog

done 10

are pri

nted continuously under the tem-

x display (24

3.35(W) x 4.71

splay

68mm (for both directions

plotting

of

blac

of 0.8mm x 1.2mm ~ 12

stanc

acte

rs/second, max

character

width.

for 45°

one

tor for connection with external

.. ... (DC

splaying

when operated one

min

utes

utes)

nter

.

About

450 digits, provided that 20

the character size

positions x 4 rows)

(H)

mm

s

)

k, blue,

e: 0.2mm

inutes

efreshed

out of one hour with th

green, r

ed

imum (for

si ze "b")

of less than

(Option:

direction

), 6W

able battery (charge

the AC

erature

EA-515P

for X and Y direc

adaptor EA-150

About

"5"

on 48 display

of 20°C.

battery wi

operated to display,

"b".

25mm

)

100 hours

ll last

hour per day

rammed

ngle

mm

o Graph print

described in Page 304 is print

o

Operating temperatur

o

Physical dimensions: 297(W) x 210(D) x 18 front)

o

Weight. About

o

Accessories: Tape recorder interfacing cable, AC adaptor

(EA-150).

red

).

ing: About

e: 5 to 40°

and 45.5 (depth in

1.3kg

write

pen (one each

paper

roll (one

roll), i

11

times,

ed conti

rear) mm

nstruction manual.

when t

nuous

ly.

C

of

black, blue, green, and

he gra

p

(depth in

RAM map

OOOO

H

8KB ROM

internal )

(CPU

2000

H

16 KB

R

AM

BASI

4000H

6000H

-

e

7000H

8

000H

FFFF

2.

I

I I

I

8KB

I

l

Card

I

I 1

card

I

I 8KB

I

I Car I

I

4KB

RAM

ROM

32

KB

ROM 1

INTER

C

PRETER

TEST

7000

RAM

7200H

image

740

76

RAM

d

7800H

7AOOH

7C

7EOOH 8

PROGR

H

DISP

1

-------

----

DI

SP

2

-------

D!SP 3

-----

DI

SP

-

---

--------

DI

SP

----

KEY

-------

KEY

32

ROM

Bund

led software

---

----

4

5

P

ORT

-----

P

ORT __

KB

-~~K_6_

ROM

2

0H ACK2

00H

OOH

~--- _

000H

AM

-

ACK

--

A

CK

ACK

--

ACK 5 1 2

1

3

4

--

Internally implemented memory test program

The

checksum test program ROM is

test the BKB CPU int

RO Ms.

ROM to be tes

CPU

internal ROM

(8KB

)

CPU enternal ROM1

,

e

(32KB)

CPU external RO

(32KB)

The ALL execution of the test program bec gram in each ROM are not assured test.

RESET switch

ted

M2

ernal

ROM and 32KB x 2 external

K

(RUM mode)

CALL&802AI

CALL&8027 I ENT

CA

LL&84F

has

ey ope

91 ENTER

to

contained

ration

ENTER

I

ER

I

be

depressed after

ause the

of

data a

its contents after

inte

O

K status

rnally to

11147

10127

38524

the

nd

pro-

the

-2-

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PC-2500

-

4. SIGNAL DESCRIPTIONS

4-1. CPU

Pin No. name

1 2 3

4

5 6 7

8

9 KON

1

0

11 1

2 HA

1

3

1

4 IA7

.j. .j.

20

21

22 IB7

23 IB6

24

25

26 IB3

2

7 IB2 Out RS throu

28

29 30 31 GND 32

.j.

47 H16 Out

(SC61860A14) p

S

igna

l

In/Ou

t

A

O

ut

R/W

CPAL

TEST

(/) (/J

RESET

XLN In

XOUT

DIS

IA8

1

O

Ou

t

Ou

t

In In

Out

In

O

ut

O

ut

O

ut

In/Out Ke

In/Out

-

IA1

I

IB5

IB4

VM VA

B8

IB1

H1

.j.

In/Out

In

Ou

t

Out

In I

n

I

n

Out

-

in

signal

D

escription

Add

ress bus, low during

W

rite

L

ow

order bit

As t

he

data

bus when a large capacity ROM

is

used,

8 bits

signal. Test pin,

Oscil

lator circuit input Oscillator ci Reset input. A

to

reset. Th

down to

I

nput from

(

EAR

ON/B

RK key in

down

Output to the data (MIC jack) and

LCD

dri

LCD driver clock. Low during

2KHz play is oper

y and RAM input. Low during generated when a key

Key

input/ during a key is de

Key

input/key during a key is depressed

Busy signal. Serial

printer control IC

Low battery

i

nput

circuit. Normally, high. CD through

request received when th s

tate and stopped when low.

CS

through th mission enable from the other end. Transmission

is

in a hi

low

.

RD through th

data.

RR through the SIO which is a receive ready signal fr r

eady

ready to receive.

reque

st from th data tran compl

ER

through the SIO. Go

exe

cution of the OPEN com LCD pow LCD power supply Power LCD

back p during displaying

LCD back plate si during displaying

(standby= power off)

clock, normally high

address la

address signal is

that

address

of 16 bits) is

normally

rcuit outp

high on this line causes

e signal

low level.

the data rec

jac

k)

to

low level.

ver Control

pul

se gen

erated when the dis-

ating

card s

key

strobe output. Low

standby.

pressed

strobe output.

standby. Pulse generated when

signal

from the low battery

the

from the

e SIO which is a trans is done when the sig

gh

state and

e SIO which is receive

om this sid

to rece

i\1¬

gh th

e SIO whi

is

smission and low

ete

.

er

supply

lat

e signal.

standby. 4-level pulse during

.

standby. 4-l

.

description

standby

tch signal.

carried

out th

signal (low

latched with

low

.

ut

is

normally pulled

put. Normally, pulled

recorder option

the

buzzer

signal

.

lot lock swit

standby.

is de

Pulse generated whe

.

busy signal from the (PCU).

([B)

SIO

which

other end. Data

e signal is

stopped wheri

and low when not

sid

e. High durin

gnal. High impedance

evel pulse during

order

thi

s

order

option

.

stand

ch

Pul

se

pressed

.

Low

which

is

an

detect

is a send

are

in a hig

h

nal

e. High when

ch

is

a sent

g

whe

n

es

high upon

mand

.

High impedance

e

by.

n

-

-4-

Signal

N

o.

name

4

8 VB

49

VDIS

50

VCC

51

voe

52

VGG

53

60

61

62

6

65

66

67 A14

.j.

80

0

.j.

3

4

.j.

DO

F05

F04

F03

F0

F01

B08

.j.

A1

In/Ou

t

Descript

ion (stan

In

LCD

power supply. High dur

s

tandby and VB when clo

In

LCD

pow

sta

ndb

y and low when clock stops.

In

L

CD pow

er supply.

Out

LCD pow

standby and low

In

Power supply. Normally, low lev

7

In/Out

Data bus impedance

dby =power off)

ck stop

er supply. High duri

Nor

mally, low

er supply. High

lin

e. Normally, high

.

duri

when clock

ing

ng

stops.

s.

.

el.

-

In/Ou

t

Data bus line. Norma impedance

Ou

t

32KB ROM1 A low on this

O

ut

SD transmit data. Low during standby (buffered with the 50H001

Out

Data. Trans

t

he PCU

2

Out

WAKE UP which

requ

which a high state of th

Out

Application ROM2 chip select enable

signal. A low on this line selects the

ROM2.

but

RAM,

Out

Addre

.

through the S

mission of serial data to

.

est signal.

DIS-LSI enable signal

ss

bus. High dur

-

Out

Address bus. High during

l ly, high

chip s

elect enable

line s

elects

IO which

is

a PCU start

The PCU wak

is signal

ing

signal.

the ROM1

is

a

).

es up

.

standby.

standby

.

4-2. Display chip (SC43537) description

G

ND

V

GG

DIS HA

-

- - ---

-)}

- ·

¢AL

(Latch clock)

0

1-8

~~---.

C

E

R/W

'

,

:CON

(/)

C/)

-

Q)

~

"O "O

<(

TROL

s:

u

:J

co

<j>- ~

':.

::'

64

(

80-B F)

M M

byte

-

64 byt

(40-?F

(

S62

(

S63

R

ead/Writ

ho; h 1:h 2:h

' '

e

)

(Display RAM)

) )

e

J:h ,:h I

'

64

byt

(

00-3F)

S62 S63

PC-2500

-

V

ors

V

A

V

B

S

1

S2

Q:;

>

~

e

0

c

)I

Q)

E

CJ) Q)

Cf)

O

ss1

QSs2

.

gN~~~~~~~~~~~~~~~~~~~

B

mmmmmmmmmmmm

SC

43537

DISP DRI

mwmmwmmm~mmm

VER

;~

~

The LCD

• Timing

GND

·VAH-

operates in 1 /

DIS

h5

SH26 :TR5

(

ESR.H:T

chart

l~' --~

R22

16 duty.

Display

)

f

VMH

-

I

Vsu..:I""

*

v"

f

80-pin

off

LC

RESET

.......

,.....;

/

5

:

r-«

ON

Display on

Power

off

(CPU at standby)

Retain the at

power off

conditions

.

-

- -l.4V

-

ov

-2.8V

V

VAL

-

t

VDI s %

5

VML

-

T

VDI

·V

VDIS

S

-

BL- I.

5-

I

Vn1

l

s

A

VM

VB

-5-

~

.__

-

NOTE: Voltage when

- -4.2V

..._ -5.

- -7.0V

VDIS

is 7 .OV.

6V

PC-2500

-

• Cou

HA

DI RES

hl (TRl

nter unit

S

)

and

segment

waveforms

h2 (TR2 h3(TR3) h4(TR4

h5(TR5)

GND=VAH

VMH

VBH -- ------~

V

DJ

S=VBL --

)

Segment output waveform

-

-- --

----

------------------

All digits of

f

Hl

-

ON ON ON

H2 H3 H4 H5 H6 H7 HS H9 H10

B

ack plate (H1) waveform

Seg

ment waveform

ONOFFOFFOF!FdFFOFFOFFON. ON ON ON ON ON ON ON OF

Hl1H12H13Hl4

H1 H2 H3 H4 H5

F

A

ll digits

O

n

O

ff

off ( DIS=

L)

h5 =

1

h5=0

VAL VBH VBL VAH VAL

VBH

-6-

PC-2500

-

4-3. Gate array (SC61J216F)

This

LSI

signal

decoder circuits

contains the

RAM,

ROM, and DI

and key strobe generating

SP

chip select circuit

.

------1

I

...

O

l

....

~

....

I

r

!

I

D

•

I

i

--{)

I

...

R/W

....

I

...

r

..

....

I

D2

D3,

I

Data latch

I

I I

CL

...

r

...

....

...

....

~

....

...

r

...

....

...

r

...

....

I I

I

I I

I

Address de

I

code

---

r

-

,___

I

I I

-

I

BOS

AS

A9 AlO All A12 A13 A14

}

.

FOl

F05

...

P

ACL

r-

I

...

,

REON

I

...

I

,

REOFF

I

...

O

UTl (CAPS LED

-

I

...

I

OUT2

(

...

7J

I

...

K

OS

....

I

...

K07

....

I

K06

I

...

K05

I

...

K0

4

.

I

...

K03

r

...

I

.

K

02

...

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.

I

I I

I

...

,

DISPl

...

I

DISP2

.

I

..

DISP

...

I

....

..

....

I

...

I

...

3 DISP4 DI

SP5

RAME,ROMEM,ROMEB

RAMl-6

I I

ROM2

...

I

...

I

R

OMl

...

I

7

LED)

:

)

for

Japan

HL

~

I

VGG

~

GNDH

L-

----

-

-------

-7-

-

-~

PC-2500

-

4-4. PCU (DLG3001

P

in

Sign

al

No.

n

1

2

3 D6

4

5 6 D9 7

D

8 Dl

D12

9

10 11

1

13

(

20 R52 2

22 GND 2 24 25 HLT In 2 27 28 29 30 R02 In

31

32 RlO Out

3

34 3

36 37 38 R20

D D14

2

D15

R40

R43 R50 R51

1

RST

3 OSCl In

OSC2

TEST

6

vcc

ROO ROl

R0

3

R11 In

R12 Out GND

5 R13

I

NTO

INTl

-

41 R23 Ou 42

R30 Out

- -

45 R33 4

6

R60

-

49

R63

ame

D

4 In

D5

D7

DB

lO

1

13

-

3

-

In/Out

In

I

n

I

n

-

Ou

t

-

I

n

Ou

t

-

Out Oscillator circuit out

-

Out GND

Out

In

Out

-

t

-

Out Out

-

Out

E)

pin signal description

D

escription

B

it size sel

(low: 7 CR code func

Low: Character kind select signal: Hi

(J5 to (J6

P

aper feed (PF) sign

feed, hig

NU NU N

U Halt enable NU NU Da

CPU.

Busy signal. Seri

CPU.

NU

ect

signal. High; 8-bi

-bit) tional

CR with LF (high: CR onl

be shorted

to be

shorted)

h:

pape

ta

signal. Serial

assignment

),

low: ASCII

al. Low: pape

r feed sto

sign

al (HALT ENABLE)

data input from

al busy signal to the

(

NU Reset pin.

signa state

GND Oscillator

GND GND

GND X/Y

High: 365 Character kind

High: CE515P (DLG3301 E character se

Output during power SIGNAL OUT

Input

SIGNAL

Carriage

Low: home position Strobe inp GND

}

Reset wi

l.

Normally,

.

circuit input

motor

pps

duri

ng power o

IN

position dete

ut

X motor s

Y

motor

Z

motor

th a high state

pulled down to a low

put

drive fre

quency se

(low: 325

select signal.

compatible

ignal

signal

t)

on

n

ct

switch signal

(left m

p

pps)

t

.

gh: JIS

lect

argin)

y)

P

in

Signal

No.

name

50 51

52 53

r

the

of

.

54

D Dl

D

NC

In/

Out

O

2

D

3

NU

-

Low

I

n

ba

ttery

high leve N U

-

Serial

I

n

High: serial interface i

nterface

-

N

U

/parallel interface sel

Descriptio

battery (LB) input

detect circuit. Normally

l.

).

n

(low:

from the low

,

ect

signal.

parallel

-8-

5. DE

SCRIPTION OF THE PRINTER

(4)

Power on

reset ti

ming (Fig.

1)

PC-2500

-

CONTROL CIRCUIT

8-bit seri printed.

(1) Ser

®

•m.c ""' ~

(2) PF switch sense

©PAP

NOTE:

al

ial interface

@BUS

One data le

®

@ One

Start

©

busy sign

@BUSY

ER FEED

Ready period

®

Busy period

The

(3) Halt

print data are

timing (Fig.1.)

Y

~ I__

bit

bit rising ed

Read timing

on/off state of the PF switch

in a bus

control sign

1°1

•

l•l•l•[•[

I

Sta

rt bi t

ngth

length 833 µse

qe

al rising edge

y period

-»

timing (Fig.1)

'-----1----

3msec 3msec

(3msec)

al

timing

received from the

®

O

J

''°':''''td

•i

@

"1" level

8.33msec c

11 Oµse

c

Paper feed

.

(Fig.1)

perio

is

CPU

to

----i__s-

1

~

d

checked once

be

Q) Rese

t

1!9

POWER ON TEST

IQ

POWER ON RESET

a. F/F

NOTE: At power on, the flipflop

(5) Al I clear

1. Pulse is

2. Pulse is

3. Hardware

_jt

~

L_

reset pulse

action

halt condition.

terminal With tion

noise.

width:

pulse from flipflop output power

ning of flipflop. Pulse added will

not operation ( F ig. added

as

at

power on

added

is

(G).

the

abo

even

if

_

Power on

on reset

the

be assumed as

to

reset by adding a pulse to

ve

there

®

---

J

f------

1msec

the C-R network. A low

performs all clear

output

all

clear operation to

to the

the all

1)

Q)

in

order to

.

(8)

for a

wake up by releasing

operation, it in

was an error in

-----

will be

is

sent out at the

RST pin thereafter

clear si

perform the same

sured all

the

program

--

reset with

state of the

operation. A

begin

reset

the

gna

l.

the

RST

clear opera-

due to

a

-

Th

is

wake up

@ Wake up

@ Halt

Halt

©

NOTE-1: Once it goes

NOTE-2: "

NOTE-3: A wai

disregard pe

reset

-»

start

wait period

wake up pulse will be disregard in

IOms.

TYP"

C-R

network. Condition

operate

completion data to

normally is

t time

receive

is

disregarded

riod

of

operation

into the halt

is

dependent

4msec, until it goes of

data

processing, with no more

.

required

into the halt state after

.

(NOTE-1) (NOTE-2) (NOTE-3)

state, arrival of

on

the factor

minimum.

this

period.

for the

20msec

10msec 120msec

of

LSI

a

the

to

-9-

Sharp pc-2500 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual