ly, divide, constant, percentage, add-on, discount, power raising, reciprocation, memory calculation, etc.
6VDC, lithium battery cells (CR2032 x 2)
0.03W Approx. 120 hours of continuous use (with
CE-212M) under normal conditions (based on 1 O tion or program execution and 50 minutes of display per hour at a temperature of 2o·c).
Life may vary depending on the operating conditions and the type of battery used.
o·cto4o·c 135(W) x 135(W) x 70.5(D) x 19.2(H)mm (closed) 1759 (batteries included)
minutes of arithmetic opera-
141
(D) x 9.6(H)mm (opened)
Model:
System diagram
CE-152 cassette tape recorder
CE-127R microcassette tape recorder
PC-1285
CE-126P printer and cassette
CE-124 cassette interface
interface
CE-140F pocket
disk drive
SHARP CORPORATION
CE-120P Printer with Cassette interface
PC-1285 pocket computer
This document has been published to be used for after sales service only. The
contents are subject to change without
notice.
,
..__I
_ ___.
eg DODOO
CJDCJD DODOO DODD DODOO
DODOO
•CJCJ ODDO
RAM card
CE-21
OM CE-211 M (4KB) CE-212M (8KB) CE-2H16M (16KB) CE-2H32M (32KB)
(2KB)
..
PC-1285
3. BATTERY LIFE AND CURRENT CONSUMPTION
PC-1285 power Lithium battery
supply CR-2032 x 2 pcs
Capacity
170mAH
Current consumption
Current consumption when PC-Current consumption when PC-(with display on)
The above values are at the room temperature of 2o·c and may vary depending on conditions.
(NOTE) Current shou
ld be measured wi
1285 OFF 1285 ON
th a RAM card loaded.
:
Terminal
voltage: 6.
45µA max.
450µA
max
0V
.
4. LOADING PROGRAM
A prog
ram
PC-12
85 in
eit
her of the following ways:
(1) Us
ing the
program stored RAM card
(2)
To load
progra
m from the cassette tap
the
followi
126P p
rin
ter/cassette interface or
ng opti
In this case,
G)
CE-face
created on the programma
® CE-1
52
ta
(3)
To load prlowing option is
CE-140F (pocket di
cassette tape recorder or CE-127R mic
pe
recorder
ogram from the 2.5"
required
.
sk drive)
(4) To load program directly from another pocket
case, the following cable EA-128C
NOTE:
Note the following when loading the RAM card wi
created or edi
(1)
(2) Erase reserve data by PC-
ted on the PC-
Set the PC-1280 in
1280
the
program. (Execute SETMEM "1" IENTERI .)
Do the following operation to erase
ISHIFTI IBASICI ...
[HJ~
&YI
IENTERI
Set
in
...
Erase reserve
ble
uni
t can be loaded
onto the
e or microcassette
on
G)
and® are
CE-1
requ
ired
24
cassette inter
.
rocassette
pocket disk. In
option is
required.
this case, t
comput
er.
th the program
.
MEM$="1" when creating or edi
1280 before
loading to PC-1285.
ting the
.
the reserve mode (RSV symbol on)
data
.
tape
he
fol
In this
.
-
-
5. MEMORY MAP
2800~-2AO Or-----_,
2COO
2EOO G.
3 0 0 O Low battery latch
3 2
3400
3600
38
00
3A
OO
3COO
3EOO
4000
0000
20
00
2800
4000
8000
A
OO
co
o
EOO
DISP I
DI SP
APOB
conversion
C
O O
Caution PON latch
write
CE
ROM bank CE
RAM bank address
Po
rt
write CE
Port wr
Memory map
Key stroke wr
CE
Internal ROM
BK
DI
SP
S
ystem ROM
16KBX8
BANK RO
------
0
-
-----
0
----
0
--
E
ite C
B
& port
2
E
ite
BANK
-
-
....,
I I
~
~-------
R
I
~~~~~~~
~---
L===
I I I I
-
Do~o PC-1470U/75 P
I
PC-1280 PC-1
285
P05
P06
P07
-
POB
POI P02 P03
:'..
P04
--+
D3 D2 DI 0 0 0
0 0 0 KS
I I I I
R7
OB
A13sentonPOB
DO
KS I
I
8
I KS!-KS8
-2-
,..
.
6. LOW BATTERY DETECT CIRCUIT
As the PC-PC-1280, this
(
Note that the parts location numbers do not always coi
those
A
s shown in the
IC, LBIC (MN1280) turns hithe detect VD.
For both signal level
IC, LBIC is turned on and off with gate array CAU
As FiCAU sidown below the
To r
ogated by
is
activated. After sensing the CAN level, the CAN line is set off (high impedance). When CAU is turned high as the voltage on pin 2 increases as there is no more resistance division. As LB is interrogated again, the level of STOP is
In
the standby mode, set high impedance. voltage drop between the standby and the STOP
abled.
(P-ch
1285 is pr
in the actual circuit di
voltage level VD, or turns to low when VIN drops below
(MN1280
g.3
shows, when the
gnal, the BATT symbol is set
chec
k the level of the signal CAU, the state of the
setting CAU low (active
level, bo
CPU FOi
open)'!--
GA CAU
(N-ch open)
2.0V
-
O<-
-~-~~-
OUT
(V)
Q
b..__L__~
Action of the vol
ovided with a low battery detect circuit like t
section describes about its functio
agram
.)
figure below, t
s of CAU and STOP are mon
),
the pin 2 input is divided by
level of the
F01 011
th the
---
------'
L_ _
tage dete
[Fi
g.2]
he
output from the low
gh when the input voltage VIN ri
supply voltage goes below the level of the
signal STOP, the symbol is turned
). If LB is at a low level, the sy
off, the output changes from low to
of the CPU and CAU of the gate array are is employed to compensate for a battery
ON/BRK key and the
DI!
~
RI
R2
---t--+
-'P
___L_.,
_
ct
IC
n.
.
active. When it goes further
operating. Upon detection of
RESET switch are
~
Cl)
Ol
~
-+
;:, Symbol ON
a.
Cl.
L__ _
::J
(J)
itored by a single
R1
_
--
--
ncide with
batte
ry det
ses above
and R2,
CAU
and R2
off
line LB is inter
sensed
[Fig.1]
signal level STOPsignal
[Fig.3]
.
mbo
.
dis
le
he
ect
vel
7. LSI SIGNAL DESCRIPTION
7-1. CPU (SC61860A38)
Pin Signal No
.
name 1 2 3
4
5 6 7 RES
A01
Rfiii
cp
T
cp1 cpo
AL
ES
In/O
ut
Description (Standby-power off)
Out
Address bus AO, high duri
Out
Write clock, normally hi
Out
Address latch. Clock used to latct
he address of the LCD drive
I
n
Test pin, normally low
In
Oscillator input
Out Oscillator output
I
n
Reset
input, reset with a high
of si
gnal.
ng standby
gh
h
r.
state
PC-12
85
-
8 9
10 XOUT Out
11
1114
20
21 22 IB7
- l
-
23 IB6 24
25
26
27
28
29 30 31 32
45
46,47
48 VB
49
50
51
52 53
60
662 666
66
7
7
80
XIN
XON In
DIS
2 3
I
I
HA IA8 IA7
I
IA1
IB8
I
B5
I
B4
183
I
B2
IB1
V
M
V
GND
H
I
H14 Out
H15
,H16
VDIS
vcc voe
V
GG
08
I
1
3 4 F02 5
I I
3
4
I
I
0
F0F04 F
03
F01
B08
B0
A08
A02
A
1
1
I
I
n
Cassette signal input ON/BRK key
down low. Cassette signal a
output L
Out
OuIn/In/Out
In/Out Key input/key strobe, low duri
-
-
-
O
-
Ou
In/
In/O
5
Out
Ou
O
-
O
Ou
1
Out
O
Out
CD dri
displaying
t LCD driv
Out
Key
input/key strobe
Key
input/key st
standby
I
In
I
n
In
In
In
In LCD drive poweIn LCD drive power I
n
ut LCD backplate signal, 4-level pulse
I
In
In
I
n
t LCD drive
In
Out
I
ut
t
ut
ut
t
I
ut
I
I
standby Not used Not used Not used 11
pin ACK
i
nterface)
t t-
pin DIN (data input on t t-pin
i
nterface
t t-
pin DOUT (data
interfacet t-
pin 102 (data input on t t-pin
interface) t t-pln 101 (d
interface)
(+)supply
during di
I
LCD during displaying (1/
Not used (because of 1 /14 duty) LCD dri
standby LCD drive
standby LCD dri
standby
standby (-)s
upply
Data bus 07, i
mpedance
I
Dat
a bus DO, normally high
im
pedance
Ga
te arr
R
OM ch
R
AM card bank selNot useLo
w battery det
duri
ng st
Addrestan
dby
I
Address bus A 15, standby
Address bus A 15, standby
Address bus A1, high during standby
input, normally pull
ver
control signa
er
sync cloc
(acknowled
)
)
ata input on 11-
splaying
backplate
ve power, hi
power, high during
ve power, high during
power, hi
normally hi
ay chip enable (CF)
ip
enable
d
andby
ss
bus A 15, high
I
ed
nd
buzzer si
k
robe, low duri
inpu
r
(1 /14 duty)
signal, 4-level pulse
14 duty)
gh during
gh
ect (BA
ect, high impedanc
high
high during
gna
l,
high durin
ng
ng
ge on 11
t on t t-pin
pin
durin
g
gh
)
durin
g
during
l
pin
g
e
-3
-
~
PC-1285
7
-2. Gate array (LZ92K41)
Pin
Signa
l
I
C
LB
1
I I
A9
I
In/Out
In
Bank selec
I
n
Chip enable
In
Data bus
I
In
D
In
(-)supply
Out
11-pin
Out
11-pin 102
Out
11-pin DOUT (P-channel open output)
Out
11-pin DIN (P-
Out
11-pin BUSY (P-output)
-
Not used
Out
Not used
Out
Not used
Out
System ROM A 14 and RAM A
Out
System ROM A 15 and RAM A 12
Out
System ROM A16 and RAM A13
Out
RAM card slot A1RAM card A16
O
ut RAM card sl
Internal RAM chip
Out DISPCHIP1 chip enable
DISPCHIP2 chip enable Reset output to
normally low
O
ut
ON/BRK output to CPU KON line, n
orma
In
Low battery detec
I
n
Reset
In
ON/BRK kdown
In
(
+)supply
(-)supply
voltage after acti
Out Key strobe (P-channel open
In
Write clock
In
Address bu
I
A
No
.
n
ame
1 2 3
I
6
(
7 8 9
10
11 1
2
13 14 15 16 17 18 19 20 2
1 22 23 24 25
26 KON
27 28 RES1 29 BRK
30 3
1 32
33
I
40 41 42
I
48 A15 In
BA CE
DCO
D03
GND
P01 P02 P03
P04 P05
N
SLTB
AS3B
AS1 AS2
AS3 AF15 AF16 Out SLT1 SLT2 Out DSP1 DSP2 Out
RESO Out
Voo
GND In
CAU Out Low battery symbol
KS
KS8 Out Key strobe (P-channel open R/W
D
escription
t
I
ata bus
101
(P-channel open output) (P-channel open output)
channel open output)
channel open
5
ot chip
ena
enable
CPU RESET line
lly low
t, low at low
input, normally pulled down
ey input, normally pulled
detect line, high impedance
vation of
I
s
I
ddress bus
activating
symbo
ble
l.
11
,
batte
outpu
output
8. SERVICE PRECAUTIONS
Each
cabinet is
D
isplay
Display side top cabinet: CAB-B Keyboard side bottom cabineKeyboard side top cabin
C
8-1.Removal and installati
Hints to
calle
d as
follows
:
side bottom cab
AB-D
latch CAB-A
®
/~=::::::::::::::=::::::::::::::~~
~==~~~~~
inet: CAB-
et: CAB-D
A
t: CAB-C
with CAB-B
on
of CAB-A
CAB-A
=~~
CAB-
A
I
C
g.2]
AB-B
Fig.
Fig.1 ®
Latch
B
1
G)
[Fig.1]
ry
t)
)
1. Engage the lat
2. Engage the latch
3. Engage the latch C, Fig.2,
How
to
remove CAB-A
ch A,
B,
[Fi
Fig.2, as shown in Fig.2.
as shown in
1. As shown in the figure tween CAB-A and arrow direction to disengage the latch C at two locations
-
4-
above, i
nsert your na
CAB-C near the hinge and push it down in
il in the clearance be-
(Fig.2
the
).
2. Do the reverse sequence to remove the latches. CAUTI
ON: When removing CAB-A, be careful not to separate the
static tape.
8-2.
Installing
*
Make sure that the pin is properly engaged in
*
When latching arr
owhead A to achieve firm engagement. Use
tight
en the
CAB-C wi
screws
CAB-C
th CAB-D, push CAB-C
.
the hole.
all the way in the
the special
..
PC-1285
Mask sheet
tool to
l
t
Latch
~[
//
~
*
The pin must be properly and firmly eng
8-3.
Installi
knob
*
For the contact i
nstalled on the location as in the
ng the c
is
secured on the knob at two locations, it has to be
Q;Y'
Knob
[
I
/,?(ke
yboard
{(
/
ontact
~J
PinonCAB-
c
abi
H
ole in
(key
board side
to the LOCK switch
figure
D
si
net)
CAB-C
aged in the hole.
.
(?1 ll
Contact
de top
bottom cabinet)
CAB-c
Latc
Lower half keyshe
CAB-D (keyboard side top cab
(Fig.
h
FPC
(5) Insta
NOTE: Do not install the memory PWB on
(
(7) Posi
NOTE:
ll
the
memory PWB unit, Fig.2, over the keysheet and insert
t
he FPC
terminal onto the gui
6) Install the mask cabine
t,
after which fol
guide pin
secure it with
(Fig.3.)
tion the sealing angle t
four sc
Tighten the two in
sheet, then the
1)
(Fig.2)
de pin
s on CAB-B.
to the gu
d back the ear of the FPC to fit it on the
rews
ner screws first, th
fixing rubber on the face of the
o the guide pins on CAB-B and
.
en two other
inet)
ide pins
yet.
screws
et
.
8-4. Insta
(1) Assemble the mas(2)
(3) Ins(4)
NOTE: At this point, the lower half of the key sheet should not yet be
lling PWB, keysheet, etc
k sheet, th
Insert the rubkey sholding
ert the key spacer by
Fold back the t
he guide pi
on the guide pins or holding pins, and the fold line should be left
ber key in CAB-D, t
hee
t.
Position the shee
pins.
lower
ns on
loose
.
CAB-B.
en the main
hen
t onto the gui
positioning it to the guide pins.
half of the key sheet and fit the terminal onto
install the
.
PWB onto CAB-B
upp
de pin
er half o
s and key sheet
.
f the
-5-
/
(Fig.3)
G
uide pin
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