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NSB1706DMW5T1G
Dual Bias Resistor
Transistor
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The Bias Resistor Transistor (BRT) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSB1706DMW5T1G,
two BRT devices are housed in the SC−88A package which is ideal for
low power surface mount applications where board space is at a
premium.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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(5) (4)
Q1Q1 Q2
R2 R2
R1
R1
(3)(2)(1)
MAXIMUM RATINGS
(TA = 25°C unless otherwise noted, common for Q1 and Q2)
Rating Symbol Value Unit
Collector-Base Voltage V
Collector-Emitter Voltage V
Collector Current I
CBO
CEO
C
50 Vdc
50 Vdc
100 mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance, Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Lead
Junction and Storage Temperature TJ, T
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 x 1.0 inch Pad.
Symbol Max Unit
P
187 (Note 1)
D
256 (Note 2)
1.5 (Note 1)
2.0 (Note 2)
R
Symbol Max Unit
R
R
670 (Note 1)
q
JA
490 (Note 2)
P
250 (Note 1)
D
385 (Note 2)
2.0 (Note 1)
3.0 (Note 2)
493 (Note 1)
q
JA
325 (Note 2)
188 (Note 1)
q
JL
208 (Note 2)
−55 to +150 °C
stg
mW
mW/°C
°C/W
mW
mW/°C
°C/W
°C/W
1
SC−88A
CASE 419A
STYLE 1
MARKING DIAGRAM
U6 M G
G
1
U6 = Device Marking
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
NSB1706DMW5T1G SC−88A
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3000 /
Tape & Reel
†
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 4
1 Publication Order Number:
NSB1706DMW5T1/D
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NSB1706DMW5T1G
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted, common for Q1 and Q2)
A
Characteristic Symbol Min Ty p Max Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(V
= 50 V, IE = 0)
CB
Collector-Emitter Cutoff Current
(VCE = 50 V, IB = 0)
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC = 0)
Collector-Base Breakdown Voltage
(IC = 10 mA, IE = 0)
Collector-Emitter Breakdown Voltage (Note 3)
(IC = 2.0 mA, IB = 0)
I
CBO
I
CEO
I
EBO
V
(BR)CBO
V
(BR)CEO
− − 100 nAdc
− − 500 nAdc
− − 0.18 mAdc
50 − − Vdc
50 − − Vdc
ON CHARACTERISTICS (Note 3)
DC Current Gain
(VCE = 10 V, IC = 5.0 mA)
Collector-Emitter Saturation Voltage
(IC = 10 mA, IB = 1 mA)
Output Voltage (on)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
Output Voltage (off)
(VCC = 5.0 V, VB = 0.25 V, RL = 1.0 kW)
h
V
CE(sat)
V
V
FE
OL
OH
80 200 −
− − 0.25 Vdc
− − 0.2
4.9 − − Vdc
Input Resistor R1 3.3 4.7 6.1
Resistor Ratio R1/R2 0.055 0.1 0.185
NOTE: New resistor combinations. Updated curves to follow in subsequent data sheets.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%.
Vdc
kW
300
250
200
150
100
, POWER DISSIPATION (mW)
50
D
P
0
−50 0 50 100 150
R
q
JA
= 833°C/W
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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NSB1706DMW5T1G
l
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
G
45
D 5 PL
−B−
MM
B0.2 (0.008)
S
12 3
N
J
C
H
K
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
INCHES
DIMAMIN MAX MIN MAX
B 1.15 1.350.045 0.053
C 0.80 1.100.031 0.043
D 0.10 0.300.004 0.012
G 0.65 BSC0.026 BSC
H --- 0.10---0.004
J 0.10 0.250.004 0.010
K 0.10 0.300.004 0.012
N 0.20 REF0.008 REF
S 2.00 2.200.079 0.087
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
MILLIMETERS
1.80 2.200.071 0.087
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
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NSB1706DMW5T1/D
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