SHARP LZ9GF16 Technical data

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1 To : ED1

SPECIFICATIONS.

ISPEC No.

ISSUE:

Sep. 2 1999

Product Type

Model No.

-X This specifications contains 22 pages including the cover and appendix.

If you have any objections, please contact us before issuing purchasing order.

CUSTOMERS ACCEPTANCE
DATE :

BY:

__-__---

_- --.-

LZ 9 G Series 1 6 0 0 Gates Gate Array

LZ9GFl6

PRESENTED

Dept.General Manager

REVIEWED BY:

Engineering Dept. 2
Display Device
System LSI Development Center

Integrated Circuits Group

SHARi CORPORATION -

PREPARED BY:

SHARP

LZ9GF16

@Handle this document carefully for it contains material protected by international copyright law.

Any reproduction, full or in part, of this material is prohibited without the express written

permission of the company.

@When using the products covered herein, please observe the conditions written herein and the precautions

outlined in the following paragraphs. In no event shall the company be liable for any damages
resulting from failure to strictly adhere to these conditions and precautions.

( 1 ) The products covered herein are designed and manufactured for the following application areas.

When using the products covered herein for the equipment listed in Paragraph (2 1, even for

the following application areas, be sure to observe the precautions given in Paragraph ( 2 ).

Never use the products for the equipment listed in Paragraph ( 3 ).
*Office electronics
. Instrumentation and measuring equipment

l

Machine tools

* Audiovisual equipment

l

Home appliances

* Communication equipment other than for trunk lines

( 2 > Those contemplating using the products covered herein for the following equipment which demands

high reliability, should first contact a sales representative of the company and then accept
responsibility for incorporating into the design fail-safe operation, redundancy, and other

appropriate measures for ensuring reliability and safety of the equipment and the overall system.
. Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
. Mainframe computers
. Traffic control systems
. Gas leak detectors and automatic cutoff devices
0 Rescue and security equipment

0 Other safety devices and safety equipment, etc.

( 3 ) Do not use the products covered herein for the following equipment which demands extremely

high performance in terms of functionality, reliability, or accuracy.

*Aerospace equipment
* Communications equipment for trunk lines
. ControI equipment for the nuclear power industry

*Medical equipment related to life support, etc.

( 4 )Please direct all queries and comments regarding the interpretation of the above three Paragraphs

to a sales representative of the company.

l Please direct all queries regarding the products covered herein to a sales representative of the

company.

LZ9GFi6

1

CONTENTS

1. Introduction

2. Feature

3. Pin Assignments

4. Explanation of Input / Output signal

5. Absolute Maximum Ratings

6. Electrical Specifications

7. Condition for signal circuit

8. Illustration of control circuit

9. Input / Output signal timing chart for above cases

10. OutIine dimension

Page

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1. Introduction
This data sheet is to introduce the specification of LZ9GF16,

timing control IC for TFT-LCD module.

The functions and the uses

Timing control IC for 5” size and 5.6” size TFTlLCD module

Horizontal frequency driver(NTSC:600 divided frequency /PAL:604 divided frequency) and
phase comparator circuit for the PLL circuit are built in.

By adding voltage Controlled Oscillator(VC0) and Low Pass Filter(LPF) to this IC to make the

PLL circuit, following signals synchronized with input composite sync.

Signal(SYN1) and vertical sync. Signal(VIN) conforming to NTSC or PAL are generated.

1) Driving signal for source driver

2) Control signal for source driver

3) Driving signal for gate driver

4) Control signal for gate driver

5) Control signal for gate driver power supply making

6) Polarity alternating signal for common electrode driving signal

: CLD, SPD
: CTR, DIS
: CLS, SPS
: LOW0

: GPS
: FBPT

7) Polarity alternating signal for video signal

: FRPV

8) Control signal for the backlight PWM brightness control

: CHK

Illustration of control circuit
Input/Output signal timing chart for above cases

2. Feature
Process

: CMOS

Wafer substrate

: P-type silicon substrate

Package

(pin & type)

: 48QFP (0.75mm pin pitch)

(material) : Plastics
Operating Temperature : -30°C - +85”C
Propagation delay time

: 0. Snslgate

(Condition

: Z-input NAND, Fanout=X, wire length=2mm,

supply voltage=5V, Operating temperature Topr=25”C)

*REMARK

Not designed or rated as radiation hardened.
You cannot rewrite the program.

: See fig. l-a - l-c
: See fig. 2-a - 2-j

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LZ9GF16

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3. Pin Assignment

ICU
ICS

01M
02M
ORZ
ORZx2

TOlM

IOCUBM
IOCURZ

: Input buffer CMOS level with PULL UP resistance R=250k8
: Schmitt-trigger Input buffer CMOS level

: Output buffer I,=O.BmA
: Output buffer 1,,=1.61nA
: Slew rate controlled Output buffer

I,,=BOfiA

: Slew rate controlled Output buffer 1~,=16OflA .

* ORZx2 buffer is connected two ORZ buffer in parallel.

: Tri-state Output buffer 1,,,=0.8mA
: Bidirecional buffer CMOS level with PULL UP resistance R=250kQ, 1,~=1.6mA

: Slew rate controlled Bidirecional buffer CMOS level

with PULL UP resistance R=250kQ, IoL=80pA
OSCB
osco

hD

GND

: Oscillator Bidirecional buffer with oscillation stop control

10,=3. 2mA

: Oscillator Output buffer Io,=l.6mA
: Power supply pin

: Earth pin

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LZ9GF16

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1

4. Explanation of Input / Output signal

?IN No.’

1 I

Signal Name

VIN Vertical sync. Signal input (Positive)

Explanation I/O

.

2 CVOP Vertical sync. Signal Output for Count Down circuit
3 CVIN Vertical sync. Signal input for Count Down circuit
4 DVOP Vertical sync. Signal output for digital separator circuit (Positive) 0

5

FBJT Polarity alternating signal output for common electrode driving signal 0
6 GPS Logic pals output for gate driver power supply making 0
7

a

GND

Ground

EXCL Input / Output for outside Clock signal
9 SYNI Composite sync. signal input

10 HSY Internal horizontal sync. signal output (Negative)
11 VSY Internal vertical sync. signal output (Negative)
12 DIS Control signal output for source driver
13

TEST0

Monitor signal output for test

14 NTPC Terminal for display mode change NTSC or PAL [Note11 I
15
16
17

ia

VRVC Input for the Vertical scanning direction setting (Note21
HRVC Input for the horizontal scanning direction setting (Note31

CHK Output for signal of backlight brightness control 0

TEST1

Input terminal for test (Note41

19 TEST0 Monitor signal output for test

20
21
22
23
24
25

26
27
28 ,

29 I

30 j

31 / GND I Ground

32 I

-__

33

---__

34

.__ -.- -

35 I
36 :

-~---

37 ’

_____.____~ __ ._~ ~..... ._ ~. .- __ ..-. ~-____-__

38

39 ; TEST1

_---

40 F---

.-.- ~~ A&y-:--.

41 ,Horlzontal scanning setting output for source driver

_-.------e-.---. --- -__--___

42 ~

IVB Scanning setting input for gate driver

_--

SPS Besetting signal output for gate driver
CLS

Clock signal output for gate driver

.__.

LOW0 Control signal output for gate driver 0

CT& Control signal output for source driver

--__

_____-

SPD Starting signal output for source driver
CLD Clock signal output for source driver

osco

osc I Input for clock oscillator circuit
SAM0 Control signal output for source driver

~----t---------.~... --.. ~__

bD

TEST1

7---./Input-f;;-ini fil ye;;7-;j-ga1

LOW1

--F-~~--~-‘--.-..-

__--_- _.-

Output for clock oscillator circuit

_---_ .---

..___- --._- . .._--.- ___­IPower supply voltage

_ ._ ..-. -~- -- -..__--__ ~-______

f--------;. _- ---- --

IInput terminal for test(Note41

-

~~~--~

-____

-__

-__-

IPoIarlty alternating<ign&%$ut for video signa

RESH TGi%t!l-counter resetting input (Note51

PDP 1 o-

IOutput for_phasecomparative signal of PLL circuit

--.--

RESV /Vertical counter resetting input (Note61

TEST1 Input terminal for test (Note41

-I-

__-.._ . ~.---- ____---

IInput terminal for test (Note41

___. -_- .-. --.-__-__ -_.~

iHorizontal scanning setting output for source driver

- -.-.

_-__--~-~

-__

-------------,~ -

--j--‘-t

--

___-

CLOC

Input for EXCL si&l-outpu%etting (Note71

____

1-- --

--i--t-

VSY signal input / output setting (Note81

I

0

I

I/O

I

I/O
I/O

0
0

I
I

I
0
0
0
0

0

/ 0
/ I

_.-

-L--I .-

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(Note11

(Note21

[Note31

(Note41

(Note51

[Note61

(Note71

(Note81

(Note91

NTPH=H
NTPC=L

VRVC=H

VRVC=L

HRVC=H
HRVC=L

Normal state : H level
BESH=H

RESH=L

RESV=H
RESV=L : forcible reset

CLOC=H : L level output
CLOC=L

CLKC=H
CLKC=L

SAMC=H : It is the independent data-sampling timing at RGB
SAMC=L

: NTSC nethod
: MBK-PAL method

: Normally (Positive scanning)
: Reversal (Negative scanning)

: Normally (Positive scanning)
: Reversal (Negative scanning)

(Refer : 9, Scanning direction setting)

: Normally
: forcible reset

: Normally

: H level output
: EXCL, HSY, VSY terminals become output mode

: EXCL, HSY, VSY terminals become input mode

: It is the simultaneous data-sampling timing at RGB dots

(Note101

Horizontal display position is changed by delay time

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5. Absolute Maximum Ratings

Parameter Symbo 1

Supply voltage

VDD

InDut V"'+a-

V,

Rating Unit

-0.3~t6.0 V

-0.3~vnrl+0.3

V

Output vo 1 tage

I “0 I

IOerating temperature 1 Topr 1
ptorage temperature 1 Tstg 1

-u..J-

VDDTU.

J

-3o--+85
“C -55-t150

6. Electrical

Specification

6-l

Operating conditions

Parameter Symbol min typ max

Unit

Supply voltage

VII0

4.5 5.0 5.5 v

Operating temperature Topt -30 -

t85 “C

[Note] Input/Output terminal of TESTI, TEST0 should be used under

Signal Name

I/O

Used condition

TEST1 I

Fixed H level

TEST0 0

Connected GND by O.l,v capacitor

Parameter

I Svmbl

the

lowing conditions.

fi-2 Electrical characteristics

IOutput “Low” voltage

IOutput “High” voltage j

I Output “Low” voltage !

n--.r --

jOutput

__.----

High voltage

Output”Low” voltage /

lOutput “High” voltage --

VOM

IOutput “Low” voltage /
bms--;;i tagyi--

Jutput “Low” voltage I

~_- ---.

#l:

Applied to input pins (ICU) and Bidirecional pins (OSCB, IOCUZM, IOCURZ)

input mode

Applied to input pins (ICS)
Applied to input pins (ICS) and Ridirecional pin (OSCB) input mode
Applied to input pins (ICUJ and Bidirecional pins

(IOCU2M, IOCURZ) input mode

Applied to output pin (OSCO)

(OSCO : under the condition the input level of OSCB (input mode) = VDD or OV 1

Applied to output pin (02M) and Bidirecional pin (IOCUZM) output mode
Applied to output pins (OlM, TOlM)

Applied to output pins (ORZ) and Bidirecional pins (IOCURZ) output mode
Applied to output pins (ORZx2)

Applied to Bidirecional pin (OSCB) output mode
Applied to output pin (TOtM)

SHARP

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7. Condition for signal input
7-l In case of using PLL circuit (CLKC=H)

Clock input : OSCI

Parameter

Input frequency

Duty ratio

­Symbo 1

min

UP

max

unit

remarks

l/To

9.4 MHZ

TOL~M

40160 so/50 60140

%

Composite (Horizontal) sync. signal (Positive) : SW1

Input condition

Base on NTSC(M) system

Base

on PUB, 3) system

remarks

NTPC=H
NTPC=L

fsm125a ~MZ

NTPC=H

f &304

kIi!?l

NTPC=L

600

PS

I

16

58

PS

(Note1 1

Timing of VIN input to be specified. (See fig. 2-h)
fsyn=SYNI (composite sync. signal) input frequency (unit : kHz)

(Note31 In case of no VIN input, vertical counter inside of IC is reset

automatically based on f&284 (NTPC=H), fsun/344 (NTPC=L).

(Note41

After VSY falling, VIN input is invalid during the period of

192H(NTPC=H), 227H(NTPC=L). (lH=l/ fm)

However, the case of VSY falling by automatic reset is exceptional.

Input LOWI, RESH and RESV
Input VDI, through and integration circuit(Contro1 circuitry example : refernces)

with following value(z ,),
or please input the Low level after

V

DD turning on by this period system reset.

--___ _____

jSymbol---

min

tYP

T”

20

---~~--~.ioo~ ,

aax----

Unit 1

i

ms _J

’ SHARP

LZ9GF16

7-2 In case of input outside sync. signal (CLKC=L)

3) Vertical sync. signal (Negative) : VSY
Parameter

Symbol

min

Input frequency

fv1

50

Pulse width

TV1

1

4) Input signal timing
Parameter

Symbol

EXCL-HSY

Data

setup time

hll

Data hold time hOI

VP

max

f&Z62

h/258

3 5

min typ max

Unit

25

ns

25

ns

Unit

Hz

H

remarks

(Note51

remarks

HSY -VSY

Data setup time

Data hold time

hz
GIOZ

1.0

1.0

(Note61

(Note51 In case of outside sync. signal input mode, it show EXCL and HSY timing.

In this case HSY input signal is brought at the rising timing of EXCL input signal.

(Note61 In case of outside sync. signal input mode, it show HSY and VSY timing.

In this case VSY input signal is brought at the rising timing of HSY input signal.

I I I

I I 1

I

r

I I

I

I I I

I I I II II

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1

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r

I

I

I

I

I I I

1

HSY

SPD

CLD

,

QPS

CTR

CLS

FRPT

FRPV

9. Input / Output signal timing chart for above

cases

OCR

SOO(O)CK : NTPC = H (NTSC mode)

604(O)CK : NTPC = H (PAL mode)

I(NTSC)

I

-O.WAL)

1

O(NTSC) 1

603.6(I’AL) 1

1045(SAMC=ll)

\ I,

08 (SAMC=I )

-0.6; II2 2

-0.6 1

f

!

!

-----~,.-.-~ .-.......” ~-..._......_.-......_.~......~...~: . . ..~-..“‘\

72

‘5

5

j

i

I

i .,...._ .._ . ..- . ...” ..-....

-0.6 i

..- _ ._..._ - ..__......_...___........-... ---.--.------.-.-----.---i- -._--. _-^

106 -0.6 !

!

$

i

1

I B

i
(

i

I

---.---.f- ---.-..-..... _-- -... _

66 : 66

-_

//

!

\

I

..l-_l_

!

\ ..-... . .

I

.._ -............ _ .._........._..........__.........~ - ..__......” .-..... _ ..__._.__._. - .._.__._.._. - _...._..-._ - _._..__. i.-_... _ .._________.._

i

SO

,.- .._.--.._.-........ I _...._.__..........._. _ .._._..

i

------

.._ I ..-..-....,

i

\

!

..--...... _ -...... _._ -..._.. .._._.._..._ - . ..__.-.......- . ..-...........--...-..-....-..

i

_.-_--..-- .-_._ I_.-_ _ ___-_,__.__._._._,___

BLKO

DIS

6(NTSC) i

I(I’AL) 1

63

(’ ’ 63

I

I

!
I

i

/

Fig.?,-a Horizontal counter timing chart- 1 ( In case of using PLL circuit)

HSY

SPD

CLD

GPS

CTR

CIS

FRPT

FRPV

DIS

OCK

1200(O)CK

(5

1199

I

\I

I
i

78 174

/

72

‘;

//

I
I

1

III

g

201

>

,

i

I20

!

.-.--_, * . ...__,___..,_. _-__ .._ I: .._._.._............. .._.

\$

i

>(

!

i

I

. ,. . _ 5 -... .._ ..-....__.-_. .- _........r. _ .._... ..- _. .-._ - .._ - _..___........_...._ _ _....... -__-._-.___ .__. I ..__II__. fws

---_-

192

/ 6

1168

1
!

I
i

8’2

_ -_____.

82

1-”

__._._ -- _.._. ._ . .._ _ _ . . . . . . .

//

i

\

!

! \

I

*. . . _.

I

,.. .._.... - ..__..........I..~......_._-......~.....-.......,. - ..__ - .__. -._- ..,......____,__., I -_______.__._-

I

I28

I

-._.----_..-.. ,. ._,. - .._.._... _....-.._..._...... -_. .._

$

!

!

1.

I

I

i ..-..........-. _ .

z

.._.... i .._.....^._. _.._ .~....-...._.__...._._.....~~.......,..~__._... _ .._...._.._.. ._._.__.__.__....___.” _,_,_

I---

-----_-

i

74 166

i

74

i
1

I

i

I

I

5 i

I i

I
i

I

i

i
I

Fig.2-b Horizontal counter timing chart-2

( In case of input outside sync. signal akd SAMC = “H ” )

SHARP .

LZ9GF16

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LZ9GF16 ’

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VSY

626H (NTPC = H)

------- - -._­G26H (NTPC = L)

CHK

‘(NTPC=H)

CHK
(NTPC=L)

VSY

HSY

CHK

u

/

106H 2

----

1 1

8911

./

._~_ ‘.

626Hm-TPC = II)

-__-.- --.--..-.._--____ _________

.

G26H (NTPC = L)

,

Expansion of time axis

1’

-

I I

nH

--.-.. __--__----.-- -...--._ -_.-.~-._-

I

III I

L

/

uuJHluuuuuuhl

U u u

106H (NTPC = H)

nH

89H (NTPC = L)

Period of invecter okcillate

u u u u u Ill

----A-

eriod of invert& not oaciIIate

Fig.2-f Output signal timing of CHK (Control signal for the backlight PWM brightness control)

VSY

LOW1

‘LOW0

Fig.2-g Output signal timing of LOW0

HSY

VIN

HSY

SYNI

PDP

r

‘r

Pig.2-h Input signal timing of VIN (Using separated circuit of vertical sync. signal)

I

I I I .

I

I

I

I I I I I

II2 (fligh-impedance state )

Fig.24 Output signal timing of PDP

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10. Outline dimension

p-o.mTYP. 48-0.33kO.l

SEE DETAI

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DRAWING NO. i AA873 UNIT ! mm