SHARP LZ23J3V Technical data

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

1

DESCRIPTION

The LZ23J3V is a 1/2.7-type (6.72 mm) solid-state
image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 1 310 000 pixels (1 344 horizontal x
971 vertical), the sensor provides a stable high­resolution color image.

FEATURES

• Optical size : 6.72 mm (aspect ratio 4 : 3)

• Interline scan format

• Square pixel

• Number of effective pixels : 1 292 (H) x 966 (V)

• Number of optical black pixels
– Horizontal : 3 front and 49 rear
– Vertical : 3 front and 2 rear

• Number of dummy bits
– Horizontal : 28
– Vertical : 2

• Pixel pitch : 4.2 µm (H) x 4.2 µm (V)

• R, G, and B primary color mosaic filters

• Supports monitoring mode

• Low fixed-pattern noise and lag

• No burn-in and no image distortion

• Blooming suppression structure

• Built-in output amplifier

• Built-in overflow drain voltage circuit and reset
gate voltage circuit

• Variable electronic shutter

• Package :
16-pin shrink-pitch WDIP [Plastic]
(WDIP016-P-0500C)
Row space : 12.70 mm

PIN CONNECTIONS

PRECAUTIONS

• The exit pupil position of lens should be 15 to 50
mm from the top surface of the CCD.

• Refer to "PRECAUTIONS FOR CCD AREA

SENSORS" for details.

LZ23J3V

1/2.7-type Interline Color CCD Area

Sensor with 1 310 k Pixels

LZ23J3V

1OD

2GND

3OFD

4PW

5Ø

RS

6NC

7Ø

H1

8

16

15

14

13

12

11

10

9Ø

H2

OS

GND

Ø

V1A

ØV1B

ØV2

ØV3A

ØV3B

ØV4

16-PIN SHRINK-PITCH WDIP

TOP VIEW

(WDIP016-P-0500C)

Back

查询LZ23J3V供应商

2

LZ23J3V

PIN DESCRIPTION

SYMBOL PIN NAME

OD Output transistor drain
OS Output signals
ØRS Reset transistor clock
Ø

V1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 Vertical shift register clock

ØH1, ØH2 Horizontal shift register clock

PW P-well
GND Ground
NC No connection

Overflow drainOFD

ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)

PARAMETER SYMBOL RATING UNIT

Output transistor drain voltage V

OD 0 to +18 V

Reset gate clock voltage V

ØRS Internal output V

Vertical shift register clock voltage V

ØV VPW to +18 V

Horizontal shift register clock voltage VØH –0.3 to +12 V
Voltage difference between P-well and vertical clock V

PW-VØV –29 to 0 V

Storage temperature T

STG –40 to +85 ˚C

Ambient operating temperature T

OPR –20 to +70 ˚C

2

NOTE

NOTES :

1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 33 Vp-p.

2. Do not connect to DC voltage directly. When Ø

RS is connected to GND, connect VOD to GND. Reset gate clock is

applied below 8 Vp-p.

3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 28 V.

1VInternal outputVOFDOverflow drain voltage

3V0 to +17V

ØV-VØVVoltage difference between vertical clocks

3

LZ23J3V

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Ambient operating temperature T

OPR 25.0 ˚C

Output transistor drain voltage V

OD 15.0 15.5 16.0 V

NOTES :

1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.

2. V

PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected

to V

L of V driver IC.

* To apply power, first connect GND and then turn on V

OD. After turning on VOD, turn on PW first and then turn on other powers

and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.

1V32.030.028.0VØOFD

Overflow drain clock

P-well voltage VPW –10.0 VØVL V2

Ground GND 0.0 V

V–7.5–8.0–8.5

V

ØV1AL, VØV1BL, VØV2L

VØV3AL, VØV3BL, VØV4L
Vertical shift
register clock

LOW level

INTERMEDIATE level

HIGH level

V

ØV1AI, VØV1BI, VØV2I

VØV3AI, VØV3BI, VØV4I

VØV1AH, VØV1BH
VØV3AH, VØV3BH

15.0

0.0

15.5 16.0VV

LOW levelHorizontal shift

register clock

V

ØH1L, VØH2L –0.05 0.0 0.05 V

HIGH level V

ØH1H, VØH2H 4.5 5.0 5.5 V

1V5.55.04.5V

ØRSReset gate clock p-p level

Reset gate clock frequency f

ØRS 12.27 MHz

Horizontal shift register clock frequency f

ØH1, fØH2 12.27 MHz

Vertical shift register clock frequency

f

ØV1A, fØV1B, fØV2

fØV3A, fØV3B, fØV4

7.87 kHz

p-p level

LZ23J3V

4

CHARACTERISTICS (Drive method : 1/30 s frame accumulation)

(T

A = +25 ˚C, Operating conditions : The typical values specified in "

RECOMMENDED OPERATING CONDITIONS

".

Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Standard output voltage V

O 150 mV 2

Photo response non-uniformity PRNU 10 % 3

Saturation output voltage V

SAT

470 550 mV 4

Dark output voltage V

DARK 0.5 3.0 mV 1, 6

Dark signal non-uniformity DSNU 0.5 2.0 mV 1, 7
Sensitivity (green channel) R 140 200 mV 8
Smear ratio SMR –75 –65 dB 9
Image lag AI 1.0 % 10
Blooming suppression ratio ABL 500 11
Output transistor drain current I

OD 4.0 8.0 mA

NOTES :

• Within the recommended operating conditions of VOD,
V

OFD of the internal output satisfies with ABL larger than

500 times exposure of the standard exposure conditions,
and V

SAT larger than 340 mV.

1. T

A = +60 ˚C

2. The average output voltage of G signal under uniform
illumination. The standard exposure conditions are
defined as when Vo is 150 mV.

3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.

4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V

SAT is the minimum

segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
high. (for still image capturing)

5. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V

SAT is the minimum

segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
low.

6. The average output voltage under non-exposure
conditions.

7. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.

8. The average output voltage of G signal when a 1 000
lux light source with a 90% reflector is imaged by a lens
of F4, f50 mm.

9. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.

10. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.

11. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.

5mV420340

LZ23J3V

5

PIXEL STRUCTURE

1 pin

,

,

,

,

,

y

y

y

y

y

,

,

,

,

,

y

y

y

y

y

1 292 (H) x 966 (V)

OPTICAL BLACK

(2 PIXELS)

OPTICAL BLACK

(3 PIXELS)

OPTICAL BLACK

(3 PIXELS)

OPTICAL BLACK

(49 PIXELS)

COLOR FILTER ARRAY

GBGBG

RGRGR

GBGBG

RGRGR

GBGBG

RGRGR

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

GBGBG

RGRGR

GBGBG

RGRGR

GBGBG

RGRGR

(1, 966) (1 292, 966)

(1, 1) (1 292, 1)

Ø

V3A

ØV1B

ØV1A

ØV3B

ØV1B

ØV1A

ØV3A

ØV1B

ØV3B

ØV1B

ØV3A

ØV3A

Pin arrangement
of the vertical
readout clock

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

,,,,,,,

yyyyyyy

LZ23J3V

6

TIMING CHART

NOTES :

1. Do not use these signals immediately after field accumulation mode is transferred to frame
accumulation mode for still image capturing.

2. Do not use these signals immediately after frame accumulation mode is transferred to field
accumulation mode for monitoring image.

* Start the exposure period after 10 ms later that OFDC is high, and finish before charge swept

transfer.

* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.

ØV3A

ØV2

ØV1B

ØV1A

VD

TIMING CHART EXAMPLE

OS

OFDC

Ø

OFD

ØV4

ØV3B

(at OFD shutter operation)

Field accumulation mode Field accumulation 

mode

(2, 3, 6, ..)

Not for use 

(NOTE 1)

Not for use 

(NOTE 2)

Frame accumulation mode

(2, 3, 6, ..) (2, 3, 6, ..) (1, 4,

...

, 964, 965) (2, 3,

...

, 963, 966) 

(Number of 
vertical line)

Pulse diagram in more detail is shown in figures q to r after the next page.

Field accumulation mode

Frame accumulation
mode at first

Frame accumulation mode

Field accumulation
mode at first

Field accumulation 
mode

525 1525 1525 1525 1525 1525 1525 1

qqwerq'q

ØV4

OFDC

OS

Ø

V3B

ØV3A

ØV2

ØV1B

ØV1A

VD

HD

Shutter speed

1/15 s

q

VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡

ØOFD

503

504 505 506 507 508 509 510 511

... ...

...

525 1 8 9 10 11 12

963 966 OB1

RG GB

OB1 OB2 2 3 6 7

GB RG GB RG

18 19 20 21 22 23 24 25

LZ23J3V

7

ØV4

OFDC

OS

Ø

V3B

ØV3A

ØV2

ØV1B

ØV1A

VD

HD

Shutter speed

1/15 s

w

VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE AT FIRST¡

ØOFD

503

504 505 506 507 508 509 510 511

... ...

...

5251 8 9 101112

963 966 OB1
RG GB

18 20 21 22 23 24 25

Not for use

19

ØV4

OFDC

OS

Ø

V3B

ØV3A

ØV2

ØV1B

ØV1A

VD

HD

e VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡

ØOFD

503

504 505 506 507 508 509 510 511

... ... ...

525 1 8 9 10 11 12

OB31458

GB GBRG RG

18 19 20 21 22 23 24 25

Not for use

Charge swept transfer (780 stages)

* Do not use the frame signals immediately after field accumulation mode is transferred to frame

accumulation mode.

* Do not use the frame signals immediately after field accumulation mode is transferred to frame

accumulation mode.

LZ23J3V

8

ØV4

OFDC

OS

ØV3B

ØV3A

ØV2

ØV1B

ØV1A

VD

HD

r VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡

ØOFD

503 504 505 506 507 508 509 510 511

... ...

...

5251 8 9 101112

OB2 2OB1965 OB2964 367

GB GBRGRG GB RG

18 19 20 21 22 23 24 25

Not for use

Charge swept transfer (780 stages)

ØV4

OFDC

OS

Ø

V3B

ØV3A

ØV2

ØV1B

ØV1A

VD

HD

Shutter speed

1/15 s

q'

VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE AT FIRST¡

ØOFD

503

504 505 506 507 508 509 510 511

... ...

...

5251 2 9 101112

963 966 OB1
RG GB

18 20 21 22 23 24 25

Not for use

19

* Do not use the field signals immediately after frame accumulation mode is transferred to field

accumulation mode.

LZ23J3V

9

ØV3A

ØV3B

ØV4

ØV2

ØV1B

ØV1A

HD

READOUT TIMING ¿ q, w, r, q'¡

1560, 1

68

100

52 132

148

436 596

676 740

628468

612420

500 564

1560, 1 156

68

52

84 164

132

100 148

116116

156

84

452 644

164

40.7 µs (500 bits)

5.22 µs

(64 bits)

5.22 µs

(64 bits)

55.1 µs (676 bits)

127.1 µs (1 560 bits)

40.7 µs (500 bits)

5.22 µs
(64 bits)

5.22 µs

(64 bits)

55.1 µs (676 bits)

127.1 µs (1 560 bits)

1560, 1

ØV3A

ØV3B

ØV4

ØV2

ØV1B

ØV1A

HD

READOUT TIMING ¿e¡

68

100

52 132

148

436 596

676 740

628468

612420

500 564

1560, 1 156

68

52

84 164

132

100 148

116

116

156

84

452 644

164

LZ23J3V

10

OS

Ø

RS

ØH2

ØH1

HD

OB (49)

ØOFD

ØV4

ØV3A
ØV3B

ØV1A
ØV1B

ØV2

HORIZONTAL TRANSFER TIMING-1

156

68

116

100

148

52

84

108

1 clk = 81.5 ns ( = 1/12.27 MHz)

140

52

132

1560, 1

πππππ

1292

OS

Ø

RS

ØH2

ØH1

HD

Ø

OFD

ØV4

ØV3A
ØV3B

ØV1A
ØV1B

ØV2

HORIZONTAL TRANSFER TIMING-2

148

164

1 clk = 81.5 ns ( = 1/12.27 MHz)

140

132

156 240

OUTPUT (1 292) 1

ππππππππ

PRE SCAN (28)

OB (3)

LZ23J3V

11

ØV1A
ØV1B

ØV4

ØV3A
ØV3B

ØV2

HD

CHARGE SWEPT TRANSFER TIMING

510H 511H 512H 524H 3H2H1H525H 7H 8H 9H

• • • • • • • • • •

1 156 1560

15382 26507498

15382 26507498

155014 38 62 86

155014 38 62 86

1234

• • • • • • • 780779778

LZ23J3V

12

SYSTEM CONFIGURATION EXAMPLE

+

OD

PW

OFD

Ø

V3B

ØV3A

ØV4

GND

NC
Ø

H1

ØH2

OS
GND
Ø

V1A

ØV1B
ØV2

ØRS

V3B
V3A
V1B
V1A
VMa

VH

V4

V2

VL

VMb

POFD

NC

VH

ØH2

VH1BX

V3X

V2X

VH3BX

V4X

VOFDH

V1X

VH3AX

VH1AX

+3.3 V

OFDX

ØH1

ØRS

VL (VPW)

CCD

OUT

VOFDH
VH3BX
OFDX
V

2X

V1X

V3X
VDD
GND

V

4X

VH3AX

VH1BX

VH1AX

+

+

1234567812

242322212019181713

11

14

10

15

9

16

2345678

1514

1

16131211109

LR36685 LZ23J3V

(*1)(*1)

VOD

OFDC

270 pF

100 $

1 M$

1 M$

5.6 k$

18 k$

0. 47 µF

0.01 µF

+

+

(*1) ØRS, OFD :

Use the circuit parameter indicated in this circuit

example, and do not connect to DC voltage

directly.

PACKAGES FOR CCD AND CMOS DEVICES

13

16-0.46

±0.10

12-0.90

±0.10

2.63

TYP.

5.24

MAX.

3.42

±0.10

1.27

±0.25

3.90

±0.30

2.60

±0.10

P-1.78

TYP.

A'

A

0.25

±0.10

12.70

2.62

±0.10

0.80

±0.05

(◊)

1

8

14.00

±0.10

16

9

11.20

±0.10

(◊)

12.40

±0.10

6.20

±0.075

0.60

±0.60

7.00

±0.075

1.40

±0.60

θ

CCD



11.20

±0.10

(◊)

Center of effective imaging area
and center of package

Rotation error of die : θ = 1.0˚

MAX.

0.04

0.04

1.66

±0.05

Package

Glass Lid

CCD

Cross section A-A'

(◊ : Lid's size)

M0.25

+0.5
–0

16 WDIP (WDIP016-P-0500C)

PACKAGE (Unit : mm)

PRECAUTIONS FOR CCD AREA SENSORS

1. Package Breakage

In order to prevent the package from being broken,
observe the following instructions :

1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
ø Take care not to drop the device when

mounting, handling, or transporting.

ø Avoid giving a shock to the package.

Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn’t fixed.

2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.

(In the case of ceramic packages)

– The leads of the package are fixed with low

melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.

(In the case of plastic packages)

– The leads of the package are fixed with

package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.

3) When mounting the package on the housing,
be sure that the package is not bent.

– If a bent package is forced into place

between a hard plate or the like, the pack­age may be broken.

4) If any damage or breakage occurs on the sur­face of the glass cap, its characteristics could
deteriorate.

Therefore,

ø Do not hit the glass cap.
ø Do not give a shock large enough to cause

distortion.

ø Do not scrub or scratch the glass surface.

– Even a soft cloth or applicator, if dry, could

cause dust to scratch the glass.

2. Electrostatic Damage

As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following anti-static
measures when handling the CCD :

1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.

2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.

Glass cap

Package
Lead

Fixed

Stand-off

Fixed

Lead

Stand-off

Low melting point glass

14

PRECAUTIONS FOR CCD AREA SENSORS

3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or

plastic.

b. do not attach any tape or labels.

c. do not clean the glass surface with dust-

cleaning tape.

4) When storing or transporting the device, put it in
a container of conductive material.

3. Dust and Contamination

Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :

1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)

2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
ø Dust from static electricity should be blown

off with an ionized air blower. For anti­electrostatic measures, however, ground all
the leads on the device before blowing off
the dust.

ø The contamination on the glass surface

should be wiped off with a clean applicator
soaked in Isopropyl alcohol. Wipe slowly and
gently in one direction only.

– Frequently replace the applicator and do not

use the same applicator to clean more than
one device.

◊ Note : In most cases, dust and contamination

are unavoidable, even before the device
is first used. It is, therefore, recommended
that the above procedures should be
taken to wipe out dust and contamination
before using the device.

4. Other

1) Soldering should be manually performed within
5 seconds at 350 °C maximum at soldering iron.

2) Avoid using or storing the CCD at high tem­perature or high humidity as it is a precise
optical component. Do not give a mechanical
shock to the CCD.

3) Do not expose the device to strong light. For
the color device, long exposure to strong light
will fade the color of the color filters.

15

PRECAUTIONS FOR CCD AREA SENSORS