SHARP LZ23J3V Technical data
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1
DESCRIPTION
The LZ23J3V is a 1/2.7-type (6.72 mm) solid-state
image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 1 310 000 pixels (1 344 horizontal x
971 vertical), the sensor provides a stable highresolution color image.
FEATURES
• Optical size : 6.72 mm (aspect ratio 4 : 3)
• Interline scan format
• Square pixel
• Number of effective pixels : 1 292 (H) x 966 (V)
• Number of optical black pixels
– Horizontal : 3 front and 49 rear
– Vertical : 3 front and 2 rear
• Number of dummy bits
– Horizontal : 28
– Vertical : 2
• Pixel pitch : 4.2 µm (H) x 4.2 µm (V)
• R, G, and B primary color mosaic filters
• Supports monitoring mode
• Low fixed-pattern noise and lag
• No burn-in and no image distortion
• Blooming suppression structure
• Built-in output amplifier
• Built-in overflow drain voltage circuit and reset
gate voltage circuit
• Variable electronic shutter
• Package :
16-pin shrink-pitch WDIP [Plastic]
(WDIP016-P-0500C)
Row space : 12.70 mm
PIN CONNECTIONS
PRECAUTIONS
• The exit pupil position of lens should be 15 to 50
mm from the top surface of the CCD.
• Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ23J3V
1/2.7-type Interline Color CCD Area
Sensor with 1 310 k Pixels
LZ23J3V
1OD
2GND
3OFD
4PW
5Ø
RS
6NC
7Ø
H1
8
16
15
14
13
12
11
10
9Ø
H2
OS
GND
Ø
V1A
ØV1B
ØV2
ØV3A
ØV3B
ØV4
16-PIN SHRINK-PITCH WDIP
TOP VIEW
(WDIP016-P-0500C)
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2
LZ23J3V
PIN DESCRIPTION
SYMBOL PIN NAME
OD Output transistor drain
OS Output signals
ØRS Reset transistor clock
Ø
V1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 Vertical shift register clock
ØH1, ØH2 Horizontal shift register clock
PW P-well
GND Ground
NC No connection
Overflow drainOFD
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
PARAMETER SYMBOL RATING UNIT
Output transistor drain voltage V
OD 0 to +18 V
Reset gate clock voltage V
ØRS Internal output V
Vertical shift register clock voltage V
ØV VPW to +18 V
Horizontal shift register clock voltage VØH –0.3 to +12 V
Voltage difference between P-well and vertical clock V
PW-VØV –29 to 0 V
Storage temperature T
STG –40 to +85 ˚C
Ambient operating temperature T
OPR –20 to +70 ˚C
2
NOTE
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 33 Vp-p.
2. Do not connect to DC voltage directly. When Ø
RS is connected to GND, connect VOD to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 28 V.
1VInternal outputVOFDOverflow drain voltage
3V0 to +17V
ØV-VØVVoltage difference between vertical clocks
3
LZ23J3V
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Ambient operating temperature T
OPR 25.0 ˚C
Output transistor drain voltage V
OD 15.0 15.5 16.0 V
NOTES :
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. V
PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L of V driver IC.
* To apply power, first connect GND and then turn on V
OD. After turning on VOD, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1V32.030.028.0VØOFD
Overflow drain clock
P-well voltage VPW –10.0 VØVL V2
Ground GND 0.0 V
V–7.5–8.0–8.5
V
ØV1AL, VØV1BL, VØV2L
VØV3AL, VØV3BL, VØV4L
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
V
ØV1AI, VØV1BI, VØV2I
VØV3AI, VØV3BI, VØV4I
VØV1AH, VØV1BH
VØV3AH, VØV3BH
15.0
0.0
15.5 16.0VV
LOW levelHorizontal shift
register clock
V
ØH1L, VØH2L –0.05 0.0 0.05 V
HIGH level V
ØH1H, VØH2H 4.5 5.0 5.5 V
1V5.55.04.5V
ØRSReset gate clock p-p level
Reset gate clock frequency f
ØRS 12.27 MHz
Horizontal shift register clock frequency f
ØH1, fØH2 12.27 MHz
Vertical shift register clock frequency
f
ØV1A, fØV1B, fØV2
fØV3A, fØV3B, fØV4
7.87 kHz
p-p level
LZ23J3V
4
CHARACTERISTICS (Drive method : 1/30 s frame accumulation)
(T
A = +25 ˚C, Operating conditions : The typical values specified in "
RECOMMENDED OPERATING CONDITIONS
".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Standard output voltage V
O 150 mV 2
Photo response non-uniformity PRNU 10 % 3
Saturation output voltage V
SAT
470 550 mV 4
Dark output voltage V
DARK 0.5 3.0 mV 1, 6
Dark signal non-uniformity DSNU 0.5 2.0 mV 1, 7
Sensitivity (green channel) R 140 200 mV 8
Smear ratio SMR –75 –65 dB 9
Image lag AI 1.0 % 10
Blooming suppression ratio ABL 500 11
Output transistor drain current I
OD 4.0 8.0 mA
NOTES :
• Within the recommended operating conditions of VOD,
V
OFD of the internal output satisfies with ABL larger than
500 times exposure of the standard exposure conditions,
and V
SAT larger than 340 mV.
1. T
A = +60 ˚C
2. The average output voltage of G signal under uniform
illumination. The standard exposure conditions are
defined as when Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
high. (for still image capturing)
5. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
low.
6. The average output voltage under non-exposure
conditions.
7. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
8. The average output voltage of G signal when a 1 000
lux light source with a 90% reflector is imaged by a lens
of F4, f50 mm.
9. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
10. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
11. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
5mV420340
LZ23J3V
5
PIXEL STRUCTURE
1 pin
,
,
,
,
,
y
y
y
y
y
,
,
,
,
,
y
y
y
y
y
1 292 (H) x 966 (V)
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(3 PIXELS)
OPTICAL BLACK
(3 PIXELS)
OPTICAL BLACK
(49 PIXELS)
COLOR FILTER ARRAY
GBGBG
RGRGR
GBGBG
RGRGR
GBGBG
RGRGR
BGBGB
GRGRG
BGBGB
GRGRG
BGBGB
GRGRG
BGBGB
GRGRG
BGBGB
GRGRG
BGBGB
GRGRG
GBGBG
RGRGR
GBGBG
RGRGR
GBGBG
RGRGR
(1, 966) (1 292, 966)
(1, 1) (1 292, 1)
Ø
V3A
ØV1B
ØV1A
ØV3B
ØV1B
ØV1A
ØV3A
ØV1B
ØV3B
ØV1B
ØV3A
ØV3A
Pin arrangement
of the vertical
readout clock
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