Sharp LZ23BP2 Datasheet

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1

DESCRIPTION

The LZ23BP2 is a 1/3-type (6.0 mm) solid-state
image sensor that consists of PN photo-diodes and
CCDs (charge-coupled devices). With approxi­mately 350 000 pixels (695 horizontal x 504
vertical), the sensor provides a stable high­resolution color image. All pixel signals can be read
independently via the vertical shift register and
horizontal shift register.

FEATURES

• Progressive scan

• Square pixel

• Compatible with VGA format

• Number of effective pixels : 659 (H) x 494 (V)

• Number of optical black pixels
– Horizontal : 2 front and 34 rear
– Vertical : 8 front and 2 rear

• Number of dummy bits
– Horizontal : 16
– Vertical : 4

• Pixel pitch : 7.4 µm (H) x 7.4 µm (V)

• R, G, and B primary color mosaic filters

• Low fixed-pattern noise and lag

• No burn-in and no image distortion

• Blooming suppression structure

• Built-in output amplifier

• Built-in overflow drain voltage circuit and reset
gate voltage circuit

• Variable electronic shutter (1/30 to 1/10 000 s)

• Package :
16-pin half-pitch WDIP [Ceramic]
(WDIP016-N-0450)
Row space : 11.43 mm

PIN CONNECTIONS

PRECAUTIONS

• The exit pupil position of lens should be more
than 25 mm from the top surface of the CCD.

• Refer to "PRECAUTIONS FOR CCD AREA

SENSORS" for details.

LZ23BP2

1/3-type Progressive-scan Color CCD

Area Sensor with 350 k Pixels

LZ23BP2

1ØV4

2ØV3

3ØV2

4ØV1

5GND

6NC

1

7GND

8

16

15

14

13

12

11

10

9OS

Ø

H2

ØH1

ØRS

PW

OFD

GND

NC

2

OD

16-PIN HALF-PITCH WDIP

TOP VIEW

(WDIP016-N-0450)

LZ23BP2

2

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

(TA = +25 ˚C)

SYMBOL PIN NAME

OD Output transistor drain
OS Output signals
ØRS Reset transistor clock
Ø

V1, ØV2, ØV3, ØV4 Vertical shift register clock

ØH1, ØH2 Horizontal shift register clock

PW P-well
GND Ground
NC

1, NC2 No connection

PARAMETER SYMBOL RATING UNIT

Output transistor drain voltage V

OD 0 to +18 V

Reset gate clock voltage V

ØRS Internal output V

Vertical shift register clock voltage V

ØV –11.5 to +17.5 V

Horizontal shift register clock voltage VØH –0.3 to +12 V
Voltage difference between P-well and vertical clock V

PW-VØV –29 to 0 V

Storage temperature T

STG –40 to +85 ˚C

Ambient operating temperature T

OPR –20 to +70 ˚C

2

NOTE

NOTES :

1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 27 Vp-p.

2. Do not connect to DC voltage directly. When Ø

RS is connected to GND, connect VOD to GND. Reset gate clock is

applied below 8 Vp-p.

3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 28 V.

Overflow drainOFD

1VInternal outputV

OFDOverflow drain voltage

3V0 to +15VØV-VØVVoltage difference between vertical clocks

3

LZ23BP2

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Ambient operating temperature T

OPR 25.0 ˚C

Output transistor drain voltage V

OD 14.55 15.0 15.45 V

NOTES :

• Connect NC1 and NC2 to GND directly or through a capacitor larger than 0.047 µF.

1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.

2. V

PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected

to V

L of V driver IC.

* To apply power, first connect GND and then turn on V

OD. After turning on VOD, turn on PW first and then turn on other powers

and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.

1V24.522.5VØOFD

Overflow drain clock

P-well voltage VPW –10.0 VØVL V2

Ground GND 0.0 V

V–8.5–9.0–9.5

V

ØV1L, VØV2L

VØV3L, VØV4L

Vertical shift
register clock

LOW level

INTERMEDIATE level

HIGH level

V

ØV1I, VØV2I

VØV3I, VØV4I

VØV1H, VØV3H 14.55

0.0

15.0 15.45VV

LOW levelHorizontal shift

register clock

V

ØH1L, VØH2L –0.05 0.0 0.05 V

HIGH level VØH1H, VØH2H 4.5 5.0 5.5 V

1V5.55.04.5V

ØRSReset gate clock p-p level

Reset gate clock frequency f

ØRS 12.27 MHz

Horizontal shift register clock frequency fØH1, fØH2 12.27 MHz

Vertical shift register clock frequency

f

ØV1, fØV2

fØV3, fØV4

15.73 kHz

p-p level

4

LZ23BP2

CHARACTERISTICS (1/30 s progressive scan readout mode)

(T

A = +25 ˚C, Operating conditions : The typical values specified in "

RECOMMENDED OPERATING CONDITIONS

".

Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Standard output voltage V

O 150 mV 2

Photo response non-uniformity PRNU 10 % 3
Saturation output voltage V

SAT 500 mV 4

Dark output voltage V

DARK 0.5 3.0 mV 1, 5

Dark signal non-uniformity DSNU 0.5 2.0 mV 1, 6
Sensitivity (green channel) R 245 370 mV 7

Smear ratio SMR –86 –76 dB 9
Image lag AI 1.0 % 10
Blooming suppression ratio ABL 500 11
Output transistor drain current I

OD 4.0 8.0 mA

Output impedance R

O 350 $

Dark noise V

NOISE 0.2 0.3 mV 12

OB difference in level 1.0 mV 1, 13

NOTES :

• Within the recommended operating conditions of VOD,
V

OFD of the internal output satisfies with ABL larger than

500 times exposure of the standard exposure conditions,
and V

SAT larger than 500 mV.

1. T

A = +60 ˚C

2. The average output voltage of G signal under uniform
illumination. The standard exposure conditions are
defined as when Vo is 150 mV.

3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.

4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V

SAT is the minimum

segment's voltage under 10 times exposure of the
standard exposure conditions.

5. The average output voltage under non-exposure
conditions.

6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.

7. The average output voltage of G signal when a 1 000
lux light source with a 90% reflector is imaged by a lens
of F4, f50 mm.

8. R

R is defined by VR/VG. RB is defined by VB/VG, where

V

R, VG and VB are the average output voltages of red,

green and blue signals respectively, under the standard
exposure conditions.

9. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.

10. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.

11. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.

12. The RMS value of the dark noise (after CDS). (100 kHz
to 5.0 MHz, SC trap on.)

13. The difference between the average output voltage of
the effective area and that of the OB area under non­exposure conditions.

80.80.550.3RR

Sensitivity ratio

80.60.40.2R

B