Sharp LZ21N3V, LZ21N3VS Datasheet
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1
DESCRIPTION
The LZ21N3V/VS are 1/2-type (8.08 mm) solidstate image sensors that consist of PN photodiodes and CCDs (charge-coupled devices). With
approximately 2 140 000 pixels (1 704 horizontal x
1 255 vertical), the sensor provides a stable highresolution color image.
FEATURES
• Optical size : 8.08 mm (aspect ratio 4 : 3)
• Interline scan format
• Square pixel
• Number of effective pixels : 1 650 (H) x 1 250 (V)
• Number of optical black pixels
– Horizontal : 2 front and 52 rear
– Vertical : 3 front and 2 rear
• Number of dummy bits
– Horizontal : 28
– Vertical : 2
• Pixel pitch : 3.95 µm (H) x 3.95 µm (V)
• R, G, and B primary color mosaic filters
• Supports monitoring mode
• Low fixed-pattern noise and lag
• No burn-in and no image distortion
• Blooming suppression structure
• Built-in output amplifier
• Built-in overflow drain voltage circuit and reset
gate voltage circuit
• Variable electronic shutter
• Packages
– LZ21N3V : 20-pin half-pitch WDIP [Plastic]
(WDIP020-P-0500)
Row space : 12.20 mm
– LZ21N3VS : 20-pin half-pitch WSOP [Plastic]
(WSOP020-P-0525)
PIN CONNECTIONS
PRECAUTIONS
• The exit pupil position of lens should be 30 to 50
mm from the top surface of the CCD.
• Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ21N3V/VS
LZ21N3V/VS
1/2-type Interline Color CCD
Area Sensors with 2 140 k Pixels
1OD
2GND
3OFD
4PW
5Ø
RS
6NC1
7NC2
8ØH1
9NC3
10ØH2
20
19
18
17
16
15
14
OS
GND
NC
5
NC4
ØV1A
ØV1B
ØV2
13 ØV3A
12 ØV3B
11 ØV4
20-PIN HALF-PITCH WDIP
20-PIN HALF-PITCH WSOP
TOP VIEW
(WDIP020-P-0500)
(WSOP020-P-0525)
Package
LZ21N3V
20-pin half-pitch WDIP
COMPARISON TABLE
20-pin half-pitch WSOP
LZ21N3VS
2
LZ21N3V/VS
PIN DESCRIPTION
SYMBOL PIN NAME
OD Output transistor drain
OS Output signals
ØRS Reset transistor clock
Ø
V1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 Vertical shift register clock
ØH1, ØH2 Horizontal shift register clock
PW P-well
GND Ground
NC1, NC2, NC3, NC4, NC
5
No connection
Overflow drainOFD
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
PARAMETER SYMBOL RATING UNIT
Output transistor drain voltage V
OD 0 to +15 V
Reset gate clock voltage V
ØRS Internal output V
Vertical shift register clock voltage V
ØV VPW to +15 V
Horizontal shift register clock voltage VØH –0.3 to +12 V
Voltage difference between P-well and vertical clock V
PW-VØV –24 to 0 V
Storage temperature T
STG –40 to +85 ˚C
Ambient operating temperature T
OPR –20 to +70 ˚C
2
NOTE
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 22 Vp-p.
2. Do not connect to DC voltage directly. When Ø
RS is connected to GND, connect VOD to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 22 V.
1VInternal outputVOFDOverflow drain voltage
3V0 to +15V
ØV-VØVVoltage difference between vertical clocks
3
LZ21N3V/VS
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Ambient operating temperature T
OPR 25.0 ˚C
Output transistor drain voltage V
OD 12.5 13.0 13.5 V
NOTES :
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. V
PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L of V driver IC.
* To apply power, first connect GND and then turn on V
OD. After turning on VOD, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1V20.919.518.6VØOFD
Overflow drain clock
P-well voltage VPW –8.0 VØVL V2
Ground GND 0.0 V
V–6.65–7.0–7.35
V
ØV1AL, VØV1BL, VØV2L
VØV3AL, VØV3BL, VØV4L
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
V
ØV1AI, VØV1BI, VØV2I
VØV3AI, VØV3BI, VØV4I
VØV1AH, VØV1BH
VØV3AH, VØV3BH
12.5
0.0
13.0 13.5VV
LOW levelHorizontal shift
register clock
V
ØH1L, VØH2L –0.05 0.0 0.05 V
HIGH level V
ØH1H, VØH2H 4.5 4.8 5.5 V
1V5.54.84.5V
ØRSReset gate clock p-p level
Reset gate clock frequency f
ØRS 17.94 MHz
Horizontal shift register clock frequency f
ØH1, fØH2 17.94 MHz
Vertical shift register clock frequency
f
ØV1A, fØV1B, fØV2
fØV3A, fØV3B, fØV4
7.87 kHz
p-p level
LZ21N3V/VS
4
CHARACTERISTICS (Drive method : 1/30 s frame accumulation)
(T
A = +25 ˚C, Operating conditions : The typical values specified in "
RECOMMENDED OPERATING CONDITIONS
".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Standard output voltage V
O 150 mV 2
Photo response non-uniformity PRNU 10 % 3
Saturation output voltage V
SAT
450 530 mV 4
Dark output voltage V
DARK 0.5 3.0 mV 1, 6
Dark signal non-uniformity DSNU 0.5 2.0 mV 1, 7
Sensitivity (green channel) R 140 180 mV 8
Smear ratio SMR –89 –82 dB 9
Image lag AI 1.0 % 10
Blooming suppression ratio ABL 1 000 11
Output transistor drain current I
OD 4.0 8.0 mA
NOTES :
• Within the recommended operating conditions of VOD,
V
OFD of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and V
SAT larger than 320 mV.
1. T
A = +60 ˚C
2. The average output voltage of G signal under uniform
illumination. The standard exposure conditions are
defined as when Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
high. (for still image capturing)
5. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
low.
6. The average output voltage under non-exposure
conditions.
7. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
8. The average output voltage of G signal when a 1 000
lux light source with a 90% reflector is imaged by a lens
of F4, f50 mm.
9. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
10. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
11. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
5mV400320
LZ21N3V/VS
5
PIXEL STRUCTURE
1 650 (H) x 1 250 (V)
1 pin
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(52 PIXELS)
OPTICAL BLACK
(3 PIXELS)
OPTICAL BLACK
(2 PIXELS)
COLOR FILTER ARRAY
(1, 1 250) (1 650, 1 250)
(1, 1)
(1 650, 1)
Ø
V3B
ØV1B
ØV3A
ØV1B
ØV3B
ØV1B
ØV3B
ØV1A
ØV3B
ØV1B
ØV3B
ØV1B
ØV3B
ØV1B
ØV3B
ØV1B
ØV3A
ØV1B
ØV3B
ØV1B
ØV3B
ØV1A
ØV3B
ØV1B
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
G
RGRGRGRGRG
BGBGBGBGB G
RGRGRGRGRG
BGBGBGBGB
Pin arrangement
of the vertical
readout clock
LZ21N3V/VS
6
TIMING CHART
NOTES :
1. Do not use these signals immediately after field accumulation mode is transferred to frame
accumulation mode for still image capturing.
2. Do not use these signals immediately after frame accumulation mode is transferred to field
accumulation mode for monitoring image.
* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.
ØV3A
ØV2
ØV1B
ØV1A
VD
TIMING CHART EXAMPLE
OS
OFDC
Ø
OFD
ØV4
ØV3B
263
525 1 1263
525
656 1 263 525 1
656
1
656
1
(at OFD shutter operation)
(Number of
vertical line)
Pulse diagram in more detail is shown in figures q to t after the next page.
Field accumulation mode Frame accumulation
mode at first
Frame accumulation mode Field accumulation
mode at first
Field accumulation
mode
qqwe rtqq'q'
Field accumulation mode Field accumulation
Not for use
(NOTE 1)
Not for use
(NOTE 2)
Frame accumulation mode
(3, 8, 13,..) (3, 8, 13,..) (3, 8, 13,..)
(1, 3,
...
, 1247, 1249) (2, 4,
...
, 1248, 1250)
mode (3, 8, 13,
..
)
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