Sharp LRS1342, LRS1341 Datasheet
Data Sheet
LRS1341/LRS1342
Stacked Chip
16M Flash Memory and 2M SRAM
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
•Flash Memory
– Access time (MAX.): 100 ns
– Operating current (MAX.):
The current for F-V
– Read: 25 mA (t
pin
CC
CYCLE
= 200 ns)
– Word write: 17 mA
– Block erase: 17 mA
– Deep power down current (the current for
pin): 10 µA (MAX. F-CE ≥ F-VCC - 0.2 V,
F-V
CC
≤ -0.2 V, F-VPP ≤ 0.2 V)
F-RP
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
PIN CONFIGURATION
– Thirty-one 32K-word main blocks
– Top/Bottom boot location versions
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
•SRAM
– Access time (MAX.): 85 ns
– Operating current (MAX.):
– 45 mA
–8 mA (t
, tWC = 1 µs)
RC
– Standby current: 45 µA (MAX.)
– Data retention current: 35 µA (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 × 16-bit flash memory and
131,072 × 16-bit static RAM in one package.
INDEX
1234567
A
NC NC NC A
B
C
D
E
F
G
NC NC
H NC A5A4A
NOTE: Two NC pins at the corner are connected.
A
16
F-WE
GND
F-WP
S-LB
F-A18F-A17A7A6A3A
Figure 1. LRS1341/LRS1342 Pin Configuration
A11A
15
14
10
T1T
T
2
S-OE
A
9
3
T
4
NC DQ
0
A8A
F-RY/
BY
F-RP
F-VPPF-A19DQ11T
S-UB
A
DQ
DQ
DQ
TOP VIEW72-BALL FBGA
8
910
GND
12
13
DQ
S-WE
15
DQ
13
S-CE
12
DQ
5
DQ
9
GND
14
DQ
6
4
S-V
CC
2
DQ
10
2
DQ
8
0
A
2
1
F-OEF-CE
DQ
DQ
F-V
CC
DQ
DQ
S-CE
11
12
NCNCA
NC
7
5
3
1
1
NCNC
NC
LRS1342-1
Data Sheet 1
LRS1341/LRS1342 Stacked Chip (16M Flash & 2M SRAM)
CC
F-V
PP
A
F-A
F-A
0
17
19
to A
F-V
to
16
F-CE
F-OE
16M (x16) BIT
FLASH MEMORY
F-WE
F-RP
F-WP
S-CE
1
S-CE
2
S-OE
2M (x16) BIT
SRAM
S-WE
S-LB
S-UB
S-V
CC
Figure 2. LRS1341/LRS1342 Block Diagram
F-RY/BY
GND
DQ0 to
DQ
15
LRS1342-2
2 Data Sheet
Stacked Chip (16M Flash & 2M SRAM) LRS1341/LRS1342
Table 1. Pin Descriptions
PIN DESCRIPTION TYPE
to A
A
0
16
F-A
to F-A
17
F-CE
, S-CE2Chip Enable Inputs (SRAM) Input
S-CE
1
F-WE
S-WE
F-OE
S-OE
S-LB
S-UB
Address Inputs (Common) Input
Address Inputs (Flash) Input
19
Chip Enable Input (Flash) Input
Write Enable Input (Flash) Input
Write Enable Input (SRAM) Input
Output Enable Input (Flash) Input
Output Enable Input (SRAM) Input
SRAM Byte Enable Input (DQ0 to DQ7) Input
SRAM Byte Enable Input (DQ8 to DQ15) Input
Reset/Power Down (Flash)
F-RP
Block erase and Word Write: V
Read: VIH or V
Reset/Power Down: V
HH
IL
IH
or V
HH
Input
Write Protect (Flash)
F-WP
Two Boot Blocks Locked: V
(with F-RP = VHH
IL
Input
Erase of Write can operate to all blocks)
Ready/Busy (Flash)
F-RY/BY
DQ
to DQ
0
F-V
S-V
CC
CC
During an Erase or Write operation: V
Block Erase and Word Write Suspend: HIGH-Z
Deep Power Down: V
Data Input/Outputs (Common) Input/Output
15
OH
Power Supply (Flash) Power
Power Supply (SRAM) Power
OL
Output
Write, Erase Power Supply (Flash)
F-V
PP
Block Erase and Word Write: F-V
All Blocks Locked: F-VPP < V
PPLK
PP
= V
PPLK
Power
GND Ground (Common) Power
NC No Connection —
T
to T
1
5
Test Pins (Should be Open) —
Data Sheet 3
LRS1341/LRS1342 Stacked Chip (16M Flash & 2M SRAM)
Table 2. Truth Table
FLASH SRAM F-CE
Read Standby L H L H
Output Disable Standby L H H H X X HIGH-Z 3
Write Standby L H H L X X D
F-RP F-OE F-WE S-CE1S-CE2S-OE S-WE S-LB S-UB
See Note 4
1
XX
See Note 4
DQ0 DQ-7
DQ8 DQ
15
D
OUT
IN
2, 3, 5, 6
Read H H X X L H L H See Note 7
Standby
Reset/Power Down
Output
Disable
Write H H X X L H L L
Read X L X X L H L H
Output
Disable
H H X X L H H H X X HIGH-Z
H H X X L H X X H H HIGH-Z
See Note 7
XLX X L H HH XX HIGH-Z
X L X X L H X X H H HIGH-Z
Write X L X X L H L L See Note 7
Standby Standby H H X X
Reset/Power Down Standby X L X X X X HIGH-Z 3
NOTES:
1. L = V
2. Refer to the ‘Flash Memory Command Definition’ section for valid
3. F-WP
, H = VIH, X = H or L. Refer to DC Characteristics.
IL
during a write operation.
D
IN
set to VIL or VIH.
4. SRAM standby mode. See Table 2a.
See Note 4
5. Command writes involving block erase or word write are reliably
6. Never hold F-OE
7. S-LB
XX
executed when F-V
erase or word write with V
See Note 4
= V
PP
PPH
< RP < VHH produce spurious results
IH
and should not be attempted.
LOW and F-WE LOW at the same time.
, S-UB control mode. See Table 2b.
HIGH-Z 3
and F-VCC = 2.7 V to 3.6 V. Block
NOTES
2, 3
MODE
Standby
(SRAM)
COMMAND
Table 2a.
PINS
S-CE
S-CE
1
S-LB S-UB
2
HXXX
XLXX
XXHH
Table 3. Command Definition for Flash Memory
BUS CYCLES
REQUIRED
OPERATION
FIRST BUS CYCLE SECOND BUS CYCLE
2
ADDRESS
3
MODE
(SRAM)
Read/Write
3
DATA
S-LB
LLD
LHD
HLHIGH-ZD
OPERATION2ADDRESS3DATA
Table 2b.
PINS
S-UB DQ0 - DQ7DQ8 - DQ
OUT/DIN
OUT/DIN
1
3
D
OUT/DIN
HIGH-Z
OUT/DIN
NOTES
Read Array/Reset 1 Write XA FFH
Read Identifier Codes ≥ 2 Write XA 90H Read IA ID 4
Read Status Register 2 Write XA 70H Read XA SRD
Clear Status Register 1 Write XA 50H
Block Erase 2 Write BA 20H Write BA D0H 5
Word Write 2 Write WA 40H or 10H Write WA WD 5
Block Erase and Word
Write Suspend
Block Erase and Word
Write Resume
NOTES:
1. Commands other than those shown in table are reserved by
SHARP for future device implementations and should not be used.
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
IA = Identifier code address;
BA = Address within the block being erased;
1WriteXAB0H 5
1WriteXAD0H 5
WA = Address of memory location to be written;
SRD = Data read from status register, see Table 6;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE
or F-CE (whichever goes high first);
ID = Data read from identifier codes.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
15
4 Data Sheet
Stacked Chip (16M Flash & 2M SRAM) LRS1341/LRS1342
Table 4. Identifier Codes
CODES
ADDRESS
- A18)
(A
0
LRS1341 DATA
(DQ0 - DQ7)
LRS1342 DATA
(DQ0 - DQ7)
Manufacture Code 00000H B0H B0H
Device Code 00001H 48H 49H
Table 5. Write Protection Alternatives
OPERATION F-V
Block Erase or
Word Write
> V
V
IL
PPLK
PP
F-RP F-WP EFFECT
XX
V
IL
V
HH
V
IH
V
IH
V
All blocks locked
All blocks locked
X
All blocks unlocked
X
Two boot blocks locked
V
IL
All blocks unlocked
IH
Table 6. Status Register Definition
WSMS ESS ES WWS VPPS WWSS DPS R
76543210
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase Status (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = Word Write Status (WWS)
1 = Error in Word Write
NOTES:
1. Check RY/BY
completion. SR.6 - SR.0 are invalid while SR.7 = 0.
2. If both SR.5 and SR.4 are ‘1’s after a block erase attempt, an
improper command sequence was entered.
3. SR.3 does not provide a continuous indication of F-V
WSM interrogates and indicates the F-V
Erase or Word Write command sequences. SR.3 is not guaranteed
to report accurate feedback only when F-V
4. The WSM interrogates the F-WP
or Word Write command sequences. It informs the system,
depending on the attempted operation, if the F-WP
F-RP
5. SR.0 is reserved for future use and should be masked out when
is not VHH.
polling the status register.
or SR.7 to determine block erase or word write
≠ V
PP
, V
PPH1
is not VIH or
level only after Block
PP
and F-RP only after Block Erase
PP
0 = Successful Word Write
level. The
.
PPH2
SR.3 = V
1 = F-V
0 = F-V
Status (VPPS)
PP
LOW Detect, Operation Abort
PP
Okay
PP
SR.2 = Word Write Suspend Status (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = F-WP
and/or F-RP Lock Detected,
Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
Data Sheet 5
LRS1341/LRS1342 Stacked Chip (16M Flash & 2M SRAM)
MEMORY MAPS
[A0 - A19]
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD BOOT BLOCK
4K-WORD BOOT BLOCK
30
2932K-WORD MAIN BLOCK
2832K-WORD MAIN BLOCK
2732K-WORD MAIN BLOCK
2632K-WORD MAIN BLOCK
2532K-WORD MAIN BLOCK
2432K-WORD MAIN BLOCK
2332K-WORD MAIN BLOCK
2232K-WORD MAIN BLOCK
2132K-WORD MAIN BLOCK
2032K-WORD MAIN BLOCK
1932K-WORD MAIN BLOCK
18 32K-WORD MAIN BLOCK
1732K-WORD MAIN BLOCK
1632K-WORD MAIN BLOCK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0
BOTTOM BOOT
LRS1342-3
Figure 3. Bottom Boot for Flash Memory
[A0 - A19]
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
TOP BOOT
4K-WORD BOOT BLOCK
4K-WORD BOOT BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
Figure 4. Top Boot for Flash Memory
0
1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LRS1342-13
6 Data Sheet
Stacked Chip (16M Flash & 2M SRAM) LRS1341/LRS1342
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATINGS UNIT NOTES
Supply voltage V
Input voltage V
Operating temperature T
Storage temperature T
voltage F-V
F-V
PP
voltage F-RP -0.5 to +14.0 V 1, 4, 5
F-RP
NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-V
3. Except F-RP
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
PP
.
.
CC
IN
OPR
STG
PP
-0.2 to +3.9 V 1, 2
-0.2 to VCC +0.3 V 1, 3, 4
-25 to +85 °C
-55 to +125 °C
-0.2 to +14.0 V 1, 4, 5
RECOMMENDED DC OPERATING CONDITIONS
TA = -25°C to +85°C
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Supply voltage V
Input voltage
CC
V
IH
V
IL
V
HH
2.7 3.0 3.6 V
2.2 VCC + 0.2 V 1
-0.2 0.6 V 2
11.4 12.6 V 3
NOTES:
1. V
is the lower one of S-VCC and F-VCC.
CC
2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
3. This voltage is applicable to F-RP
pin only.
PIN CAPACITANCE
TA = 25°C, f = 1 MHz
PARAMETER SYMBOL CONDITION MIN. TYP. MAX. UNIT
Input capacitance* C
I/O capacitance* C
NOTE: *Sampled by not 100% tested.
IN
I/O
VIN = 0 V 20 pF
V
= 0 V 22 pF
I/O
Data Sheet 7
LRS1341/LRS1342 Stacked Chip (16M Flash & 2M SRAM)
DC CHARACTERISTICS
TA = -25°C to + 85°C, VCC = 2.7 V to 3.6 V
1
PARAMETER SYMBOL CONDITION MIN. TYP.
Input leakage current I
Output leakage current I
VIN = VCC or GND -1.5 +1.5 µA
LI
V
LO
= VCC or GND -1.5 +1.5 µA
OUT
F-CE = F-RP = F-VCC ± 0.2 V
F-WP
Standby Current I
Deep Power-Down Current I
CCS
CCD
= F-VCC ± 0.2 V
or F-GND ± 0.2 V
F-CE
= F-RP = V
F-RP = F-GND ± 0.2 V,
(F-RY/BY) = 0 mA
I
OUT
CMOS input, F-CE = F-GND,
Read Current I
F-V
CC
CCR
f = 5 MHz, I
TTL input, F-CE
f = 5 MHz, I
Word Write Current I
Block Erase Current I
Word Write Block Erase
Suspend Current
Standby or Read Current
I
CCWS
I
CCES
I
I
Deep Power-Down Current I
Word Write Current I
F-V
PP
Block Erase Current I
Word Write or Block Erase
Suspend Current
I
PPWS
I
PPES
Standby Current
S-V
CC
I
Operation Current
I
Input LOW Voltage V
Input HIGH Voltage V
Output LOW Voltage V
Output HIGH Voltage (CMOS) V
Lockout during Normal Operations V
F-V
PP
F-V
Word Write or Block Erase
PP
Operations
Lockout Voltage V
F-V
CC
Unlock Voltage V
F-RP
V
V
CCW
PPW
I
F-VPP = 2.7 V to 3.6 V 17 mA
= 11.4 V to 12.6 V 12 mA
F-V
PP
F-VPP = 2.7 V to 3.6 V 17 mA
CCE
= 11.4 V to 12.6 V 12 mA
F-V
PP
F-CE = V
F-VPP = F-V
PPS
PPR
PPD
> F-V
F-V
PP
F-RP = F-GND ± 0.2 V 0.1 5 µA
F-VPP = 2.7 V to 3.6 V 12 40 mA
= 11.4 V to 12.6 V 30 mA
F-V
PP
F-VPP = 2.7 V to 3.6 V 8 25 mA
PPE
= 11.4 V to 12.6 V 20 mA
F-V
PP
F-VPP = V
S-CE1, S-CE2 ≥ S-VCC - 0.2 V
I
SB
or S-CE
S-CE1 = VIH or S-CE2 = V
SB1
S-CE1 = VIL, S-CE2 = VIH, VIN = VIL or
CC1
V
IH
, t
CYCLE
≤ 0.2 V
2
S-CE1 = 0.2 V, S-CE2 = S-VCC - 0.2 V,
V
CC2
IL
IH
OL
OH1IOH
PPLK
PPH1
PPH2
LKO
HH
= S-VCC - 0.2 V, or 0.2 V
IN
= 1 µs, I
t
CYCLE
IOL = 0.5 mA 0.4 V 2
= -0.5 mA 2.2 V 2
Unavailable F-WP 11.4 12.6 V 6
NOTES:
1. Reference values at V
2. Includes F-RY/BY
= 3.0 V and TA = +25°C.
CC
.
3. Automatic Power Savings (APS) for Flash Memory reduces typi to 3 mA at 2.7 VCC in static operation.
cal I
CCR
4. CMOS inputs are either V
are either V
or VIH.
IL
± 0.2 V or GND ± 0.2 V. TTL inputs
CC
OUT
OUT
IH
CC
CC
PPH
= MIN., I
25 50 µA 2
F-WP = VIH or V
IH,
IL
0.2 2 mA
= 0 mA
= F-GND,
= 0 mA
±2 ±15 µA
10 200 µA
10 200 µA
IL
= 0 mA
I/O
= 0 mA
I/O
-0.2 0.6 V
2.2 VCC + 0.2 V
2.7 3.6 V
11.4 12.6 V
1.5 V
5. Block erases and word writes are inhibited when F-V
not guaranteed in the range between V
(MIN.), and above V
6. F-RP
connection to a VHH supply is allowed for a maximum cumu-
PPH
(MAX.).
lative period of 80 hours.
MAX. UNIT NOTES
510µA
25 mA 3, 4
30 mA 3, 4
6mA
45 µA
3mA
45 mA
8mA
1.5 V 5
PP≤VPPLK
(MAX.) and V
PPLK
and
PPH
8 Data Sheet
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