Sharp LRS1331 Datasheet

Data Sheet

LRS1331

Stacked Chip

16M Flash Memory and 4M SRAM

FEATURES

• Flash Memory and SRAM

• Stacked Die Chip Scale Package

• 72-ball 8 mm × 11 mm CSP plastic package

• Power supply: 2.7 V to 3.6 V

• Operating temperature: -25°C to +85°C

•Flash Memory – Access time (MAX.): 90 ns – Operating current (MAX.)

(The current for F-V – Read: 25 mA (t

CYCLE

pin and F-V

CC

= 200 ns)

CCW

pin):

– Word write: 57 mA – Block erase: 42 mA

– Standby current (the current for F-V

(MAX. F-RP

≤ GND ± 0.2 V)

pin): 15 µA

CC

– Optimized array blocking architecture

– Two 4K-word boot blocks – Six 4K-word parameter blocks

PIN CONFIGURATION

INDEX

– Thirty-one 32K-word main blocks – Bottom boot location

– Extended cycling capability

– 100,000 block erase cycles

– Enhanced automated suspend options

– Word write suspend to read – Block erase suspend to word write – Block erase suspend to read

•SRAM – Access time (MAX.): 85 ns – Operating current: 45 mA (MAX.) – Standby current: 15 µA (MAX.) – Data retention current: 2 µA (MAX.)

DESCRIPTION

The LRS1331 is a combination memory organized as

1,048,576 × 16-bit flash memory and 262,144 × 16-bit static RAM in one package.

TOP VIEW72-BALL FBGA

1234567

A

NC NC NC A

B

C

D

E

F

G

NC NC

H NC A5A4A

NOTE: All F-GND and S-GND pins are connected on the board. Two NC pins at the corner are connected.

A11A

15

A

A8A

16

F-RY/

F-WE

GND

F-RP T

F-WP

F-VPPF-A19DQ11T

S-LB

S-UB

F-A18F-A17A7A6A3A

BY

10

T

1

2

S-OE

Figure 1. LRS1331 Pin Configuration

A

14

A

DQ

9

S-A17DQ

DQ

T

4

NC DQ

0

8

910

F-GND

A

12

13

DQ

S-WE

3

15

13

12

9

DQ

S-CE

DQ

F-GND

14

DQ

6

4

S-V

CC

2

DQ

10

2

DQ

8

0

A

2

1

F-OEF-CE

DQ

F-V

DQ

S-CE

11

12

NCNC

NC

7

5

CC

3

1

NCNC

NC

LRS1331-1

Data Sheet 1

LRS1331 Stacked Chip (16M Flash & 4M SRAM)

F-V

PP

SRAM

F-GND

F-RY/BY

DQ

0

DQ

15

to

A

F-A F-A

0

to A

17

19

F-CE

F-OE

F-WE

F-RP

F-WP

S-A

S-CE

S-OE

S-WE

S-UB

S-LB

to

F-V

CC

16

16M (x16) BIT

FLASH MEMORY

17

1

2

4M (x16) BIT

S-GNDS-V

CC

Figure 2. LRS1331 Block Diagram

LRS1331-2

2 Data Sheet

Stacked Chip (16M Flash & 4M SRAM) LRS1331

Table 1. Pin Descriptions

PIN DESCRIPTION TYPE

A

to A

0

16

to F-A

F-A

17

S-A

17

F-CE

, S-CE2Chip Enable Inputs (SRAM) Input

S-CE

1

F-WE

S-WE

F-OE

S-OE

S-LB

S-UB

Address Inputs (Common) Input

Address Inputs (Flash) Input

19

Address Input (SRAM) Input

Chip Enable Input (Flash) Input

Write Enable Input (Flash) Input

Write Enable Input (SRAM) Input

Output Enable Input (Flash) Input

Output Enable Input (SRAM) Input

SRAM Byte Enable Input (DQ0 to DQ7) Input

SRAM Byte Enable Input (DQ8 to DQ15) Input

Deep Power Down Input (Flash)

F-RP

F-WP

Block erase and Word Write: V Read: V Deep Power Down: V

IH

IL

Write Protect Input (Flash)

Two Boot Blocks Locked: V

IH

Input

IL

Ready/Busy Output(Flash)

F-RY/BY

to DQ

DQ

0

F-V

S-V

CC

During an Erase or Write operation: V Block Erase and Word Write Suspend: HIGH-Z Deep Power Down: V

Data Input and Outputs (Common) Input/Output

15

OH

Power Supply (Flash) Power

Power Supply (SRAM) Power

OL

Output

Write, Erase Power Supply (Flash)

F-V

PP

Block Erase and Word Write: F-V All Blocks Locked: F-VPP < V

PPLK

PP

= V

PPLK

Power

F-GND Ground (Flash) Power

S-GND Ground (SRAM) Power

NC No Connection —

T

to T

1

5

Test Pins (Should be Open) —

Data Sheet 3

LRS1331 Stacked Chip (16M Flash & 4M SRAM)

Table 2. Truth Table

FLASH SRAM F-CE

Read Standby L H L H

Output Disable Standby L H H H X X HIGH-Z 3

Write Standby L H H L X X D

F-RP F-OE F-WE S-CE1S-CE2S-OE S-WE S-LB S-UB

See Note 4

1

XX

See Note 4

DQ0 -

DQ

DQ8 DQ

7

D

OUT

IN

15

NOTES

2, 3, 5, 6

Read H H X X L H L H See Note 7

Standby

Reset

Output Disable

Write H H X X L H L L

Read X L X X L H L H

Output Disable

HHX X L H H HX X HIGH-Z

HHX X L H X X HH HIGH-Z

See Note 7

XLX X L H HHXX HIGH-Z

XLX X L H X XHH HIGH-Z

Write X L X X L H L L See Note 7

Standby Standby H H X X

Reset Standby X L X X X X HIGH-Z 3

NOTES:

1. L = V

, H = VIH, X = H or L. Refer to DC Characteristics.

IL

See Note 4

5. Command writes involving block erase or word write are reliably

2. Refer to the ‘Flash Memory Command Definition’ section for valid address input and D

3. F-WP

set to VIL or VIH.

4. SRAM standby data. See Table 2a.

during a write operation.

IN

6. Never hold F-OE

7. S-LB

XX

executed when V

See Note 4

(2.7 V to 3.6 V) and F-VCC = 2.7 V to

CCWH

3.6 V. Block erase or word write with F-V

HIGH-Z 3

< V

CCW

CCWH

produce spurious results and should not be attempted.

LOW and F-WE LOW at the same timing.

, S-UB Control Mode. See Table 2b.

2, 3

(MIN.)

MODE

Standby (SRAM)

Table 2a.

PINS

S-CE

1

2

S-LB S-UB

HXXX

XLXX

XXHH

MODE

(SRAM)

Read/Write

Table 2b.

PINS

S-LB

LLD

LHD

HLHIGH-ZD

S-UB DQ0 - DQ7DQ8 - DQ

OUT/DIN

D

OUT/DIN

HIGH-Z

OUT/DIN

15

4 Data Sheet

Stacked Chip (16M Flash & 4M SRAM) LRS1331

Table 3. Command Definition for Flash Memory

COMMAND

Read Array/Reset 1 Write XA FFH

Read Identifier Codes

Read Status Register 2 Write XA 70H Read XA SRD

Clear Status Register 1 Write XA 50H

Block Erase 2 Write BA 20H Write BA D0H 5

Full Chip Erase 2 Write XA 30H Write XA D0H

Word Write 2 Write WA 40H or 10H Write WA WD 5

Block Erase and Word Write Suspend

Block Erase and Write Resume

Set Block Lock-Bits 2 Write BA 60H Write BA 01H 6

Clear Block Lock-Bits 2 Write XA 60H Write XA D0H 6, 7

Set Permanent Lock-Bits 2 Write XA 60H Write XA F1H

NOTES:

1. Commands other than those shown in table are reserved by SHARP for future device implementations and should not be used.

2. BUS operations are defined in Table 2.

3. XA = Any valid address within the device; IA = Identifier code address; BA = Address within the block being erased; WA = Address of memory location to be written; SRD = Data read from status register; WD = Data to be written at location WA. Data is latched on the rising edge of F-WE ID = Data read from identifier codes.

4. See Table 4 for Identifier Codes.

5. See Table 5 for Write Protection Alternatives.

6. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands cannot be done.

7. The clear block lock-bits operation simultaneously clears all block lock-bits.

BUS CYCLES

REQUIRED

≥

2 Write XA 90H Read IA ID 4

1WriteXAB0H 5

1WriteXAD0H 5

or F-CE (whichever goes HIGH first);

OPERATION

FIRST BUS CYCLE SECOND BUS CYCLE

2

ADDRESS

3

DATA

3

OPERATION2ADDRESS3DATA

1

NOTES

3

Table 4. Identifier Codes

CODES ADDRESS (A0 - A19) DATA (DQ0 - DQ7)1NOTES

Manufacture Code 00000H B0H

Device Code 00001H E9H

Block Lock Configuration

Permanent Lock Configuration

NOTES:

- DQ15 outputs 00H in word mode. DQ1 - DQ7 are reserved for future use.

1. DQ

8

2. BA selects the specific block lock configuration code to be read. See Figure 3 for the device identifier code memory map.

Block is Unlocked BA + 2 DQ

Block is Locked BA + 2 DQ

Device is Unlocked 00003H DQ

Device is Locked 00003H DQ

= 0 2

0

= 1 2

0

= 0

0

= 1

0

Data Sheet 5

LRS1331 Stacked Chip (16M Flash & 4M SRAM)

Table 5. Write Protection Alternatives

OPERATION F-V

Block Erase or Word Write

Full Chip Erase

Set Block Lock-Bit

Clear Block Lock-Bit

Set Permanent Lock-Bit

≤ V

> V

≤ V

> V

≤ V

> V

≤ V

> V

≤ V

> V

CCW

CCWLK

F-RP

PERMANENT

LOCK-BIT

XX XX

V

IL

V

IH

XXX

X

XX XX

V

IL

V

IH

XXX

XX

XX XX

V

IL

XXX

0XX

V

IH

1XX

XX XX

V

IL

XXX

0XX

V

IH

1XX

XX XX

V

IL

V

IH

XXX

BLOCK

LOCK-BIT

0

1

F-WP

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

All blocks locked

Two boot blocks locked

Block Erase and Word Write enabled

Block Erase and Word Write disabled

All blocks locked

All unlocked blocks are erased. Two boot blocks and locked blocks are not erased

All unlocked blocks are erased. Locked blocks are not erased

Set block lock-bit disabled

Set block lock-bit enabled

Set block lock-bit disabled

Clear block lock-bits disabled

Clear block lock-bits enabled

Clear block lock-bits disabled

Set permanent lock-bit disabled

Set permanent lock-bit enabled

EFFECT

6 Data Sheet

Stacked Chip (16M Flash & 4M SRAM) LRS1331

Table 6. Status Register Definition

WSMS BESS ECBLBS WBWSLBS VCCWS WBWSS DPS R

76543210

SR.7 = Write State Machine Status (WSMS)

1 = Ready 0 = Busy

SR.6 = Erase Suspend Status (BESS)

1 = Block Erase Suspended 0 = Block Erase in Progress/Completed

SR.5 = Erase and Clear Block Lock-Bits Status (

ECBLBS

)

1 = Error in Block Erase, Bank Erase or

Clear Block Lock-Bits

0 = Successful Block Erase, Bank Erase or

Clear Block Lock-Bits

SR.4 = Word/Byte Write and Set Lock-Bit Status (WBWSLBS)

1 = Error in Word/Byte Write or Set

Block/Permanent Lock-Bit

0 = Successful Word/Byte Write or Set

Block/Permanent Lock-Bit

SR.3 = V

1 = V 0 = V

Status (VCCWS)

CCW

LOW Detect, Operation Abort

CCW

Okay

CCW

SR.2 = Word/Byte Write Suspend Status (WBWSS)

1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed

NOTES:

1. Check SR.7 to determine block erase, bank erase, word/byte write or lock-bit configuration completion. SR.6 - SR.0 are invalid while SR.7 = 0.

2. If both SR.5 and SR.4 are ‘1’s after a block erase, bank erase or lock-bit configuration attempt, an improper command sequence was entered.

3. SR.3 does not provide a continuous indication of F-V The WSM interrogates and indicates the F-V block erase, bank erase, word/byte write or lock-bit configuration command sequences. SR.3 is not guaranteed to report accurate feedback only when F-V

4. SR.1 does not provide a continuous indication of permanent and block lock-bit and F-WP nent lock-bit, block lock-bit and F-WP erase, word/byte write or lock-bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/

is VIL. Reading the block lock and permanent lock confi-

or F-WP gruation codes after writing the Read Identifier codes command indicates permanent and block lock-bit status..

5. SR.0 is reserved for future use and should be masked out when polling the status register.

≠ F-V

CCW

values. The WSM interrogates the perma-

.

CCWH

only after block erase, bank

level only after

CCW

level.

SR.1 = Device Protect Status (DPS)

1 = Block Lock-Bits, Permanent Lock-Bits

and/or F-WP

Lock Detected, Operation Abort

0 = Unlock

SR.0 = Reserved for future enhancements (R)

Data Sheet 7

LRS1331 Stacked Chip (16M Flash & 4M SRAM)

MEMORY MAP

[A0 - A19]

FFFFF

F8000

F7FFF

F0000

EFFFF

E8000

E7FFF

E0000

DFFFF

D8000

D7FFF

D0000

CFFFF

C8000

C7FFF

C0000

BFFFF B8000

B7FFF

B0000

AFFFF

A8000

A7FFF

A0000

9FFFF

98000

97FFF

90000

8FFFF

88000

87FFF

80000

7FFFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

07000

06FFF

06000

05FFF

05000

04FFF

04000

03FFF

03000

02FFF

02000

01FFF

01000

00FFF

00000

32K-WORD MAIN BLOCK

4K-WORD PARAMETER BOOT BLOCK

4K-WORD BOOT BLOCK

BOTTOM BOOT

Figure 3. Memory Map for Flash Memory

30

2932K-WORD MAIN BLOCK

2832K-WORD MAIN BLOCK

2732K-WORD MAIN BLOCK

2632K-WORD MAIN BLOCK

2532K-WORD MAIN BLOCK

2432K-WORD MAIN BLOCK

2332K-WORD MAIN BLOCK

2232K-WORD MAIN BLOCK

2132K-WORD MAIN BLOCK

2032K-WORD MAIN BLOCK

1932K-WORD MAIN BLOCK

18 32K-WORD MAIN BLOCK

1732K-WORD MAIN BLOCK

1632K-WORD MAIN BLOCK

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

5

4

3

2

1

0

1

0

LRS1331-3

8 Data Sheet

Sharp LRS1331 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual