Sharp LRS13023 Datasheet

PRODUCT SPECIFICATIONS

Integrated Circuits Group

LRS1302

Stacked Chip

8M Flash and 1M SRAM

(Model No.: LRS13023)

Spec No.: EL116039

Issue Date: June 11, 1999

SHARP

Handle this document carefully for it contains material protected by international

without the express written permission of the company.

When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.

(1)

LRS13023

The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment

listed in Paragraph (2). even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3).

- Office electronics * Instrumentation and measuring equipment

- Machine tools

- Audiovisual equipment

- Home appliances * Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following

equipment which demands high reliability, should first contact a sales

representative of the company and then accept responsibility for incorporating into the design fail-sale operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.

* Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment

* Mainframe computers

- Traffic control systems * Gas leak detectors and automatic cutoff devices

- Rescue and security equipment * Other safety devices and safety equipment,etc.

(3) Do not use the products covered herein for the following equipment which

demands extremely high performance in terms of functionality, reliability, or accuracy.

- Aerospace equipment

- Communications equipment for trunk lines

- Control equipment for the nuclear power industry

- Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the

above three Paragraphs to a sales representative of the company.

Please direct all queries regarding the products covered herein to a sales representative of the company.

SHARP

LRS13023

Part 1 Overview

l.Description

The LRS1302 is a combination memory organized as

memory and

It is fabricated using silicon-gate CMOS process technology.

Features OAccess Time

Flashmemoryaccesstime SRAM access time

OOpemtingcurrent

Flash memory Read

SRAM

131,072X8

Byte write Block erase

operatin%

bit static RAM in one package.

- * * *

. . . .

- - * *

1448,576 X 8

130 nsMax.

70 nsMax.

12 mAMax. (t&ti2OOns) 57 r&Max. 37 mAMax.

25 mA Max. hcxJz.=2=)

bit flash

ostandbycurrent

Flash memory

Sk4M

(Total standby curnat is the summation of Flash memory’s standby current and SRAM’s one.)

OPower supply

OSRAM data retention voltage

OOperating temperature OFully static operation oThree-state output

ONot designed or rated as radiation hardened 040 pin TSOP ( TSOP~O-p-0819 plastic package

OFlash memory has P-type bulk silicon, and SRAh4 has N-type bulk silicon.

. . . .

20 @ Max. (F-EZF-Vc,0.2V,

EbO.2V, F-V&O.2V)

30 pA Max. (S-EZS-Vc,0.2V)

0.7 @ Typ. (T,=25”c, S-V,-3V, S-CErs-Vcc-0.2V)

2.7V to 3.6V @ead/SRAM write)

2.7~ to 3.6~ @LASH erase/write)(T,=O to 85c

2.0 V Min.

40°C to +85”c

The contents described in Part 1 take first priority over Part 2 and Part 3.

SHARP

LRS13023

Part 1 Overview

l.Description

The LRS1302 is a combination memory organized as memory and It is fabricated using silicon-gate CMOS process technology.

OAccess Time

Flashmemoryaccesstime SRAM access time

OOpemtingcment

Flash memory Read

SRAM Operating

131,072X8

Byte write

Block erase

bit static RAM in one package.

- * * *

. . . .

- - * *

1,048,576X 8 bit flash

130 nsMax.

70 nsMax.

12 mAMax. (t&ti2Oons> 57 mAMax. 37 mAMax.

25 mAMax.

hcxJ&oons)

ostandbycurrent

Flash memory

Sk4M

(Total standby current is the summation of Flash memory’s standby current and SRAM’s one.)

3Power supply

3SRAM data retention voltage 3Operating temperature IFully static operation 3Three-state output JNot designed or rated as radiation hardened

240 Pin TSOP ( TSOP~O-p-0819 plastic package IFlash memory has P-type bulk silicon, and SRAM has N-type bulk silicon.

. . . .

20 pA Max. (F-EZF-Vc,0.2V,

EbO.2V, F-V&O.2V)

30 @ Max. (S-=ZS-Vc,0.2V)

0.7 @ Typ. (T,=25”c, S-V,-3V, s-CEZS-vcc-0.2v)

2.7V to 3.6V @ead/SPAM write)

2.7~ to 3.6~ (FLASH erase/write>Cr,=O to 85c

2.0 V Min.

40°C to +85”c

The contents described in Part 1 take first priority over Part 2 and Part 3.

SHARI=

LRS13023

3. Notes This product is a stacked TSOP package that a 1,048,576X 8 bit Flash Memory and a

13 1,072 X 8 bit SRAM are assembled into.

POWER SUPPLY AND CHIP ENABLE OF FLASH MEMORY AND SRAM

It is forbidden that both F-E and S-E should be LOW simultaneously. If the two memories are active

together, possibly they may not operate normally by interference noises or data collision on I/O bus.

Both F-V, and S-V, are needed to be applied by the recommended supply voltage at the same time except

SRAM data retention mode.

SUPPLY POWER

Maximum difference (between F-V,

SRAM DATA RETENTION

SRAM data retention is capable in three ways as below. SRAM power switching between a system

battery and a backup battery needs careful

voltage from

supply voltage or of control si{nals (F-B, F-?% and RP).

CASE I: FLASH MEMORY IS IN STANDBY MODE. (F-Vcc=2.7V to 3.6V)

* SRAM inputs and input/outputs except S-mare needed to be applied with voltages in the range of

-0.3V to S-Vcc+O.3V or to be open(High-Z).

* Flash Memory inputs and input/outputs except F-eand Gare needed to be applied with voltages in

the range of -0.3V to S-V,,+O.3V or to be open(High-Z).

failing

lower han

2.OV by a Flash Memory peak current caused by transition of Flash Memory

and S-V, ) of the voltage is less than -0.3V.

device

decoupling from Flash Memory to prevent SRAM

supply

CASE 2: FLASH MEMORY IS IN DEEP POWER DOWN MODE. (F-Vcc=2.7V to 3.6V)

* SRAM inputs and input/outputs except S-mare needed to be applied wilh voltages in the range of

-0.3V to S-V,c+O.3V or to be open.

* Flash Memory inputs and input/outputs except mare needed to be applied with voltages in the range of

-0.3V to S-Vc,+O.3V or to be open(High-Z). RP is needed to be at the same level as F-V,, or to be open.

CASE 3: FLASH MEMORY POWER SUPPLY IS TURNED OFF. (F-VcpOV)

* Fix- LOW level before turning off Flash memory power supply. * SRAM inputs and input/outputs except S-mare needed to be applied with voltages in the range of

-0.3V to S-V,c+O.3V or to be open(High-Z).

- Flash Memory inputs and input/outputs except mare needed to be at GND or to be open(High-Z).

POWER UP SEQUENCE

When turning on Flash memory power supply, keep i@ LOW. After F-V,, reaches over 2.7V, keep RP

LOW for more than 1OOnsec.

DEVICE DECOUPLING

The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is

in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals.

The contents described in Part 1 take first priority over Part 2 and Part 3.

SHARP

LRS13023

4.Truth table(* 1.3) F-a F-m F-m RP S-a S-m S-m Address Mode I/O, toI/O, Current Note

LLHHHXXX Flash read output LHHHHXXX Flash read High-Z I,, *4

LHLHHXXX Flash write Input HXXXLLHX SRAM read output Ice HXXXLHHX sR4M read High-Z I,,

HXXXLXLX SRAM write Input I HXXHHXXX Standby High-Z Iss HXXLHXXX Deep power down High-Z Isa *4

Notes:

* 1. Do not make F-C? and S-C8 “LOW” level at the samc,limc. * 2. Reffcr to DC Character&tics. When F-V&V,,.,.,, memory contents can be read, but not altered. * 3. X can be V,,, or V,,, for control pins and addresses, and V,,nx or VI,,,,, for F-V,,,,. See DC Characteristics

for V,,,k and V,,.,, voltages.

* 4. i@ at GND f0.2V ensures the lowest deep power-down current.

* 5. Command writes involving block erase, write, or lock-bit configuration are reliably executed when

F-V,,=V,, and F-V,@,. Block erase, byte write, or lock-bit conliguration with Vcc<3.0V or

V,,, <m< V,,,, produce spurious results and should not be attempted. * 6. Reffer to Part 2 Section 3 Table 4 for valid DIN during a write operation. $7. Do not

use in

a timing that both F-mand F-WE is “LOW” level.

*2,7

*5,6,7

5. Block Diagram

F-n i

F-GE / >

F-m j

RP ;

F-A,, to F-A,, !

&to&, ;

S-TE / S-FE

s-m ;

F-V, F-V,,

____________________----------.------------------------------------------

w v

> >

1,048,576 X 8

131,072X8

bit Flash memory

bit SR4M

e- ; e

The contents described in Part 1 take first priority over Part 2 and Part 3.

SHARP

LRS13023

6.Absolute Maximum Ratings

Notes) * 8.The maximum applicable voltage on any pin with respect to GND.

* 9. Except Vrp,

* 10. Except @. * 11. -2.OV undershoot is allowed when the pulse width is less than 20nsec. * 12. +14.OV overshoot is allowed when the pulse width is less than 2Onscc.

7.Recommended DC Operating Conditions CT,= -40°C to +85”c )

Parameter Symbol Min. Supply voltage Input voltage

vc-2 V”, VU.

v,,,,(* 14)

2.7 3.0 3.6

2.2 V,,+O.3 (*15) V

-0.3 (*13:

11.4 12.6

TYP.

Max. Unit

0.4

Notes) * 13. -2.OV undershoot is allowed when the pulse width is less than 2Onsec.

* 14. This voltage is applicable toi@ Pin only. * 15. V, is the lower one of S-V, and F-V,,.

8.Pin Capacitance (T,=25”c, f=lMHz)

Parameter Symbol Condition Input capacitance I/O capacitance

Note) * 16. Sampled but not 100% tested

Gi CIA3

v,=ov v,=ov

Min. TYP.

Max. Unit

PF PF

*16

The contents described in Part 1 take first priority over Part 2 and Part 3.

SHARP

LRS13023

Part2 Flash memory

CONTENTS

PAGE

.. INTRODUCTION

1.1 New Features.. ...........................................................

1.2 Product Overview

!. PRINCIPLES OF OPERATION

2.1 Data Protection

I.BUS OPERATION.. ........................................... .

3.1 Read

3.2 Output Disable

3.3 Standby

3.4 Deep Power-Down

3.5 Read Identifier Codes Operation

3.6 Write ...........................................................................

I. COMMAND DEFINITIONS

4.1 Read Array Command

4.2 Read Identifier Codes Command .........................

4.3 Read Status Register Command..

4.4 Clear Status Register

4.5 Block Erase Command

4.6 Byte Write Command ..............................................

4.7 Block Erase Suspend Command

4.8 Byte Write Suspend Command.. ...........................

4.9 Set Block and Master Lock-Bit Commands

........................................................................... 13

...................................................................... 13

........................................................... 9

......................................................

...................................

.........................................................

............

........................................

...................................................

.......................................

............................................ 17

Command

............................................ 17

;............... 13

........................... 14

..........................

...........................

.........

-9 9

.17 .17

.17

.18 .19

-19

PAGE

4.10 Clear Block Lock-Bits

5. DESIGN CONSIDERATIONS .................................... 28

5.1 Three-Line Output Control .................................... 28

5.2 Power Supply

5.3 V,, Trace on Printed Circuit Boards.. ................... 28

5.4 V,,, V,,, i?is Transitions.. ......................................

5.5 Power-Up/Down Protection.. ................................ 29

5.6 Power Dissipation.. .................................................. 29

6.ELECTRICAL SPECIFICATIONS ............................... 30

6 1 Absolute Maximum

6.2 Operating Conditions..

6.2.1 AC Input/Output Test Conditions.. ................ 31

6.2.2 DC Characteristics .............................................

6.2.3 AC Characteristics - Read-Only Operations

6.2.4 AC Characteristics - Write Operations..

6.2.5 Alternative a-Controlled Writes ................... 38

6.2.6 Reset Operations ................................................ 40

6.2.7 Block Erase, Byte Write and Lock-Bit

Configuration Performance.. ...........................

Decoupling.. .................................... 28

Command.. ....................... 20

Ratings.. ................................. 30

............................................ 30

... 34

.36

.........

SHARP

LRS13023

Part2 Flash memory

CONTENTS

PAGE

.. INTRODUCTION

1.1 New Features.. ...........................................................

1.2 Product Overview

!. PRINCIPLES OF OPERATION

2.1 Data Protection

I.BUS OPERATION.. ........................................... . ............ 13

3.1 Read

3.2 Output Disable

3.3 Standby

3.4 Deep Power-Down

3.5 Read Identifier Codes Operation

3.6 Write ...........................................................................

I. COMMAND DEFINITIONS

4.1 Read Array Command

4.2 Read Identifier

4.3 Read Status Register Command..

4.4 Clear Status Register Command

4.5 Block Erase Command

4.6 Byte Write Command

4.7 Block Erase Suspend

4.8 Byte Write Suspend

4.9 Set Block and Master Lock-Bit Commands

........................................................................... 13

...................................................................... 13

...........................................................

......................................................

...................................

.........................................................

........................................

...................................................

....................................... 14

............................................ 17

Codes Command

............................................ 17

.............................................. 18

Command

Command..

;............... 13

........................... 14

.........................

..........................

...........................

.........

-9 9

12 12

.17 .17 .17

.18 .19

-19

PAGE

4.10 Clear Block Lock-Bits Command.. ....................... 20

.........

.36

5. DESIGN CONSIDERATIONS ....................................

5.1 Three-Line Output Control .................................... 28

5.2 Power Supply

5.3 V,, Trace on Printed

5.4 V,,, V,,, i?is Transitions.. ...................................... 29

5.5 Power-Up/Down

5.6 Power Dissipation..

6.ELECTRICAL SPECIFICATIONS ............................... 30

6 1 Absolute Maximum

6.2 Operating Conditions..

6.2.1 AC Input/Output

6.2.2 DC Characteristics ............................................. 32

6.2.3 AC Characteristics - Read-Only Operations ... 34

6.2.4 AC Characteristics - Write Operations..

6.2.5 Alternative a-Controlled Writes ................... 38

6.2.6 Reset Operations ................................................ 40

6.2.7 Block Erase, Byte Write and Lock-Bit

Configuration Performance.. ........................... 41

Decoupling.. .................................... 28

Circuit Boards.. ................... 28

Protection.. ................................ 29

.................................................. 29

Ratings.. ................................. 30

............................................ 30

Test Conditions.. ................ 31

SHARP

LRS13023

INTRODUCTION

his datasheet contains LRS1302 specifications. iection 1 provides a flash memory overview. Sections !, 3,4, and 5 describe the memory organization and unctiordity. Section 6 covers electrical specifications.

..l New Features The LRS1302 SmartVoltage Flash memory maintains

)ackwards-compatibility with SHARP’s 28F008SA. Cey enhancements over the 28F008SA include:

SmartVoltage Technology *Enhanced Suspend Capabilities Jn-System Block Locking

30th devices share a compatible, status register, and oftware command set. These similarities enable a clean upgrade from the 28FOO8SA to LRS1302. When upgrading, it is important to note the following iifferences:

-Because of new feature support, the two devices have different device codes. This allows for software optimization.

.VPpLK has been lowered from 6SV to 1.5V to

support 2.7V-3.6V block erase, byte write, and lock-bit configuration operations. Designs switch VPP off during read operations should make sure that the VP, voltage transitions to GND.

*To take advantage of SmartVoltage technology,

allow VP, connection to 2.7V-3.6V.

that

SmartVoltage technology provides a choice of Vcc and VP, combinations, as shown in Table 1, to meet system performance and power expectations. V, at 2.7V to

3.6V eliminates the need for a separate 12V converter. In addition to flexible erase and program voltages, the dedicated VPP pm gives complete data protection when VP, I VP,,.

Table 1. V,, and VP, Voltage Combinations Offered

;_.

2,7V to 3.6V(‘l) 2.7V to 3.6V

NOTE’ ’

‘1. FLASH Erase/Write(T*=O”C to 85°C) Internal Vcc and

automatically configures the device for optimized read and write operations.

A Command User Interface (CUT) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUT initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for

block erase, byte write, and lock-bit configuration

operations. A block erase operation erases one of the device’s

64Kbyte blocks typically within 1.8 second independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

by SmartVoltage Technology

Vcc Voltage VPP Voltage

detection Circuitry

I.2 Product Overview The LRS1302 is a high-performance &Mbit

;martVoltage Flash memory organized as 1 Mbyte of 8 >its. The 1 Mbyte of data is arranged in sixteen &Kbyte blocks which are individually erasable, o&able, and unlockable in-system. The memory map s shown in Figure 2.

Writing memory data is performed in byte increments typically within 17 us. Byte write suspend mode

enables the system to read data or execute code from any other flash memory array location.

SHARP

LRS13023

~Individual block locking uses a combination of bits, ‘sixteen block lock-bits and a master lock-bit, to lock land unlock blocks. Block lock-bits gate block erase and ‘byte write operations, while the master lock-bit gates ~block lock-bit modification. Lock-bit configuration loperations (Set Block Lock-Bit, Set Master Lock-Bit,

and Clear Block Lock-Bits commands) set and cleared lock-bits.

The status register indicates when the WSM’s block

erase, byte write, or lock-bit configuration operation is finished.

The access time is 130 ns (tAvQv) over the commercial

temperature range (-40°C to +BS’C) and V,, supply

voltage range of 2.7V-3.6V.

The Automatic Power Savings (AI%) feature substantially reduces active current when the device is in static mode (addresses not switching).

When a and RF pins are at V,,, the I,, CMOS standby mode is enabled. When the RP pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHqv) is required from RP switching high until outputs are valid. Likewise, the device has a wake time (tpHEL) from m-high until writes to the CUI are recognized. With RP at GND, the WSM is reset and the status register is cleared.

4 x :

occcdc.r .

64KByle

BlOCb

Figure 1. Block Diagram

SHARP

Svm

f40-419

I/O&O~

_. _-

Vcc

GND

rote: V,-,

LRS13023

Table 2. Pin Descriptions

Type

INPUT

INPUT/

OUTPUT

INPUT

SUPPLY

SUPPLY GROUND: Do not float any ground pins.

,P, n, m and WE mean F-V,,, F-V,,, F-a, Fa and F-WE.

ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs

data during memory array, status register, and identifier code read cycles. Data pins

float to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle. CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. a-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. m-high enables normal operation. When driven low, p inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. Ris at V,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is

set. RP=V,,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with V,,<RI’cV& produce spurious results and should not be attempted. OUTPUT ENABLE: Gates the device’s outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses latched BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes, or configuring lock-bits. With VPP5VPPLK, memory

contents cannot

invalid VP, (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLYDo not float any power pins. With VCCIVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid Vcc voltage (see DC Characteristics) produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with V,,<3.OV are not supported.

the rising edge of the WE pulse.

be altered. Block erase, byte write, and lock-bit configuration with an

Name and Function

and

data are

SHARI=

2 PRINCIPLES OF OPERATION

LRS13023

The LRS1302 SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings.

After initial device power-up or return from deep power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the VP, voltage. High voltage on V,, enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contents-block erase, byte write, Lock-bit configuration, status, and identifier codes-are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data.

Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location.

Aoooo 9FFFF

9oMw)

SFFFF

8oooO

7FFFF

7owo

6FFFF

t5wlo

SFFFF

2Izzz

OFFFF

ooom

2.1 Data Protection Depending on the application, the system designer

may choose to make the V,, power supply switchable

(available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to V,,,. design practice and encourages optimization of the processor-memory interface.

64Kbyte Block

64-Kbyte Block

64Kbyte Block 4 1

64Kbyte Block 64Kbyte Block 0

Figure 2. Memory Map

The device accommodates either

15 I

10 I

SHARI=

LRS13023

When VPPIVPPLK, memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VP+. All write functions are disabled when V,, VLKO or when RP is at Vl,. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations.

3 BUS OPERATION The local CPU reads and writes flash memory

in-system. All bus cycles to or from the flash memory :onform to standard microprocessor bus cycles.

3.1 Read Information can be read from any block, identifier

:odes, or status register independent of the VP, voltage. RP can be at either Vl, or V,,.

The first task is to write the appropriate read mode :ommand (Read Array, Read Identifier Codes, or Read status Register) to the CUI. Upon initial device Tower-up or after exit from deep power-down mode, :he device automatically resets to read array mode. Four control pins dictate the data flow in and out of :he component: CE, OE, WE, and m. CE and m must >e driven active to obtain data at the outputs. m is the device selection control, and when active enables the ielected memory device. m is the data output

I/O&O,) control and when active drives the ielected memory data onto the I/O bus. WE must be it VI, and m must be at V,, or V,,. Figure 12 llustrates a read cycle.

1.2 Output Disable Mith 0lY at a logic-high level (Vt,), the device outputs

Ire disabled. Output pins I/0,-1/0, are placed in a high-impedance state.

is below the write lockout voltage

---

3.3 Standby n at a logic-high level (V,,) places the device in

standby mode which substantially reduces device power consumption. I/O&O, outputs are placed in a high-impedance state independent of OE. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and

consuming active power until the operation completes.

3.4 Deep Power-Down i?Ij at V,, initiates the deep power-down mode. In read modes, m-low deselects the memory, places

output drivers in a high-impedance state and turns off

all internal circuits. RP must be held low for a minimum of 100 ns. Time tPHQv is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase, byte write, or lock-bit configuration modes, m-low will abort the operation. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tpHWL is required after Rp goes to logic-high (VI,) before another command can be written.

As with any automated device, it is important to assert Rp during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs

with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the i?l? input. In this application, Rp is controlled by

the same m signal that resets the system CPU.

SHARP

LRS13023

1.5 Read Identifier Codes Operation The read identifier codes operation outputs the

nanufacturer code, device code, block lock :onfiguration codes for each block, and the master ock configuration code (see Figure 3). Using the nanufacturer and device codes, the system CPU can u,rtomatically match the device with its proper algorithms. The block lock and master lock :onfiguration codes identify locked and unlocked ~1ock.s and master lock-bit setting.

Reserved for

FOO04 FOOO3

FOOOZ 1

FOOOl

FOOOO

Future Implementation

Block 15 Lock Configuration Code

Reserved for

Future Implementation

Block 1

(Blocks 2 through 14) ’

3.6 Write Writing commands to the CUI enable reading of

device data and identifier codes. They also control inspection and clearing of the status register. When V,--=Vccl and VPP=VPPH, the CUI additionally controls block erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits co

mmand requires

the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when WE and a are active. The address and data needed to execute a command-are latched on the rising edge of WE or CE (whichever goes high first& Stand,ard microprocessor write

timings are used. jQures:13 and 14 illustrate WE and

m-controlled write operahons.

IFFFF

Reserved for

looo4 1ooo3

Future Implementation

Block 1 Lock Configuration Code

OFFFF

Reserved for

Future Implementation

oooo4

oooo3 moo2

ooml

Master Lock Configuration Code

------------------------------------. Block 0 Lock Configuration Code

~~~~~~~~----__-__---________________(

--------_-__________----------------.

Device Code

Manufacturer Code

Block

Figure 3. Device Identifier Code Memory Map

4 COMMAND D&INITlON~ When the VP, voftage I VPPLK, Read operations from

the status register, identifier codes, or blocks are enabled. Placing VP,, on.Vpp enables successful block erase, byte write and lock-bit configuration operations.

Device operations are selected by writing specific commands into the CUI. Table 4 defines these

commands.

SHARP

LRS13023 15

NOTES:

1. Refer to DC Characteristics. When VPPIVPP,,

2. X can be VI, or V,, for control pins and addresses, and VP,, or VP,, for VP,. See DC Characteristics for VW, and V,,, voltages.

3. i@ at GND&.2V ensures the lowest deep power-down current.

4. See Section 4.2 for read identifier code data.

5. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPp=VppH and Vcc=VccIU~=O to 85 “c) results and should not be attempted.

6. Refer to Table 4 for valid h during a write operation.

7. Don’t use the timing both m and m are VIM

. Block erase, byte write, or lock-bit configuration with V,<mkV, produce spurious

memory contents can be read, but not altered.

SHARI=

LRS13023

Table 4. Commanc - - ___._. ~_ _

RIW f-vr1c.c

Command Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register 1 Block Erase 2 5 Byte Write

Req’d . Notes

Ope# ) Addrc2) 1 DataQ) Oper(l) 1 Addrt2) 1 Datac3)

Write X

4 Write X 90H

Write X 70H

Write X 5UH Write BA 20H Write WA 40H

I I I I

Block Erase and Byte Write

Suspend

Block Erase and Byte Write Resume Set Block Lock-Bit 2 7 Write BA 60H Set Master Lock-Bit 2 Clear Block Lock-Bits 2 8 Write

NOTES:

1. BUS operations are defined in Table 3. ”

2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 3. BA=Address within the block being erased or locked.

WA=Address of memory location to be written.

3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE or CE (whichever goes high first). ID=Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Section 4.2 for read identifier code data.

5. If the block is locked, i?i? must be at V,, erase or byte write to a locked block while m is VII+

6. Either 40H or 10H are recognized by the WSM as the byte write setup.

7. If the master lock-bit is set, m must be at V,, If the master lock-bit is not set, a biock lock-bit can be set while i?is is V,,.

8. If the master lock-bit is set, RP must be at V,, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RR 1s Vl,.

9. Commands other than those shown above are reserved by SHARP for future device implementa lions and should not be used.

5 Write

7 Write X 60H

to enable block erase or byte write operations. Attempts to issue a block

to set a block lock-bit. RP must be at V,, to set the master lock-bit.

1 Definitions(9)

Fist Bus Cycle Second Bus Cycle

---- I

FFH

Read. IA ID

_. ----

or I

10H

X BOH X

X 60H Write X DOH

DOH

Read X

Write BA

Write WA WD

I I

Write BA OlH Write X FlH

SRD DOH

SHARP

LRS13023

:.l Read Array Command Jpon initial device power-up and after exit from deep

jowerdown mode, the device defaults to read array node. This operation is also initiated by writing the lead Array command. The device remains enabled for eads until another command is written. Once the nternal WSM has started a block erase, byte write or sck-bit configuration, the device will not recognize he Read Array command until the WSM completes its lperation unless the WSM is suspended via an Erase luspend or Byte Write Suspend command. The Read bray command functions independently of the VP, poltage and m can be V,, or V,,.

,.2 Read Identifier Codes Command ‘he identifier code operation is initiated by writing the

Lead Identifier Codes command. Following the ommand write, read cycles from addresses shown in ‘igure 3 retrieve the manufacturer, device, block lock onfigura tion and master lock configuration codes (see ‘able 5 for identifier code values). To terminate the Nperation, write another valid command. Like the Lead Array command, the Read Identifier Codes ommand functions independently of the VP, voltage

nd RP can be V,, or V,,. Following the Read dentifier Codes command, the following information an be read:

Table 5. Identifier Codes

4.3 Read Status Register Command

The status register may be read to determine when a

block erase, byte write, or, lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE or CE, whichever occurs. OE or

iZ must toggle to V,,

the status register latch. The Read Status Register command functions independently of the VP, voltage.

Rp can be V,, or V,,.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to

“1”s by the WSM and can only be reset by the Clear

Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurre during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VP, Voltage. RP can be V,, or V,,. This command is not functional during block erase or byte write suspend modes.

before further reads to update

Block Lock Configuration .Block is Unlocked

*Block is Locked

-Reserved for Future Use Master Lock Configuration

SDevice is Unlocked ,Device is Locked ,Reserved for Future Use IOTE: . X selects the specific block lock configuration code

to be read. See Figure’3 for the device identifier

code memory map.

4.5 Block Erase Command Erase is executed one block at a time and initiated by a

two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase

changes all block data to FFH). Block preconditioning,

erase, and verify are handled internally by the WSM

(invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 4). The CPU can detect block erase completion by analyzing status register bit SR.7.

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Sharp LRS13023 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual