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LK520D3LZ97
Specification
37 pgs2.28 Mb0

SHARP LK520D3LZ97 Specification

26
LD- 19Z08-1
1. Application
This specification applies to the color 52.0” TFT-LCD module LK520D3LZ97.
* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,
automobiles, etc.), rescue and security equipment and various safety related equipment which require higher reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant system design should be taken.
* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for life support.
* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with
the instructions and the precautions specified in these specification.
* Contact and consult with a SHARP sales representative for any questions about this device.
2. Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit, inverter circuit and back light
system etc. Graphics and texts can be displayed on a 1920×RGB×1080 dots panel with using LVDS (L
This module also includes the DC/AC inverter to drive the CCFT. (+24V of DC supply voltage)
And in order to improve the response time of LCD, this module applies the Over Shoot driving (O/S driving) technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal according to a pre-fixed process as an image signal of the present frame when a difference is found between image signal of the previous frame and that of the current frame after comparing them.
With this technology, image signals can be set so that liquid crystal response completes within one frame. As a result, motion blur reduces and clearer display performance can be realized.
This LCD module also adopts Double Frame Rate driving method.
With combination of these technologies, motion blur can be reduced and clearer display performance can be realized.
ow Voltage Differential Signaling) to interface, +12V of DC supply voltages.
one billion
colors by
3. Mechanical Specifications
Parameter Specifications Unit
Display size
Active area 1152.0(H) x 648.0 (V) mm
Pixel Format
Pixel pitch 0.600(H) x 0.600 (V) mm Pixel configuration R, G, B vertical stripe Display mode Normally black Unit Outline Dimensions (*1) 1219.0(W) x 706.7(H) x 64.6(D) mm Mass
Surface treatment
(*1) Outline dimensions are shown in Fig.1 (excluding protruding portion)
132.174 （Diagonal）
52.0 （Diagonal）
1920(H) x 1080(V) （1pixel = R + G + B dot）
21.0 ±1.0 Anti glare Hard coating: 2H
cm
inch
pixel
kg
4. Input Terminals
4.1. TFT panel driving
CN1 (Interface signals and +12V DC power supply) (Shown in Fig.1)
Using connector : FI-RE51S-HF (Japan Aviation Electronics Ind., Ltd.)
Mating connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind., Ltd.)
Mating LVDS transmitter : THC63LVD1023 or equivalent device
Pin No. Symbol Function Remark
1 2 3 4 5
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
GND Reserved It is required to set non-connection(OPEN) Reserved It is required to set non-connection(OPEN) Reserved It is required to set non-connection(OPEN)
FRAME
O/S set O/S operation setting H:O/S_ON, L:O/S_OFF [Note 3] Pull up 3.3V
SELLVDS
Reserved Reserved Reserved
GND
AIN0- Aport (-)LVDS CH0 differential data input
AIN0+ Aport (+)LVDS CH0 differential data input
AIN1- Aport (-)LVDS CH1 differential data input
AIN1+ Aport (+)LVDS CH1 differential data input
AIN2- Aport (-)LVDS CH2 differential data input
AIN2+ Aport (+)LVDS CH2 differential data input
GND
ACK- Aport LVDS Clock signal(-)
ACK+ Aport LVDS Clock signal(+)
GND
AIN3- Aport (-)LVDS CH3 differential data input
AIN3+ Aport (+)LVDS CH3 differential data input
AIN4- Aport (-)LVDS CH4 differential data input
AIN4+ Aport (+)LVDS CH4 differential data input
GND
GND
BIN0- Bport (-)LVDS CH0 differential data input
BIN0+ Bport (+)LVDS CH0 differential data input
BIN1- Bport (-)LVDS CH1 differential data input
BIN1+ Bport (+)LVDS CH1 differential data input
BIN2- Bport (-)LVDS CH2 differential data input
BIN2+ Bport (+)LVDS CH2 differential data input
GND
BCK- Bport LVDS Clock signal(-)
BCK+ Bport LVDS Clock signal(+)
GND
BIN3- Bport (-)LVDS CH3 differential data input
BIN3+ Bport (+)LVDS CH3 differential data input
BIN4- Bport (-)LVDS CH4 differential data input
BIN4+ Bport (+)LVDS CH4 differential data input
GND
GND
GND
Frame frequency setting 1:60Hz 0:50Hz
Select LVDS data order [Note1,2] It is required to set non-connection(OPEN) It is required to set non-connection(OPEN) It is required to set non-connection(OPEN)
[Note1]
Pull up 3.3V Pull up 3.3V Pull up 3.3V
Pull down : (GND)
Pull down : (GND) Pull down : (GND) Pull down : (GND) Pull down : (GND)
LD- 19Z08-2 45 46 47 48 49 50 51
GND GND VCC +12V Power Supply VCC +12V Power Supply VCC +12V Power Supply VCC +12V Power Supply VCC +12V Power Supply
CN2 (Interface signals) (Shown in Fig1)
Using connector : FI-RE41S-HF (Japan Aviation Electronics Ind., Ltd.)
Mating connector : FI-RE41HL, FI-RE41CL (Japan Aviation Electronics Ind., Ltd.)
Pin No. Symbol Function Remark
1 2 3 4 5 6 Reserved 7 Reserved 8 Reserved
9 GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Reserved (VCC) (+12V Power Supply) Reserved (VCC) (+12V Power Supply) Reserved (VCC) (+12V Power Supply) Reserved (VCC) (+12V Power Supply)
Reserved
CIN0- Cport (-)LVDS CH0 differential data input
CIN0+ Cport (+)LVDS CH0 differential data input
CIN1- Cport (-)LVDS CH1 differential data input
CIN1+ Cport (+)LVDS CH1 differential data input
CIN2- Cport (-)LVDS CH2 differential data input
CIN2+ Cport (+)LVDS CH2 differential data input
GND
CCK- Cport LVDS Clock signal(-)
CCK+ Cport LVDS Clock signal(+)
GND
CIN3- Cport (-)LVDS CH3 differential data input
CIN3+ Cport (+)LVDS CH3 differential data input
CIN4- Cport (-)LVDS CH4 differential data input
CIN4+ Cport (+)LVDS CH4 differential data input
GND GND
DIN0- Dport (-)LVDS CH0 differential data input
DIN0+ Dport (+)LVDS CH0 differential data input
DIN1- Dport (-)LVDS CH1 differential data input
DIN1+ Dport (+)LVDS CH1 differential data input
DIN2- Dport (-)LVDS CH2 differential data input
DIN2+ Dport (+)LVDS CH2 differential data input
GND
DCK- Dport LVDS Clock signal(-)
DCK+ Dport LVDS Clock signal(+)
GND
DIN3- Dport (-)LVDS CH3 differential data input
DIN3+ Dport (+)LVDS CH3 differential data input
DIN4- Dport (-)LVDS CH4 differential data input
DIN4+ Dport (+)LVDS CH4 differential data input
GND GND
[Note] GND of a liquid crystal panel drive part has connected with a module chassis.
LD- 19Z08-3
[Note 1]The equivalent circuit figure of the terminal
LD- 19Z08-4
Te rm in al
[Note 2] LVDS Data order
Data L(GND) or Open
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 NA NA TC5 NA NA TC6 DE(*) DE(*) TD0 TD1 TD2 TD3 TD4 TD5 TD6
TE0
TE1
TE2
TE3
TE4
TE5
TE6
NA: Not Available (*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE signal during operation at ”High”.
100Ω
SELLVDS
[VESA]
R0(LSB) R1 R2 R3 R4 R5 G0(LSB) G1 G2 G3 G4 G5 B0(LSB) B1 B2 B3 B4 B5
R6 R7 G6 G7 B6 B7
N/A
R8 R9(MSB) G8 G9(MSB) B8 B9(MSB)
N/A
2.0KΩ
H(3.3V)
[JEIDA] R4 R5 R6 R7 R8 R9(MSB) G4 G5 G6 G7 G8 G9(MSB) B4 B5 B6 B7 B8 B9(MSB)
R2 R3 G2 G3 B2 B3 N/A R0(LSB) R1 G0(LSB) G1 B0(LSB) B1 N/A
–
,
–
–
,
–
SELLVDS= Low (GND) or OPEN
ACK+,BCK+ CCK+,DCK+
ACK– ,BCK– CCK– ,DCK–
AIN0+,BIN0+ CIN0+,DIN0+ AIN0
–,BIN0–
CIN0–,DIN0–
AIN1+,BIN1+ CIN1+,DIN1+ AIN1
–,BIN1–
CIN1–,DIN1–
AIN2+,BIN2+ CIN2+,DIN2+
–,BIN2–
AIN2 CIN2–,DIN2–
AIN3+,BIN3+ CIN3+,DIN3+ AIN3
–,BIN3–
CIN3–,DIN3–
AIN4+,BIN4+ CIN4+,DIN4+
–,BIN4–
AIN4 CIN4
DIN4
SELLVDS= High (3.3V)
ACK+,BCK+ CCK+,DCK+
ACK– ,BCK– CCK– ,DCK–
AIN0+,BIN0+ CIN0+,DIN0+ AIN0 CIN0–,DIN0–
AIN1+,BIN1+ CIN1+,DIN1+ AIN1 CIN1–,DIN1–
AIN2+,BIN2+ CIN2+,DIN2+ AIN2–,BIN2– CIN2–,DIN2–
AIN3+,BIN3+ CIN3+,DIN3+ AIN3–,BIN3– CIN3–,DIN3–
AIN4+,BIN4+ CIN4+,DIN4+ AIN4 CIN4
–,BIN0–
–,BIN1–
–,BIN4–
DIN4
DE: Display Enable, NA: Not Available (Fixed Low)
LD- 19Z08-5
1 cycle
G0 R5 R4 R3 R2 R1 R0 R0 R1 G0
B1 B0 G5 G4 G3 G2 G1 G1 G2 B1
DE
NA NA
B7 B6 G7 G6 R7 R6 R6 R7 NA NA
B9 B8 G9 G8 R9 R8 R8 R9 NA NA
B5 B4 B3 B2 B2 B3
DE
1 cycle
G4 R9 R8 R7 R6 R5 R4 R4 R5 G4
B5 B4 G9 G8 G7 G6 G5 G5 G6 B5
DE
NA NA
B3 B2 G3 G2 R3 R2 R2 R3 NA NA
B1 B0 G1 G0 R1 R0 R0 R1 NA NA
B9 B8 B7 B6 B6 B7
DE
V
[Note 3] The equivalent circuit figure of the terminal
Te rm in al
4.2. Interface block diagram CN1 side:
Contr oller
AR0 AR 9
∼
AG0 AG9
∼
AB0 AB9
∼
ENAB_A
Hsync _A Vsync _A
CLKA
BR0 ∼ BR9 BG0 ∼ BG9 BB0 ∼ BB9
ENAB_B
Hsync _B
Vsync _B
CLKB
(TV Side)
Port A
10
10
10
LVDS
↑
TTL
PLL
Port B
10
10
10
LVDS
↑
TTL
PLL
2.0KΩ
AIN0+( 13)
AIN0– (12)
AIN1+( 15)
AIN1– (14)
AIN2+( 17)
AIN2– (16)
AIN3+( 23)
AIN3– (22)
AIN4+( 25)
AIN4– (24)
ACK+(20)
ACK– (19)
BIN0+(29)
BIN0– (28)
BIN1+(31)
BIN1– (30)
BIN2+(33)
BIN2– (32)
BIN3+(39)
BIN3– (38)
BIN4+(41)
BIN4– (40)
BCK+(36)
BCK–(35)
3.3
LD- 19Z08-6
(TFT-LCD side)
TTL
↑
LVDS
PLL
TTL
↑
LVDS
PLL
Port A
Port B
10
AR0 AR9
10
AG0
10
AB0 AB9
10
BR0 BR9
10
BG0 BG9
10
BB0 BB9
∼ ∼
∼
DE_A
Hsync _A
Vsync _A
CLKA
∼ ∼
∼
DE_B
Hsync _B Vsync _B
CLKB
AG9
LCD Internal Circuit
Corresponding Transmitter: THC63LVD1023 (THine) or equivalent device.
CN2 side:
g
Controller
CR0 CR9
∼
CG0 CG9
∼
CB0 CB9
∼
ENAB_C
Hsync _C Vsync _C
CLKC
DR0 ∼ DR9 DG0 ∼ DG9 DB0 ∼ DB9
ENAB_D
Hsync_ D
Vsync _D
CLKD
LD- 19Z08-7
(TV Side)
Port C
10
10
10
Port D
10
10
10
LVD S
↑
TTL
PLL
LVDS
↑
TTL
PLL
CIN0+(11)
CIN0– (10)
CIN1+(13)
CIN1– (12)
CIN2+(15)
CIN2– (14)
CIN3+(21)
CIN3– (20)
CIN4+(23)
CIN4– (22)
CCK+(18)
CCK– (17)
DIN0+(27)
DIN0– (26)
DIN1+(29)
DIN1– (28)
DIN2+(31)
DIN2– (30)
DIN3+(37)
DIN3– (36)
DIN4+(39)
DIN4– (38)
DCK+(3 4)
DCK–(3 3)
TTL
LVDS
PLL
TTL
LVD S
PLL
(TFT-LCD side)
Port C
↑
Port D
↑
10
CR0 CR9
10
CG0
10
CB0 CB9
DE_C
Hsync _C
Vsync _C
10
DR0 DR9
10
DG0 DG9
10
DB0 DB9
DE_D
Hsync _D Vsync _D
CLKC
CLKD
∼ ∼
CG9
∼
LCD Internal Circuit
∼ ∼
∼
Corresponding Transmitter: THC63LVD1023 (THine) or equivalent device.
4.3. Block diagram(LCD Module)
INPUT SIGNALS
CIN0- CIN0+ CIN1- CIN1+ CIN2- CIN2+ CIN3- CIN3+ CIN4- CIN4+ CCK- CCK+ DIN0- DIN0+ DIN1- DIN1+ DIN2- DIN2+ DIN3- DIN3+ DIN4- DIN4+ DCK- DCK+
GATE DRIVER
INPUT SIGNALS
Von, V
,
BRT
BRT _sel
V
CN2
CONTROL PWB
Control
nals
Si
SOURCE DRIVER
LCD PANEL
1920×3(RGB)×1080
SOURCE DRIVER
CN1
Power Supply
Circuit
GATE DRIVER
INVERTER
CN103, 104
INPUT SIGNALS
Frame O/S_set SELLVDS AIN0- AIN0+ AIN1- AIN1+ AIN2- AIN2+ AIN3- AIN3+ AIN4- AIN4+ ACK- ACK+ BIN0- BIN0+ BIN1- BIN1+ BIN2- BIN2+ BIN3- BIN3+ BIN4- BIN4+ BCK- BCK+
POWER SUPPLY +12V DC
BACK LIGHT(CCFT×24)
POWER SUPPLY
+24V DC
LD- 19Z08-8
4.4. Backlight driving
CN103 (+24V DC power supply and inverter control)
Using connector: S14B-PH-K-S (LF) (JST) Mating connector: PHR-14 (JST)
Pin No. Symbol Function Default(OPEN) Input Impedance Remark
1 VINV +24V - 2 VINV +24V - 3 VINV +24V - 4 VINV +24V - 5 VINV +24V - 6 GND - 7 GND - 8 GND -
9 GND - 10 GND - 11 Reserved For LCD module internal
usage, should be open
12 VON Inverter ON/OFF GND : pull down
Inverter OFF
13 VBRT Brightness Control 3.3V : pull up
Brightness 100%
14 VBRT_sel Brightness Control
selection
*GND of an inverter board is not connected to GND of a module chassis and a liquid crystal panel drive part.
CN104(+24V DC power supply)
Using connector: S14B-PH-K-S(LF) (JST) Mating connector: PHR-14 (JST)
Pin No. Symbol Function Default(OPEN) Input Impedance Remark
1 VINV +24V -
2 VINV +24V -
3 VINV +24V -
4 VINV +24V -
5 VINV +24V -
6 GND -
7 GND -
8 GND -
9 GND - 10 GND - 11 Reserved For LCD module internal
usage, should be open
12 Reserved For LCD module internal
usage, should be open
13 Reserved For LCD module internal
usage, should be open
14 Reserved For LCD module internal
usage, should be open
[Note 1] Inverter ON/OFF
Input voltage Function
0V Inverter : OFF
3.3V Inverter : ON
3.3V : pull up Selected Analog PWM
22K ohm [Note 1]
100K ohm [Note 3]
100K ohm [Note 2]
-
-
[Note 2] Brightness Control selection
Pin No.14 is used for the selection of dimming control for V
Input voltage V
BRT
BRT pin (Pin No.13).
0V Pulse dimming
3.3V Analog dimming
[Note 3]Brightness Control
1. Analog Dimming
Brightness control is regulated by analog input voltage (0V to 3.3V).
Input voltage [V
BRT
[Reference]
Brightness ratio［%］
]
MIN TYP MAX Function
0V <-> 3.3V
0V: Dark - 3.3V: Bright
20 <-> 100
[Note] PWM frequency : 275±10Hz
[Note]There is a case that lamp mura may happen, depending on ambient temperature and dimming.
Dimming level should be set according to your evaluation of actual display performance. (Minimum input voltage 1.5V at below 15℃)
2.Pulse Dimming
Pin No.13 is used for the control of the PWM duty with input pulse from 150Hz to 350Hz.
LD- 19Z08-9
Ta=25℃
Input PWM waveform
High voltage
Low voltage
Ton
ON ON OFF
T
Duty＝TON/T
Pulse signal [Hz]
MIN TYP MAX
150 275 350
DUTY(TON/T) [%] 35 <-> 100 Dimming level
[%] 20 <-> 100
(Brightness ratio)
Pulse signal=275Hz
Remark
Ta=25℃ Ta=25℃
[Note]There is a case that lamp mura may happen, depending on ambient temperature,
in dimming. Minimum dimming level should be set according to your evaluation of actual display performance. (Minimum duty 60％ at below 15℃)
[Note]In case of using Pulse Dimming, be careful so that the V
signal (Pin 13) doesn’t have glitch.
BRT
LD- 19Z08-10
4.5. The back light system characteristics
The back light system is direct type with 24 CCFTs (Cold Cathode Fluorescent Tube).
The characteristics of the lamp are shown in the following table. The value mentioned below is at the case of one
CCFT.
Item Symbol Min. Typ. Max. Unit Remarks
Life time TL - 60000 - Hour [Note]
[Note]
• Lamp life time is defined as the time when brightness becomes 50% of the original value in the continuous
operation under the condition of Ta=25°C and brightness control(V
=100%).
BRT
• Above value is applicable when the long side of LCD module is placed horizontally (Landscape position).
(Lamp lifetime may vary if LCD module is in portrait position due to the change of mercury density inside
the lamp.)
5. Absolute Maximum Ratings
Parameter Symbol Condition Ratings Unit Remark
Input voltage
(for Control)
12V supply voltage
(for Control) Input voltage (for Inverter)
24V supply voltage
(for Inverter)
I
V
VCC
V
ON
V
BRT
VBRT _sel
V
INV
Ta=25 °C
Ta=25 °C
Ta=25 °C
Ta=25 °C
-0.3 ~ 3.6 V [Note 1]
0 ~ + 14 V
0 ~ + 6 V
0 ~ +29 V
Storage temperature Tstg - -25 ~ +60
Operation temperature
(Ambient)
Topa - 0 ~ +50
[Note 1] SELLVDS, FRAME, O/S_set, [Note 2] Humidity 95%RH Max.(Ta≦40°C)
Maximum wet-bulb temperature at 39 °C or less.(Ta>40°C) No condensation.
°C
[Note 2]
°C
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