SHARP LK520D3LZ88 Specification

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RECORDS OF REVISION
MODEL No. : LK520D3LZ88
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SPEC No. DATE
LD-20125
2008.1.17
2008.2.25
REVISED
A
No.
㧙㧙
PAGE SUMMARY NOTE
2 Changed the Mating LVDS transmitter
20 Changed the Lot No Label
21 Added comment about UL label
(Identification Code)
1st Issue
2nd Issue
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1. Application
This specification applies to the color 52.0” TFT-LCD module LK520D3LZ88.
* These technical literature are proprietary products of SHARP CORPORATION (“SHARP”) and include materials protected under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or by any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of SHARP.
* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,
automobiles, etc.), rescue and security equipment and various safety related equipment which require higher reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant system design should be taken.
* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for life support.
* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with
the instructions and the precautions specified in these specification.
* Contact and consult with a SHARP sales representative for any questions about this device.
2. Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit, inverter circuit and back light
system etc. Graphics and texts can be displayed on a 1920RGB1080 dots panel with using LVDS (L
This module also includes the DC/AC inverter to drive the CCFT. (+24V of DC supply voltage)
And in order to improve the response time of LCD, this module applies the Over Shoot driving (O/S driving) technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal according to a pre-fixed process as an image signal of the present frame when a difference is found between image signal of the previous frame and that of the current frame after comparing them.
With this technology, image signals can be set so that liquid crystal response completes within one frame. As a result, motion blur reduces and clearer display performance can be realized.
ow Voltage Differential Signaling) to interface, +12V of DC supply voltages.
3. Mechanical Specifications
Parameter Specifications Unit
Display size
Active area 1152.0(H) x 648.0 (V) mm
Pixel Format
Pixel pitch 0.600(H) x 0.600 (V) mm Pixel configuration R, G, B vertical stripe Display mode Normally black Unit Outline Dimensions (*1) 1219.0(W) x 706.7(H) x 64.6(D) mm Mass
Surface treatment
(*1) Outline dimensions are shown in Fig.1 (excluding protruding portion)
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132.174 㧔Diagonal㧕
52.0 Diagonal
1920(H) x 1080(V) 1pixel = R + G + B dot
21.0 r1.0 Anti glare Hard coating: 2H
LD- 20125A-1
one billion
cm
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4. Input Terminals
4.1. TFT panel driving
CN1 (Interface signals and +12V DC power supply)
Using connector : FI-RE51S-HF (Japan Aviation Electronics Ind. , Ltd.)
Mating connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind. , Ltd.)
Mating LVDS transmitter : THC63LVD1023 or equivalent device
Pin No. Symbol Function Remark
1 2 3 4 5 Reserved 6 Reserved 7 SELLVDS 8 Reserved
9 10 11 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
GND Reserved It is required to set non-connection(OPEN) Reserved It is required to set non-connection(OPEN) Reserved It is required to set non-connection(OPEN)
It is required to set non-connection(OPEN) It is required to set non-connection(OPEN) Select LVDS data order [Note1,2] It is required to set non-connection(OPEN)
O/S set O/S operation setting H:O/S_ON, L:O/S_OFF [Note 3]
FRAME
AIN0- Aport (-)LVDS CH0 differential data input
AIN0+ Aport (+)LVDS CH0 differential data input
AIN1- Aport (-)LVDS CH1 differential data input
AIN1+ Aport (+)LVDS CH1 differential data input
AIN2- Aport (-)LVDS CH2 differential data input
AIN2+ Aport (+)LVDS CH2 differential data input
GND
ACK- Aport LVDS Clock signal(-)
ACK+ Aport LVDS Clock signal(+)
GND
AIN3- Aport (-)LVDS CH3 differential data input
AIN3+ Aport (+)LVDS CH3 differential data input
AIN4- Aport (-)LVDS CH4 differential data input
AIN4+ Aport (+)LVDS CH4 differential data input
GND
GND
BIN0- Bport (-)LVDS CH0 differential data input
BIN0+ Bport (+)LVDS CH0 differential data input
BIN1- Bport (-)LVDS CH1 differential data input
BIN1+ Bport (+)LVDS CH1 differential data input
BIN2- Bport (-)LVDS CH2 differential data input
BIN2+ Bport (+)LVDS CH2 differential data input
GND
BCK- Bport LVDS Clock signal(-)
BCK+ Bport LVDS Clock signal(+)
GND
BIN3- Bport (-)LVDS CH3 differential data input
BIN3+ Bport (+)LVDS CH3 differential data input
BIN4- Bport (-)LVDS CH4 differential data input
BIN4+ Bport (+)LVDS CH4 differential data input
GND
GND
GND
Frame frequency setting 1:60Hz 0:50Hz
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(Shown in Fig.1)
LD- 20125A-2
ًA
Pull up 3.3V Pull up 3.3V Pull up 3.3V Pull down: (GND) Pull down: (GND) Pull down: (GND) Pull down: (GND) Pull up 3.3V Pull down :GND
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45 46 47 48 49 50 51
[note]GND of a liquid crystal panel drive part has connected with a module chassis.
GND
GND
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
[Note 1]The equivalent circuit figure of the terminal
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LD- 20125A-3
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[Note 2] LVDS Data order
SELLVDS
Data L(GND) or Open
TA0 TA1 TA2 TA3 TA4 TA5
TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 NA NA
TC5 NA NA TC6 DE(*) DE(*) TD0
TD1 TD2 TD3 TD4 TD5 TD6
TE0
TE1
TE2
TE3
TE4
TE5
TE6
NA: Not Available (*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE signal during operation at ”High”.
R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7
R8
R9(MSB)
G8
G9(MSB)
B8
B9(MSB)
NA
R0(LSB)
R1
G0(LSB)
G1
B0(LSB)
B1
NA
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LD- 20125A-4
H(3.3V)
R4 R5 R6 R7 R8 R9(MSB) G4 G5 G6 G7 G8 G9(MSB) B4 B5 B6 B7 B8 B9(MSB)
R2 R3 G2 G3 B2 B3
N/A R0(LSB)
R1 G0(LSB) G1 B0(LSB) B1 N/A
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,
SELLVDS= Low (GND) or OPEN
ACK+,BCK+
ACK ,BCK
AIN0+,BIN0+ AIN0
BIN0
AIN1+,BIN1+ AIN1
,BIN1
AIN2+,BIN2+ AIN2
,BIN2
AIN3+,BIN3+
,BIN3
AIN3
AIN4+,BIN4+ AIN4
,BIN4
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ًA
1 cycle
G2 R7 R6 R5 R4 R3 R2 R2 R3 G2
B3 B2 G7 G6 G5 G4 G3 G3 G4 B3
DE
NA NA
B9 B8 G9 G8 R9 R8 R8 R9 NA NA
B1 B0 G1 G0 R1 R0 R0 R1 NA NA
B7 B6 B5 B4 B4 B5
LD- 20125A-5
DE
SELLVDS= High (3.3V)
ACK+,BCK+
ACK ,BCK
AIN0+,BIN0+ AIN0
,BIN0
AIN1+,BIN1+ AIN1
,BIN1
AIN2+,BIN2+ AIN2
,BIN2
AIN3+,BIN3+ AIN3
,BIN3
AIN4+,BIN4+
,BIN4
AIN4
1 cycle
G4 R9 R8 R7 R6 R5 R4 R4 R5 G4
B5 B4 G9 G8 G7 G6 G5 G5 G6 B5
DE
NA NA
B3 B2 G3 G2 R3 R2 R2 R3 NA NA
B1 B0 G1 G0 R1 R0 R0 R1 NA NA
B9 B8 B7 B6 B6 B7
DE
DE: Display Enable,NA: Not Available (Fixed Low)
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[Note 3] The equivalent circuit figure of the terminal
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4.2. Interface block diagram
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LD- 20125A-6
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