SHARP LK520D3LZ17 Specification

RECORDS OF REVISION

MODEL No. : LK520D3LZ17
SPEC No. : LD-19X10

SPEC No. DATE

REVISED

LD-19X10 2007.10.23

No.

−



PAGE

Changed Contents from LK520D3LZ18

−

- Adjusting Color Tracking to be flat

- Changing input signals to 10bit (8bit+2bit FRC)

SUMMARY NOTE

1st Issue

LD- 19X10-1

1. Application

This specification applies to the color 52.0” TFT-LCD module LK520D3LZ17.

* These specification sheets are proprietary products of SHARP CORPORATION (“SHARP”) and include materials
protected under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or by
any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of
SHARP.

* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,

automobiles, etc.), rescue and security equipment and various safety related equipment which require higher
reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant
system design should be taken.

* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,

telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for
life support.

* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with

the instructions and the precautions specified in these specification sheets.

* Contact and consult with a SHARP sales representative for any questions about this device.

2. Overview

This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is
composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit, inverter circuit and back light

system etc. Graphics and texts can be displayed on a 1920×RGB×1080 dots panel with 650 million colors by
using LVDS (Low Voltage Differential Signaling) to interface, +12V of DC supply voltages.

This module also includes the DC/AC inverter to drive the CCFT. (+24V of DC supply voltage)

And in order to improve the response time of LCD, this module applies the Over Shoot driving (O/S driving)
technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal
according to a pre-fixed process as an image signal of the present frame when a difference is found between image
signal of the previous frame and that of the current frame after comparing them.

With this technology, image signals can be set so that liquid crystal response completes within one frame. As a
result, motion blur reduces and clearer display performance can be realized.

3. Mechanical Specifications

Parameter Specifications Unit

Display size

Active area 1152.0(H) x 648.0 (V) mm

Pixel Format

Pixel pitch 0.600(H) x 0.600 (V) mm
Pixel configuration R, G, B vertical stripe
Display mode Normally black
Unit Outline Dimensions (*1) 1219.0(W) x 706.7(H) x 64.6(D) mm
Mass

Surface treatment

(*1) Outline dimensions are shown in Fig.1 (excluding protruding portion)

132.174 （Diagonal）

52.0 （Diagonal）

1920(H) x 1080(V)
（1pixel = R + G + B dot）

21.0 ±1.0
Anti glare
Hard coating: 2H

cm

inch

pixel

kg

4. Input Terminals

4.1. TFT panel driving

CN1 (Interface signals and +12V DC power supply)

Using connector : FI-RE51S-HF (Japan Aviation Electronics Ind. , Ltd.)
Mating connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind. , Ltd.)
Mating LVDS transmitter : THC63LVD1023 or equivalent device

Pin No. Symbol Function Remark

1
2 TEST

3 TEST
4

5 R/L
6 U/D
7 SELLVDS
8 TEST

9
10
11 GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Reserved

Reserved

Reserved
Reserved

AIN0- Aport (-)LVDS CH0 differential data input

AIN0+ Aport (+)LVDS CH0 differential data input

AIN1- Aport (-)LVDS CH1 differential data input

AIN1+ Aport (+)LVDS CH1 differential data input

AIN2- Aport (-)LVDS CH2 differential data input

AIN2+ Aport (+)LVDS CH2 differential data input

GND

ACK- Aport LVDS Clock signal(-)

ACK+ Aport LVDS Clock signal(+)

GND

AIN3- Aport (-)LVDS CH3 differential data input

AIN3+ Aport (+)LVDS CH3 differential data input

AIN4- Aport (-)LVDS CH4 differential data input

AIN4+ Aport (+)LVDS CH4 differential data input

GND
GND

BIN0- Bport (-)LVDS CH0 differential data input

BIN0+ Bport (+)LVDS CH0 differential data input

BIN1- Bport (-)LVDS CH1 differential data input

BIN1+ Bport (+)LVDS CH1 differential data input

BIN2- Bport (-)LVDS CH2 differential data input

BIN2+ Bport (+)LVDS CH2 differential data input

GND

BCK- Bport LVDS Clock signal(-)

BCK+ Bport LVDS Clock signal(+)

GND

BIN3- Bport (-)LVDS CH3 differential data input

BIN3+ Bport (+)LVDS CH3 differential data input

BIN4- Bport (-)LVDS CH4 differential data input

BIN4+ Bport (+)LVDS CH4 differential data input

GND
GND
GND

Fix to Low level or open usually.
Fix to Low level or open usually.

Horizontal shift direction [Note1,2]
Vertical shift direction [Note1,2]
Select LVDS data order [Note3,4]
Fix to Low level or open usually.

(Shown in Fig.1)

Pull down : (GND)
Pull down : (GND)
Pull up : (3.3V)
Pull down : (GND)

LD- 19X10-2

45
46
47
48
49
50
51

[note]GND of a liquid crystal panel drive part has connected with a module chassis.



GND
GND
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply

[Note 1] Display reversal function

Normal (Default)  Horizontal reverse image

R/L : L (GND) U/D: L (GND) R/L : H (3.3V) U/D: L (GND)

CN1

Vertical reverse image Horizontal and vertical reverse image

R/L : L (GND) U/D: H (3.3V) R/L : H(3.3V) U/D: H (3.3V)

CN1

[Note 2]The equivalent circuit figure of the terminal

100Ω

Terminal

LD- 19X10-3

CN1

CN1

Min : 16.5KΩ
Typ : 47KΩ
Max : 330KΩ



[Note 3]The equivalent circuit figure of the terminal

3.3V

4.7KΩ

100Ω

Terminal

Min : 16.5KΩ
Typ : 60KΩ
Max : 330KΩ



[Note 4] LVDS Data order

Data L(GND) H(3.3V) or Open

TA0 R2 R4

TA1 R3 R5

TA2 R4 R6

TA3 R5 R7

TA4 R6 R8

TA5 R7 R9(MSB)

TA6 G2 G4

TB0 G3 G5
TB1 G4 G6
TB2 G5 G7
TB3 G6 G8
TB4 G7 G9(MSB)
TB5 B2 B4
TB6 B3 B5
TC0 B4 B6
TC1 B5 B7
TC2 B6 B8
TC3 B7 B9(MSB)
TC4 NA NA
TC5 NA NA
TC6 DE(*) DE(*)
TD0 R8 R2
TD1 R9(MSB) R3
TD2 G8 G2
TD3 G9(MSB) G3
TD4 B8 B2
TD5 B9(MSB) B3
TD6 N/A N/A

TE0 R0(LSB) R0(LSB)

TE1 R1 R1

TE2 G0(LSB) G0(LSB)

TE3 G1 G1

TE4 B0(LSB) B0(LSB)

TE5 B1 B1

TE6 N/A N/A

NA: Not Available
(*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE
signal during operation at ”High”.

LD- 19X10-4

SELLVDS

NAN

NAN

NAN

NAN

–

,

–

–

SELLVDS= High (3.3V) or OPEN

ACK+,BCK+

ACK– ,BCK–

AIN0+,BIN0+
AIN0

–,BIN0–

AIN1+,BIN1+

–,BIN1–

AIN1

AIN2+,BIN2+
AIN2

–,BIN2–

AIN3+,BIN3+
AIN3

–,BIN3–

AIN4+,BIN4+

–,BIN4–

AIN4

SELLVDS= Low (GND)

ACK+,BCK+

ACK– ,BCK–

AIN0+,BIN0+
AIN0

BIN0

AIN1+,BIN1+
AIN1

–,BIN1–

AIN2+,BIN2+
AIN2

–,BIN2–

AIN3+,BIN3+

–,BIN3–

AIN3

AIN4+,BIN4+

AIN4

–,BIN4

DE: Display Enable, NA: Not Available (Fixed Low)

LD- 19X10-5

1 cycle

G4 R9 R8 R7 R6 R5 R4 R4 R5 G4

B5 B4 G9 G8 G7 G6 G5 G5 G6 B5

DE

A

A

NA NA

B3 B2 G3 G2 R3 R2 R2 R3

B1 B0 G1 G0 R1 R0 R0 R1

B9 B8 B7 B6 B6 B7

DE

1 cycle

G2 R7 R6 R5 R4 R3 R2 R2 R3 G2

B3 B2 G7 G6 G5 G4 G3 G3 G4 B3

DE

A

A

NA NA

B9 B8 G9 G8 R9 R8 R8 R9

B1 B0 G1 G0 R1 R0 R0 R1

B7 B6 B5 B4 B4 B5

DE

LD- 19X10-6

CN2 (O/S control) (Shown Fig 1)

O/S Driving Pin No and function
Using connector : SM07B-SRSS-TB-A (JST)
Mating connector : SHR-07V-S or SHR-07V-S-B（JST）

Pin No. Symbol Function Default Remark

1

FRAME

Frame frequency setting 1:60Hz 0:50Hz

2 O/S set O/S operation setting H:O/S_ON, L:O/S_OFF [Note 1]
3 TEST Not Available
4 Temp3 Data3 of panel surface temperature
5 Temp2 Data2 of panel surface temperature
6 Temp1 Data1 of panel surface temperature

Pull down :GND
Pull up 3.3V [Note 2]
Pull down :GND
Pull up 3.3V
Pull up 3.3V
Pull up 3.3V

7 GND GND

*L: Low level voltage (GND) H: High level voltage(3.3V)

[Note 1] In case of O/S set setting ”L”(O/S_OFF), it should be set the TEMP1~3 to “L”.

[Note 2] The equivalent circuit figure of the terminal

3.3V

4.7KΩ

100Ω

Terminal

[Note 2]
[Note 2]
[Note 2]

Min : 16.5KΩ
Typ : 47KΩ
Max : 330KΩ

According as the surface temperature of the panel, enter the optimum 3 bit signal into pin No.4, 5 and 6.
Measuring the correlation between detected temperature by the sensor on PWB in user’s side and actual
surface temperature of panel at center, convert the temperature detected by the sensor to the surface
temperature of panel to enter the 3 bit temperature data.
For overlapping temperatures (such as 5°C, 10°C, 15°C, 20°C, 25°C, 30°C, 35°C) select the optimum
parameter, judging from the actual picture image.

Surface temperature of panel

Pin no.

0-5°C 5-10°C 10-15°C 15-20°C 20-25°C 25-30°C 30-35°C 35°C and

above
4 0 0 0 0 1 1 1 1
5 0 0 1 1 0 0 1 1
6 0 1 0 1 0 1 0 1

*0: Low level voltage (GND) 1: High level voltage(3.3V)
*For overlapping temperatures (such as 5°C, 10°C, 15°C, 20°C, 25°C, 30°C, 35°C) select the optimum

parameter, judging from the actual picture image.

4.2. Interface block diagram

O/S CONTROL
SIGNALS

O/SSET
FRAME
TEMP3
TEMP2

INPUT
SIGNALS

VON,VBRT




Control




1920×3(RGB)×1080



GATEDRIVER



CN2

CONTROLPWB

SOURCE DRIVER

LCDPANEL

INVERTER

CN1

PowerSupply

Circuit

INPUTSIGNALS

R/L
U/D
SELLVDS 
AIN0-AIN0+
AIN1-AIN1+
AIN2-AIN2+
AIN3-AIN3+
AIN4-AIN4+
ACK-ACK+
BIN0-BIN0+
BIN1-BIN1+
BIN2-BIN2+
BIN3-BIN3+
BIN4-BIN4+
BCK-BCK+


POWERSUPPLY
  +12VDC

GATEDRIVER

BACK LIGHT(CCFT×24)

POWERSUPPLY

  +24VDC

LD- 19X10-7



LD- 19X10-8

4.3. Backlight driving
CN103 (+24V DC power supply and inverter control)

Using connector: S14B-PH-K-S (LF) (JST)
Mating connector: PHR-14 (JST)

Pin No. Symbol Function Default(OPEN) Input Impedance Remark

1 VINV +24V -
2 VINV +24V -
3 VINV +24V -
4 VINV +24V -
5 VINV +24V -
6 GND -
7 GND -
8 GND -

9 GND -
10 GND -
11 Reserved For LCD module internal

usage, should be open

12 VON Inverter ON/OFF GND : pull down

Inverter OFF

13 VBRT Brightness Control 3.3V : pull up

Brightness 100%

14 VBRT _sel Brightness Control

selection

*GND of an inverter board is not connected to GND of a module chassis and a liquid crystal panel drive part.

CN104(+24V DC power supply)

Using connector: S14B-PH-K-S(LF) (JST)
Mating connector: PHR-14 (JST)

Pin No. Symbol Function Default(OPEN) Input Impedance Remark

1 VINV +24V -

2 VINV +24V -

3 VINV +24V -

4 VINV +24V -

5 VINV +24V -

6 GND -

7 GND -

8 GND -

9 GND -
10 GND -
11 Reserved For LCD module internal

usage, should be open

12 Reserved For LCD module internal

usage, should be open

13 Reserved For LCD module internal

usage, should be open

14 Reserved For LCD module internal

usage, should be open

[Note 1] Inverter ON/OFF

Input voltage Function

0V Inverter : OFF

3.3V Inverter : ON

3.3V : pull up
Selected Analog PWM

22K ohm [Note 1]

950K ohm [Note 3]

26.7K ohm [Note 2]

-

-

[Note 2] Brightness Control selection

Pin No.14 is used for the selection of dimming control for V

Input voltage V

BRT

BRT pin (Pin No.13).

0V Pulse dimming

3.3V Analog dimming

[Note 3]Brightness Control

1. Analog Dimming
Brightness control is regulated by analog input voltage (0V to 3.3V).

Input voltage [V

BRT

]

[Reference]

Brightness ratio［%］

MIN TYP MAX Function

0V <-> 3.3V

0V: Dark - 3.3V: Bright

20 <-> 100

[Note] PWM frequency : 275±10Hz

[Note]There is a case that lamp mura may happen, depending on ambient temperature and dimming.

Dimming level should be set according to your evaluation of actual display performance.
(Minimum input voltage 1.4V at below 15℃)

2.Pulse Dimming
Pin No.13 is used for the control of the PWM duty with input pulse from 150Hz to 350Hz.

LD- 19X10-9

Ta=25℃

InputPWMwaveform

Pulse signal [Hz]
DUTY(TON/T) [%] 40 <-> 100

Dimming level
(luminance ratio)

[Reference]The characteristic of the pulse PWM duty vs dimming level

[Note]There is a case that lamp mura may happen, depending on ambient temperature,

[Note]In case of using Pulse Dimming, be careful so that the V

Ton

Highvoltage

Lowvoltage

ON ONOFF

T

Duty＝T

ON

/T

MIN TYP MAX

Remark

150 275 350

Ta=25℃

DUTY(TON/T)

[%] 20 <-> 100

Dimming level

Ta=25℃

(luminance ratio)
40% 20%
60% 45%
80% 70%

Input Condition
Pulse Signal=275Hz
Ta=25℃

100% 100%

in dimming. Minimum dimming level should be set according to your evaluation of
actual display performance. (Minimum duty 60% at below 15℃)

signal (Pin 13) doesn’t have glitch.

BRT