SHARP LK520D3LB2S Specification
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RECORDS OF REVISION
MODEL No. : LK520D3LB2S
SPEC No. : LD-K21Y20
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SPEC No. DATE
LD-K21Y20 2009.12.14 - - - 1st ISSUE
REVISED
PAGE SUMMARY NOTE
No.
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1. Application
This specification applies to the color 52.0” TFT-LCD module LK520D3LB2S
* This specification is proprietary product of SHARP CORPORATION (“SHARP”) and include materials protected
under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or by any
means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of
SHARP.
* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,
automobiles, etc.), rescue and security equipment and various safety related equipment which require higher
reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant
system design should be taken.
* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for
life support.
* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with
the instructions and the precautions specified in these specification.
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LD- K21Y20-1
* Contact and consult with a SHARP sales representative for any questions about this device.
2. Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is
composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit, LED drive circuit and back
light system etc. Graphics and texts can be displayed on a 1920 × RGB × 1080 dots panel with one billion colors by
using 10bit LVDS (L
This module also includes the LED-PWB module to drive the LED. (±120mA of DC supply current)
And in order to improve the response time of LCD, this module applies the Over Shoot driving (O/S driving)
technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal
according to a pre-fixed process as an image signal of the present frame when a difference is found between image
signal of the previous frame and that of the current frame after comparing them.
With this technology, image signals can be set so that liquid crystal response completes within one frame. As a
result, motion blur reduces and clearer display performance can be realized.
This LCD module also adopts Quadruple-Frame Rate driving method including FRC (Frame Rate Control)
function on the control circuit. Therefore the input signal to this LCD module is Single Frame Rate, but the output is
Quadruple-Frame Rate picture (inserting the intermediate image which is generated by the FRC).
With combination of these technologies, motion blur can be reduced and clearer display performance can be
realized.
ow Voltage Differential Signaling) to interface, +12V of DC supply voltages.
3. Mechanical Specifications
Parameter Specifications Unit
Display size
Active area 1152.0(H) × 648.0 (V) mm
Pixel Format
Pixel pitch 0.600 (H) × 0.600 (V) mm
Pixel configuration R, G, B vertical stripe
Display mode Normally black
Unit Outline Dimensions [Note] 1227 (W) × 741 (H) × 27.6 (D) mm
Mass 14.7 kg
Surface treatment
[Note] Outline dimensions are shown in Fig.17 (excluding protruding portion)
132.174 (Diagonal) cm
52.0 (Diagonal) inch
1920(H) × 1080(V)
（1pixel = R + G + B dot）
Clear LR(Low Reflection coating)
Hard coating: 3H
pixel
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4. Input Terminals
4.1. TFT panel driving
CN1 (Interface signals and +12V DC power supply) (Shown in Fig.1)
Using connector : FI-RNE51SZ-HF (Japan Aviation Electronics Ind., Ltd.)
Mating connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind., Ltd.)
Mating LVDS transmitter : THC63LVD1023 or equivalent device
Pin No. Symbol Function Remark
1
2
3
4
5
6
7
8
9
10
11 AIN0+ Aport (+)LVDS CH0 differential data input
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
VCC +12V Power Supply
Open
GND
GND
GND
AIN0-
AIN1- Aport (-)LVDS CH1 differential data input
AIN1+ Aport (+)LVDS CH1 differential data input
AIN2- Aport (-)LVDS CH2 differential data input
AIN2+ Aport (+)LVDS CH2 differential data input
GND
ACK- Aport LVDS Clock signal(-)
ACK+ Aport LVDS Clock signal(+)
GND
AIN3- Aport (-)LVDS CH3 differential data input
AIN3+ Aport (+)LVDS CH3 differential data input
AIN4- Aport (-)LVDS CH4 differential data input
AIN4+ Aport (+)LVDS CH4 differential data input
GND
BIN0- Bport (-)LVDS CH0 differential data input
BIN0+ Bport (+)LVDS CH0 differential data input
BIN1- Bport (-)LVDS CH1 differential data input
BIN1+ Bport (+)LVDS CH1 differential data input
BIN2- Bport (-)LVDS CH2 differential data input
BIN2+ Bport (+)LVDS CH2 differential data input
GND
BCK- Bport LVDS Clock signal(-)
BCK+ Bport LVDS Clock signal(+)
GND
BIN3- Bport (-)LVDS CH3 differential data input
BIN3+ Bport (+)LVDS CH3 differential data input
BIN4- Bport (-)LVDS CH4 differential data input
BIN4+ Bport (+)LVDS CH4 differential data input
GND
I2C_SCL I2C CLK
I2C_SDA I2C Data
Open
B-INT
PANEL_SEL
FRC_PWR_CTRL
Aport (-)LVDS CH0 differential data input
Open
I2C bus enable(H:enable, L:disable) [Note 1]
(PANEL Sel Signal) [Note 2]
Power on sequence(DC/DC On Signal)
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LD- K21Y20-2
Open
Pull down : (GND)
Pull down : (GND)
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46
47
48
49
50
51
[Note] GND of a liquid crystal panel drive part has connected with a module chassis.
CN2 (+12V DC power supply)
Using connector : BM04B-PASS (J.S.T.Mfg Co., Ltd.)
Mating connector : (PAP-04V-S) (J.S.T.Mfg Co., Ltd.)
Pin No. Symbol Function Remark
1
2
3
4
SA_MODE
PANEL_ON
FRC_RST FRC IC RESET Pull down : (GND)
Open
TCON_RDY TCON ready signal (H:OK, L:NG)
Open
VCC +12V Power Supply
VCC +12V Power Supply
GND
GND
SA Mode Sel Signal
(L:Set mode, H:Stand alone(SA) mode)
Power on sequence
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LD- K21Y20-3
Pull up +3.3V
Pull down : (GND)
Open
Open
[Note 1] B_INT
Pin No. Symbol Function
43
[Note 2] PANEL_SEL
R1 Panel type Address
Open Standard Slave address and Power sequence are standard.
B_INT Select I2C Bus
0: FRC is I2C master. (EEPROM access mode )
1: FRC is I2C slave. (μ com mode(SA_MODE = ‘1’))
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㪋㪎㫂
com
㱘
㪪㪼㫋㩷㪹㫆㪸㫉㪻
Fig.1 Block diagram of PANEL_SEL
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4.2. LVDS Data order
LVDS Mapping
Data [JEIDA]
TA0 R4
TA1 R5
TA2 R6
TA3 R7
TA4 R8
TA5 R9
TA6 G4
TB0 G5
TB1 G6
TB2 G7
TB3 G8
TB4 G9
TB5 B4
TB6 B5
TC0 B6
TC1 B7
TC2 B8
TC3 B9
TC4 HSYNC
TC5 VSYNC
TC6 DE (*)
TD0 R2
TD1 R3
TD2 G2
TD3 G3
TD4 B2
TD5 B3
TD6 N/A
TE0 R0
TE1 R1
TE2 G0
TE3 G1
TE4 B0
TE5 B1
TE6 N/A
NA:Not Available
(*)Since the display position is prescribed by the rise of DE(Display Enable) signal, please do not fix DE
signal during operation at ”High”.
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LD- K21Y20-4
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4.3. LVDS Mapping
ACK+,BCK+
ACK
– ,BCK–
AIN0+,BIN0+
AIN0
–,BIN0–
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LD- K21Y20-5
1 cycle
G4 R9 R8 R7 R6 R5 R4 R4R5 G4
AIN1+,BIN1+
AIN1
–,BIN1–
AIN2+,BIN2+
AIN2
–,BIN2–
AIN3+,BIN3+
–,BIN3–
AIN3
AIN4+,BIN4+
–,BIN4–
AIN4
B5 B4 G9 G8 G7 G6 G5 G5G6 B5
DE
Vsync Hsync
B3 B2 G3 G2 R3 R2 R2R3 NANA
B1 B0 G1 G0 R1 R0 R0R1 NANA
B9 B8 B7 B6 B6B7
DE: Display Enable, NA: Not Available (Fixed Low)
Fig.2 LVDS Mapping
DE
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4.4. Panel ID data map
The slave address of EEPROM(24C02) is AA.
No. Item Spec(Ex.) Address Data Remark
1
2
3
4
5
6
7
8
[Note 1] Vender code
Vender code Data
SHARP
Vender code SHARP 00 03 Select Note1) *Sony use.
Screen size 52” 01 34
H-Resolution 1920 02,03 07,80
V-Resolution 1080 04,05 04,38
V-Frequency 200/240Hz 06 02 Select Note2)
Data format
Revision code
Part Number
-
-
-
-
-
-
00
01
02
03
04
05
06
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10bit 07 02
001
LK520D3LB2S
FA〜FF
E0〜EF
30,30,31,00,00,00
4C,4B,35,32,30,44,
33,4C,42,32,53,00,
00,00,00,00
HEX data
HEX data
HEX data
Select Note3)
ASCII Note4)
ASCII Note4)
LD- K21Y20-6
*Sony use.
*Sony use.
[Note 2] V-Frequency
V-Frequency Data
50/60Hz
100/120Hz
200/240Hz
[Note 3] Data format
Data format Data
6bit
8bit
10bit
[Note 4] An empty address inputs “00”.
00
01
02
00
01
02
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㩿
㪀
㪪㪦㪬㪩㪚㪜 㪛㪩㪠㪭㪜㪩
Single Frame
-Rate Signal
Quadruple Frame
-Rate Signal
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㩿
㪀
4.5. Interface block diagram
POWER SUPPLY
+12V DC
㩷
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㩷
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㩷
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LD- K21Y20-7
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㪧㪘㪥㪜㪣㪶㪦㪥㩷
㪝㪩㪚㪶㪩㪪㪫㩷
㩷
㪫㪚㪦㪥㪶㪩㪛㪰㩷
㩷
㩷 㩷 㪂㪈㪉㪭㩷㪛㪚㩷
㩷㩷
㪚㪥㪈㪇㪊
BACK LIGHT (LED276 package)
㪚㪥㪈㪇㪋
㪈㪉㪇㫄㪘㩷㫏㩷㪉㪣㫀㫅㪼㩷
㪄㪉㪊㪇㪭㩷‒㪛㪚
㪈㪉㪇㫄㪘㩷㫏㩷㪉㪣㫀㫅㪼㩷
㪂㪉㪊㪇㪭㩷‒㪛㪚
Fig.3 Interface block diagram
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