SHARP LK520D1LH00 Specification
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P
RODUCT SPECIFICATIONS
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AVC Liquid Crystal Displays Group
LK520D1LH00
TFT-LCD Module
Spec. Issue Date: June 30, 2007
No: LD-20125-1
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RECORDS OF REVISION
MODEL No. : LK520D1LH00
SPEC No. : LD-20125-1
REVISED
DATE NO. PAGE SUMMARY
No.
NOTE
2007.04.12 LD-20125
2007.09.28 LD-20125-1
−
A
−
P26 Changed Timing
−
characteristics
1st Issu
2nd Issue
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1. Application
This specification applies to the color 52.0” TFT-LCD module LK520D1LH00.
* These technical literature are proprietary products of SHARP CORPORATION (“SHARP”) and include materials
protected under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or by
any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of
SHARP.
* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,
automobiles, etc.), rescue and security equipment and various safety related equipment which require higher
reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant
system design should be taken.
* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for
life support.
* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with
the instructions and the precautions specified in these specification.
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LD- 20125-1
* Contact and consult with a SHARP sales representative for any questions about this device.
2. Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is
composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit, inverter circuit and back light
system etc. Graphics and texts can be displayed on a 1920×RGB×1080 dots panel with
using LVDS (Low Voltage Differential Signaling) to interface, +12V of DC supply voltages.
This module not includes the DC/AC inverter to dri ve the CCFT.
And in order to improve the response time of LCD, this module applies the Over Shoot driving (O/S driving)
technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal
according to a pre-fixed process as an image signal of the present frame when a difference is found between image
signal of the previous frame and that of the current frame after comparing them.
With this technology, image signals can be set so that liquid crystal response completes within one frame. As a
result, motion blur reduces and clearer display performance can be realized.
one billion
colors by
3. Mechanical Specifications
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4. Input Terminals
4.1. TFT panel driving
CN1 (Interface signals and +12V DC power supply) (Shown in Fig.1)
Using connector : FI-RE51S-HF (Japan Aviation Electronics Ind. , Ltd.)
Mating connector
Mating LVDS transmitter
Pin No. 1Symbol
GND
2
3
4
5
6
7
8
9
10
11 GND
12 AIN013 AIN0+ Aport (+)LVDS CH0 differential data input
14
15
16 AIN2- Aport (-)LVDS CH2 differential data input
17
18
19
20
21
22 AIN3- Aport (-)LVDS CH3 differential data input
23
24
25
26
27
28 BIN0- Bport (-)LVDS CH0 differential data input
29
30
31
32 BIN2- Bport (-)LVDS CH2 differential data input
33
34
35
36
37
38
39
40
41
42
43
44
Reserved It is required to set non-connection(OPEN)
Reserved It is required to set non-connection(OPEN)
Reserved It is required to set non-connection(OPEN)
Reserved It is required to set non-connection(OPEN)
Reserved It is required to set non-connection(OPEN)
SELLVDS Select LVDS data order [Note1,2]
Reserved It is required to set non-connection(OPEN)
O/S set O/S operation setting H:O/S_ON, L:O/S_OFF [Note 3]
FRAME Frame frequency setting 1:60Hz 0:50Hz
Aport (-)LVDS CH0 differential data input
AIN1- Aport (-)LVDS CH1 differential data input
AIN1+ Aport (+)LVDS CH1 differential data input
AIN2+ Aport (+)LVDS CH2 differential data input
GND
ACK- Aport LVDS Clock signal(-)
ACK+ Aport LVDS Clock signal(+)
GND
AIN3+ Aport (+)LVDS CH3 differential data input
AIN4- Aport (-)LVDS CH4 differential data input
AIN4+ Aport (+)LVDS CH4 differential data input
GND
GND
BIN0+ Bport (+)LVDS CH0 differential data input
BIN1- Bport (-)LVDS CH1 differential data input
BIN1+ Bport (+)LVDS CH1 differential data input
BIN2+ Bport (+)LVDS CH2 differential data input
GND
BCK-
BCK+
Bport LVDS Clock signal(-)
Bport LVDS Clock signal(+)
GND
BIN3-
Bport (-)LVDS CH3 differential data input
BIN3+ Bport (+)LVDS CH3 differential data input
BIN4- Bport (-)LVDS CH4 differential data input
BIN4+ Bport (+)LVDS CH4 differential data input
GND
GND
GND
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LD- 20125-2
: FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind. , Ltd.)
: THC63LVDM83R or equivalent device
Function Remark
Pull up 3.3V
Pull up 3.3V
Pull up 3.3V
Pull down : (GND)
Pull down : (GND)
Pull down : (GND)
Pull down : (GND)
Pull up 3.3V
Pull down :GND
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45
46
47
48
49
50
51
GND
GND
VCC
VCC
VCC
VCC
VCC
+12VPower Supply
+12VPower Supply
+12VPower Supply
+12VPower Supply
+12VPower Supply
[note]GND of a liquid crystal panel drive part has connected with a module chassis.
[Note 1]The equivalent circuit figure of the terminal
Terminal
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LD- 20125-3
100Ω
10KΩ
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[Note 2] LVDS Data order
SELLVDS
Data
L(GND) or Open
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LD- 20125-4
H(3.3V)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4 NA
TC5 NA
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TE0
TE1
TE2
TE3
TE4
TE5
TE6
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
DE(*)
R8
R9(MSB)
G8
G9(MSB)
B8
B9(MSB)
NA
R0(LSB)
R1
G0(LSB)
G1
B0(LSB)
B1
NA
R4
R5
R6
R7
R8
R9(MSB)
G4
G5
G6
G7
G8
G9(MSB)
B4
B5
B6
B7
B8
B9(MSB)
NA
NA
DE(*)
R2
R3
G2
G3
B2
B3
N/A
R0(LSB)
R1
G0(LSB)
G1
B0(LSB)
B1
N/A
NA: Not Available
(*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE
signal during operation at ”High”.
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LD- 20125-5
SELLVDS= Low (GND) or OPEN
ACK+,BCK+
–
,BCK
,BIN2
–
,BIN3
–
–
–
–
–
R3
G4
B5
R9
R2
G3
B4
R8
ACK
AIN0+,BIN0+
AIN0–,BIN0
AIN1+,BIN1+
AIN1–,BIN1
AIN2+,BIN2+
–
AIN2
AIN3+,BIN3+
AIN3
▲A
G2
B3
DE
NA
1 cycle
R7
B2
NA NA
B9 B8
R6
G7
R5
G6
B7
G9
R4
G5
B6
G8
R3
G4
B5
R9
R2
G3
B4
R8
G2
B3
DE
NA
AIN4+,BIN4+
AIN4–,BIN4
–
SELLVDS= High (3.3V)
ACK+,BCK+
ACK
–
,BCK
–
AIN0+,BIN0+
AIN0
–
,BIN0
–
AIN1+,BIN1+
–
,BIN1
–
,BIN2
–
,BIN3
–
–
–
AIN1
AIN2+,BIN2+
AIN2
AIN3+,BIN3+
AIN3
R1
R5
G6
B7
R3
R0
R4
G5
B6
R2
NA
G4
B5
DE
NA
B1
R9
B4
NA
B3
B0
R8
G9
NA
B2
G1
1 cycle
R7
G8
B9
G3
G0
R6
G7
B8
G2
R1
R5
G6
B7
R3
R0
R4
G5
B6
R2
NA
G4
B5
DE
NA
AIN4+,BIN4+
AIN4
–
,BIN4
–
R1
R0
NA
B1
B0
G1
G0
R1
R0
DE: Display Enable, NA: Not Available (Fixed Low)
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NA
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