SHARP LK400D3HAxx Specification
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TECHNICAL LITERATURE
TFT - LCD PANEL
( Open Cell )
㨀㧱㧺㨀㧭㨀㧵㨂㧱
FOR
No.
DATE May. 21. 2010
LD-K22553
MODEL No.
The technical literature is subject to change without notice.
So, please contact SHARP or its representative before designing
your product based on this literature.
LK400D3HA
㧖㧖
DEVELOPMENT DEPARTMENT. 2
LIQUID CRYSTAL DISPLAY DIVISION.1
LIQUID CRYSTAL DISPLAY GROUP
SHARP CORPORATION
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RECORDS OF REVISION
LK400D3HA㧖㧖
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SPEC No. DATE
No. PAGE
LD-K22553 May. 21. 2010 - - - 1st. Issue
REVISED
SUMMARY NOTE
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1 Application
This specification applies to the color 40.0” TFT-LCD Open Cell LK400D3HA㧖㧖
With parts (FPC,C-PWB) to drive it.䯵
䯴
* These specification are proprietary products of SHARP CORPORATION (“SHARP”) and include materials
protected under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in any form or
by any means, electronic or mechanical, for any purpose, in whole or in part, without the express written
permission of SHARP.
* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,
automobiles, etc.), rescue and security equipment and various safety related equipment which require higher
reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant
system design should be taken.
* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for
life support.
* SHARP assumes no responsibility for any damage resulting from the use of the device that does not comply with
the instructions and the precautions specified in these specification.
* Contact and consult with a SHARP sales representative for any questions about this device.
2 Overview
This Open Cell is a color active matrix LCD Open-Cell incorporating amorphous silicon TFT (Thin Film Transistor).
It is composed of a color TFT-LCD panel, driver ICs and Source PWB. The following content can be achieved in
using LK0DZ1C0㧖㧖㧖(CONTROL PWBC-PWB) and LK0DZ1C0112 (FPC) that SHARP specifies. Graphics
and texts can be displayed on a 1920RGB1080 dots panel with one billion colors by using 10bit+ LVDS (L
V
oltage Differential Signaling) to interface, +12V of DC supply voltages.Graphics and texts can be displayed on a
1920RGB1080 dots panel with one billion colors by using 10bit+ LVDS (L
interface, +12V of DC supply voltages.
And in order to improve the response time of LCD, This C-PWB applies the Over Shoot driving (O/S driving)
technology for the control circuit .In the O/S driving technology, signals are being applied to the Liquid Crystal
according to a pre-fixed process as an image signal of the present frame when a difference is found between image
signal of the previous frame and that of the current frame after comparing them.
With combination of these technologies, motion blur can be reduced and clearer display performance can be realized.
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LD-K22553䙱1
ow
ow Voltage Differential Signaling) to
LK0DZ1C0㧖㧖㧖
LK0DZ1C0112
CN1
CONTROL PWB
Control Signals
FPC
SOURCE PWB
SOURCE DRIVER
GATE DRIVER
LCD PANEL
1920×3(RGB)×1080
LK400D3HA㧖㧖 (Open Cell)
CN2
CN3
Power Supply
Circuit
FPC
GATE DRIVER
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3 Mechanical Specifications
Parameter Specifications Unit
Display size
Active area 885.6H) x 498.15 (V) mm
Pixel Format
Pixel pitch 461.25(H) x 461.25 (V) um
Pixel configuration R, G, B vertical stripe
Display mode Normally black
Cell Outline Dimensions[Note1] 921.18(H) x 548.55(V) x 1.82(D) mm
Mass
Surface treatment [Note2]
(Upper Polarizing film)
Surface treatment [Note2]
(Lower Polarizing film)
[Note1] Outline dimensions are shown in P21.
[Note2] With the protection film removed.
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101.609 㧔Diagonal㧕
40.0 㧔Diagonal㧕
1920(H) x 1080(V)
㧔1pixel = R + G + B dot㧕
1.81 r0.3
Low-Haze Anti Glare
Hard coating : 2H and more
Plane
Hard coating :㧙
LD-K22553䙱2
cm
inch
pixel
kg
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4 Cell Driving Specifications
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LD-K22553䙱3
4.1
Driving interface of Control PWB SHARP specifies[
CN1 (Interface signals and +12V DC power supply)
Using connector : FI-RNE51SZ-HF (Japan Aviation Electronics Ind., Ltd.)
Matching connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind., Ltd.)
Matching LVDS transmitter : THC63LVD1023 or equivalent device
Pin No. S
1
2
3
4
5
6
7
8
9
10
11 GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
mbol Function Remark
GND
Reserved It is re
Reserved It is re
Reserved It is re
FRAME
O/S set O/S o
SELLVDS
Reserved
Reserved
Reserved
AIN0- A
AIN0+ A
AIN1- A
AIN1+ A
AIN2- A
AIN2+ A
GND
AC
ACK+ A
GND
AIN3- A
AIN3+ A
AIN4- A
AIN4+ A
GND
GND
BIN0- B
BIN0+ B
BIN1- B
BIN1+ B
BIN2- B
BIN2+ B
GND
BC
BCK+ B
GND
BIN3- B
BIN3+ B
BIN4- B
BIN4+ B
GND
GND
GND
GND
GND
VCC +12V Power Su
VCC +12V Power Su
VCC +12V Power Su
VCC +12V Power Su
VCC +12V Power Su
Frame fre
Select LVDS data orde
It is re
It is re
It is re
- Aport LVDS Clock signal(-
- Bport LVDS Clock signal(-
uired to set non-connection(OPEN
uired to set non-connection(OPEN
uired to set non-connection(OPEN
uency setting 0:120Hz 1:100Hz[Note 1
eration setting H:O/S ON, L:O/S OFF [Note 2] Pull up 3.3V
uired to set non-connection(OPEN
uired to set non-connection(OPEN
uired to set non-connection(OPEN
ort (-)LVDS CH0 differential data input
ort (+)LVDS CH0 differential data input
ort (-)LVDS CH1 differential data input
ort (+)LVDS CH1 differential data input
ort (-)LVDS CH2 differential data input
ort (+)LVDS CH2 differential data input
ort LVDS Clock signal(+
ort (-)LVDS CH3 differential data input
ort (+)LVDS CH3 differential data input
ort (-)LVDS CH4 differential data input
ort (+)LVDS CH4 differential data input
ort (-)LVDS CH0 differential data input
ort (+)LVDS CH0 differential data input
ort (-)LVDS CH1 differential data input
ort (+)LVDS CH1 differential data input
ort (-)LVDS CH2 differential data input
ort (+)LVDS CH2 differential data input
ort LVDS Clock signal(+
ort (-)LVDS CH3 differential data input
ort (+)LVDS CH3 differential data input
ort (-)LVDS CH4 differential data input
ort (+)LVDS CH4 differential data input
(Shown in Fig1)
Note 2,3
LK0DZ1C0
㧖㧖㧖]
Pull up 3.3V
Pull up 3.3V
Pull up 3.3V
Pull down :
Pull up 3.3V
Pull down : (GND
Pull down : (GND
Pull down : (GND
GND
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CN2 (Interface signals) (Shown in Fig1)
Using connector : FI-RNE41SZ-HF (Japan Aviation Electronics Ind., Ltd.)
Matching connector : FI-RE41HL, FI-RE41CL (Japan Aviation Electronics Ind., Ltd.)
Pin No. Symbol Function Remark
1
2
3
4
5
Reserved
Reserved
Reserved
VCC) (+12V Power Suppl
VCC) (+12V Power Suppl
VCC) (+12V Power Suppl
Reserved
Reserved
6 Reserved
7 Reserved
8 Reserved
9 GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
CIN0- C
CIN0+ C
CIN1- C
CIN1+ C
CIN2- C
CIN2+ C
GND
CC
- Cport LVDS Clock signal(-
CCK+ C
GND
CIN3- C
CIN3+ C
CIN4- C
CIN4+ C
GND
GND
DIN0- D
DIN0+ D
DIN1- D
DIN1+ D
DIN2- D
DIN2+ D
GND
DC
- Dport LVDS Clock signal(-
DCK+ D
GND
DIN3- D
DIN3+ D
DIN4- D
DIN4+ D
GND
GND
[Note] GND of parts drived a liquid crystal panel drive has connected with a module chassis.
[Note 1]The equivalent circuit figure of the terminal
Control PWB
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LD-K22553䙱4
ort (-)LVDS CH0 differential data input
ort (+)LVDS CH0 differential data input
ort (-)LVDS CH1 differential data input
ort (+)LVDS CH1 differential data input
ort (-)LVDS CH2 differential data input
ort (+)LVDS CH2 differential data input
ort LVDS Clock signal(+
ort (-)LVDS CH3 differential data input
ort (+)LVDS CH3 differential data input
ort (-)LVDS CH4 differential data input
ort (+)LVDS CH4 differential data input
ort (-)LVDS CH0 differential data input
ort (+)LVDS CH0 differential data input
ort (-)LVDS CH1 differential data input
ort (+)LVDS CH1 differential data input
ort (-)LVDS CH2 differential data input
ort (+)LVDS CH2 differential data input
ort LVDS Clock signal(+
ort (-)LVDS CH3 differential data input
ort (+)LVDS CH3 differential data input
ort (-)LVDS CH4 differential data input
ort (+)LVDS CH4 differential data input
100
Te rm in al
2.0K
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V
[Note 2]The equivalent circuit figure of the terminal
100
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LD-K22553䙱5
3.3
2.0K
[Note 3] LVDS Data order
Data L(GND)
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4 NA NA
TC5 NA NA
TC6 DE(*) DE(*)
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TE0
TE1
TE2
TE3
TE4
TE5
TE6
NA: Not Available
(*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE
signal during operation at ”High”.
SELLVDS
[VESA]
R0(LSB)㩷
R1㩷
R2㩷
R3㩷
R4㩷
R5㩷
G0(LSB)㩷
G1㩷
G2㩷
G3㩷
G4㩷
G5㩷
B0(LSB)㩷
B1㩷
B2㩷
B3㩷
B4㩷
B5㩷
R6㩷
R7㩷
G6㩷
G7㩷
B6㩷
B7㩷
N/A㩷
R8㩷
R9(MSB)㩷
G8㩷
G9(MSB)㩷
B8㩷
B9(MSB)㩷
N/A㩷
H(3.3V) or Open
[JEIDA]
R4
R5
R6
R7
R8
R9(MSB)
G4
G5
G6
G7
G8
G9(MSB)
B4
B5
B6
B7
B8
B9(MSB)
R2
R3
G2
G3
B2
B3
N/A
R0(LSB)
R1
G0(LSB)
G1
B0(LSB)
B1
N/A
Control PWB
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–
,
–
–
,
–
SELLVDS= Low (GND)
ACK+,BCK+
CCK+,DCK+
ACK– ,BCK–
CCK– ,DCK–
AIN0+,BIN0+
CIN0+,DIN0+
AIN0
–,BIN0–
CIN0–,DIN0–
AIN1+,BIN1+
CIN1+,DIN1+
AIN1
–,BIN1–
CIN1–,DIN1–
AIN2+,BIN2+
CIN2+,DIN2+
AIN2
–,BIN2–
CIN2–,DIN2–
AIN3+,BIN3+
CIN3+,DIN3+
AIN3
–,BIN3–
CIN3–,DIN3–
AIN4+,BIN4+
CIN4+,DIN4+
AIN4
–,BIN4–
CIN4
DIN4
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LD-K22553䙱6
1 cycle
G0 R5 R4 R3 R2 R1 R0 R0 R1 G0
B1 B0 G5 G4 G3 G2 G1 G1 G2 B1
DE
NA NA
B7 B6 G7 G6 R7 R6 R6 R7 NA NA
B9 B8 G9 G8 R9 R8 R8 R9 NA NA
B5 B4 B3 B2 B2 B3
DE
SELLVDS= High (3.3V) or OPEN
ACK+,BCK+
CCK+,DCK+
ACK– ,BCK–
CCK– ,DCK–
AIN0+,BIN0+
CIN0+,DIN0+
AIN0–,BIN0–
CIN0–,DIN0–
AIN1+,BIN1+
CIN1+,DIN1+
AIN1
CIN1–,DIN1–
AIN2+,BIN2+
CIN2+,DIN2+
–,BIN2–
AIN2
CIN2–,DIN2–
AIN3+,BIN3+
CIN3+,DIN3+
AIN3
CIN3–,DIN3–
AIN4+,BIN4+
CIN4+,DIN4+
–,BIN4–
AIN4
CIN4
–,BIN1–
–,BIN3–
DIN4
DE: Display Enable, NA: Not Available (Fixed Low)
1 cycle
G4 R9 R8 R7 R6 R5 R4 R4 R5 G4
B5 B4 G9 G8 G7 G6 G5 G5 G6 B5
DE
NA NA
B3 B2 G3 G2 R3 R2 R2 R3 NA NA
B1 B0 G1 G0 R1 R0 R0 R1 NA NA
B9 B8 B7 B6 B6 B7
DE
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