SHARP LH7A400 User Manual
LH7A400
Preliminary Data Sheet
FEATURES
• ARM922T™ Core:
– 32-bit ARM9TDMI™ RISC Core
– 16KB Cache: 8KB Instruction Cache and
8KB Data Cache
– MMU (Windows CE Enabled)
• High Performance (200 MHz)
• 80KB On-Chip Memory
• External Bus Interface
– 100 MHz
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Low Power Modes
– Run (147 mA), Halt (41 mA), Standby (42 µA)
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64,000 Colors and 15 Gray Shades
• DMA (10 Channels)
–AC97
–MMC
–USB
• USB Device Interface (USB 1.1)
• Synchronous Serial Port (SSP)
– Motorola SPI™
– Texas Instruments SSI
– National MICROWIRE™
32-Bit System-on-Chip
• Three Programmable Timers
• Three UARTs
– Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
• DC-to-DC Converters
• MultiMediaCard™ Interface
• AC97 Codec Interface
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 60 General Purpose I/Os
• Programmable Interrupt Controller
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– 1.8 V Core
– 3.3 V Input/Output (1.8 V I/O Optional
• 5 V Tolerant Inputs (except oscillator pins
• Operating Temperature
– 0°C to +70°C Commercial
– -40°C to +85°C Industrial (With Clock Frequency
Reduction
• 256-Ball PBGA or 256-Ball CABGA Package
1
)
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
This high degree of integration lowers overall sys-
tem costs, reduces development cycle time and accelerates product introduction.
1
)
2
)
Motorola SPI is a trademark of Motorola, Inc.
National Semiconductor MICROWIRE is a trademark of
National Semiconductor Corporation.
Windows CE is a trademark of Microsoft Corporation.
Preliminary Data Sheet 12/8/03 1
NOTES:
1. Under development. Results pending further characterization.
2. Oscillator pins R13, T13, P15, and P16 are 1.8 V ±10%
LH7A400 32-Bit System-on-Chip
14.7456 MHz 32.768 kHz
EXTERNAL
BUS
INTERFACE
(ASYNCHRONOUS)
CONTROLLER
PCMCIA/CF
CONTROLLER
SYNCHRONOUS
DYNAMIC RAM
CONTROLLER
LCD AHB
BUS
ARM922T
STATIC
MEMORY
(SMC)
(SDMC)
80KB
SRAM
OSCILLATOR,
PLL1 and PLL2, POWER
MANAGEMENT, and
RESET CONTROL
INTERRUPT
CONTROLLER
ADVANCED
PERIPHERAL
BUS BRIDGE
REAL TIME
CLOCK
WATCHDOG
TIMER
TIMER (3)
GENERAL
PURPOSE I/O
(60)
SYNCHRONOUS
SERIAL PORT
BATTERY
MONITOR
INTERFACE
UART (3)
IrDA
INTERFACE
USB DEVICE
INTERFACE
COLOR LCD
CONTROLLER
ADVANCED LCD
INTERFACE
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
Figure 1. LH7A400 Block Diagram
DMA
CONTROLLER
ADVANCED
PERPHERAL
BUS (APB)
MULTIMEDIACARD
INTERFACE
ADVANCED AUDIO
CODEC (AC97)
AUDIO CODEC
INTERFACE
SMART CARD
INTERFACE
(ISO7816)
DC to DC
INTERFACE
(2)
LH7A400-1
2 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 1. Functional Pin List
PBGA
CABGA
PIN
G7 C10
F1 F9
K7 F11
M1 F14
M5 G8
T6 H13
R14 J9
M14 K15
J11 L7
J12 N6
F13 N8
B14 N12
E10 N13
B8 P11
H7 B8
G3 C6
K4 D5
N5 D13
P6 E8
T14 F7
R16 G13
N16 H9
K13 J14
H9 K7
C15 L8
A11 L10
E8 L12
A5 M11
F7 M14
E1 C4
J4 D7
P3 D10
T8 F4
K9 F10
L13 J4
E15 J8
D12 K8
A7 L6
H5 G7
M3 H4
L9 H8
T10 L4
N15 L9
H12 N3
B15 N7
C9 N10
G6 R5
PIN
SIGNAL DESCRIPTION
VDD I/O Ring Power
VSS I/O Ring Ground
VDDC Core Power
VSSC Core Ground
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
Preliminary Data Sheet 12/8/03 3
LH7A400 32-Bit System-on-Chip
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
R11 P12
N12 M10
P12 R13
T11 N11
D3 E4 nPOR Power On Reset Input Input
H6 D1 nURESET
D4 E2 WAKEUP Wake Up Input (Sch mitt) Input
E4 F2 nPWRFL Power Fail Signal Input (Schmitt) Input
C2 D2 nEXTPWR External Power Input (Schmitt) Input
R13 R14 XTALIN
T13 R15 XTALOUT LOW LOW
P16 N14 XTAL32IN
P15 M13 XTAL32OUT Output Output
P14 M12 CLKEN External Oscillator Clock Enable Output LOW LOW 8 mA
J6 J5 PGMCLK Programmable Clock (14.7456 MHz MAX.) LOW LOW 8 mA
K11 P14 nCS0 Asynchronous Memory Chip Select 0 HIGH HIGH 12 mA
K10 P16 nCS1 Asynchronous Memory Chip Select 1 HIGH HIGH 12 mA
P13 N15 nCS2 Asynchronous Memory Chip Select 2 HIGH HIGH 12 mA
M12 N16
PIN
SIGNAL DESCRIPTION
VDDA Analog Power for PLL
VSSA Analog Ground for PLL
User Reset; should be pulled HIGH for normal or
JTAG operation.
14.7456 MHz Crystal Oscillator pins. An external
clock source can be connected to XTALIN leaving XTALOUT open.
32.768 kHz Real Time Clock Crystal Oscillator
pins. An external clock source can be connected
to XTAL32IN leaving XTAL32OUT open.
nCS3/
nMMSPICS
• Asynchronous Memory Chip Select 3
• MultiMediaCard SPI Mode Chip Select
RESET
STATE
Input (Schmitt) Input
Input Input
Input Input
HIGH: nCS3 HIGH 12 mA
STANDBY
STATE
OUTPUT
DRIVE
4 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
L12 L11 D0
M15 L13 D1
N13 L14 D2
L16 K11 D3
L15 L16 D4
L14 K14 D5
H11 J15 D6
K12 J12 D7
J15 J10 D8
J13 H16 D9
J10 H14 D10
H15 H11 D11
H13 G16 D12
G15 G9 D13
G11 G14 D14
G12 G12 D15
F15 F15 D16
F12 E15 D17
E14 D16 D18
D16 F12 D19
H10 E13 D20
D14 D14 D21
F10 E12 D22
A16 B16 D23
A14 D12 D24
B13 A16 D25
C13 B13 D26
E12 B14 D27
G10 C12 D28
B12 A14 D29
B11 B12 D30
D11 A12 D31
M16 M15 A0/nWE1
N14 M16 A1/nWE2
PIN
SIGNAL DESCRIPTION
RESET
STATE
Data Bus LOW LOW 12 mA
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 1
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 2
HIGH: nWE1 HIGH 12 mA
HIGH: nWE2 HIGH 12 mA
STANDBY
STATE
OUTPUT
DRIVE
Preliminary Data Sheet 12/8/03 5
LH7A400 32-Bit System-on-Chip
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
M13 L15 A2/SA0
K16 K12 A3/SA1 LOW LOW 12 mA
K15 K13 A4/SA2 LOW LOW 12 mA
K14 K16 A5/SA3 LOW LOW 12 mA
J8 J13 A6/SA4 LOW LOW 12 mA
J16 J11 A7/SA5 LOW LOW 12 mA
J14 J16 A8/SA6 LOW LOW 12 mA
J9 H15 A9/SA7 LOW LOW 12 mA
H16 H10 A10/SA8 LOW LOW 12 mA
H14 H12 A11/SA9 LOW LOW 12 mA
G16 G15 A12/SA10 LOW LOW 12 mA
G14 G10 A13/SA11 LOW LOW 12 mA
G13 G11 A14/SA12 LOW LOW 12 mA
F16 F16 A15/SA13 LOW LOW 12 mA
F14 E16 A16/SB0
E16 F13 A17/SB1
E13 E14 A18
F11 D15 A19
D15 C16 A20
C16 C15 A21
B16 C14 A22
A15 B15 A23
A13 E11 A24
G8 D8 A25/SCIO
F8 B7 A26/SCCLK
A8 A7 A27/SCRST
D8 C8 nOE Asynchronous Memory Output Enable HIGH HIGH 12 mA
C8 F8 nWE0 Asynchronous Memory Write Byte Enable 0 HIGH HIGH 12 mA
D10 D9 nWE3 Asynchronous Memory Write Byte Enable 3 HIGH HIGH 8 mA
B10 E9 CS6/SCKE1_2
C10 A10 CS7/SCKE0
G9 A11 SCKE3 Synchronous Memory Clock Enable 3 LOW LOW 12 mA
A10 B10 SCLK Synchronous Memory Clock LOW LOW
C14 C13 nSCS0 Synchronous Memory Chip Select 0 HIGH HIGH 12 mA
D13 A15 nSCS1 Synchronous Memory Chip Select 1 HIGH HIGH 12 mA
E11 D11 nSCS2 Synchronous Memory Chip Select 2 HIGH HIGH 12 mA
A12 E10 nSCS3 Synchronous Memory Chip Select 3 HIGH HIGH 12 mA
C12 A13 nSWE Synchronous Memory Write Enable HIGH HIGH 12 mA
C11 B11 nCAS
PIN
SIGNAL DESCRIPTION
• Asynchronous Address Bus
• Synchronous Address Bus
• Asynchronous Address Bus
• Synchronous Device Bank Address 0
• Asynchronous Address Bus
• Synchronous Device Bank Address 1
Asynchronous Address Bus LOW LOW 12 mA
• Asynchronous Memory Address Bus
• Smart Card Interface I/O (Data)
• Asynchronous Memory Address Bus
• Smart Card Interface Clock
• Asynchronous Memory Address Bus
• Smart Card Interface Reset
• Asynchronous Memory Chip Select 6
• Synchronous Memory Clock Enable 1 OR 2
• Asynchronous Memory Chip Select 7
• Synchronous Memory Clock Enable 0
Synchronous Memory Column Address
Strobe Signal
RESET
STATE
LOW LOW 12 mA
LOW LOW 12 mA
LOW LOW 12 mA
LOW: A25 LOW 12 mA
LOW: A26 LOW 12 mA
LOW: A27 LOW 12 mA
LOW: CS6 LOW 12 mA
LOW: CS7 LOW 12 mA
HIGH HIGH 12 mA
STANDBY
STATE
OUTPUT
DRIVE
20 mA
(sink)
12 mA
(source)
6 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
F9 C11 nRAS Synchronous Memory Row Address Strobe Signal HIGH HIGH 12 mA
A9 C9 DQM0 Synchronous Memory Data Mask 0 HIGH HIGH 12 mA
B9 A9 DQM1 Synchronous Memory Data Mask 1 HIGH HIGH 12 mA
D9 B9 DQM2 Synchronous Memory Data Mask 2 HIGH HIGH 12 mA
E9 A8 DQM3 Synchronous Memory Data Mask 3 HIGH HIGH 12 mA
J5 K1 PA0/LCDVD16
K1 K2 PA1/LCDVD17
K2 K3 PA2
K3 K4 PA3
K5 K6 PA4
L1 K5 PA5
L2 L1 PA6
L3 L2 PA7
L4 L3 PB0/UARTRX1
L5 M1 PB1/UARTTX3
L7 M2 PB2/UARTRX3
M2 M3
M4 L5
N1 N1
N2 N2
N3 M4 PB7/SMBCLK
P1 P1 PC0/UARTTX1
P2 P2 PC1/LCDPS
R1 R1
K6 M5 PC3/LCDREV
L8 P3 PC4/LCDSPS
T1 N4 PC5/LCDCLS
PIN
SIGNAL DESCRIPTION
• GPIO Port A
• LCD Data bit 16. This CLCDC output signal is
always LOW.
• GPIO Port A
• LCD Data bit 17. This CLCDC output signal is
always LOW.
GPIO Port A Input No Change 8 mA
• GPIO Port B
• UART1 Receive Data Input
• GPIO Port B
• UART3 Transmit Data Out
• GPIO Port B
• UART3 Receive Data In
PB3/
UARTCTS3
PB4/
UARTDCD3
PB5/
UARTDSR3
PB6/SWID/
SMBD
PC2/
LCDVDDEN
• GPIO Port B
• UART3 Clear to Send
• GPIO Port B
• UART3 Data Carrier Detect
• GPIO Port B
• UART3 Data Set Ready
• GPIO Port B
• Single Wire Data
• Smart Battery Data
• GPIO Port B
• Smart Battery Clock
• GPIO Port C
• UART1 Transmit Data Output
• GPIO Port C
• HR-TFT Power Save
• GPIO Port C
• HR-TFT Power Sequence Control
• GPIO Port C
• HR-TFT Gray Scale Voltage Reverse
• GPIO Port C
• HR-TFT Reset Row Driver Counter
• GPIO Port C
• HR-TFT Row Driver Clock
RESET
STATE
Input: PA0 No Change 8 mA
Input: PA1 No Change 8 mA
Input: PB0 No Change 8 mA
Input: PB1
Input: PB2 No Change 8 mA
Input: PB3 No Change 8 mA
Input: PB4 No Change 8 mA
Input: PB5 No Change 8 mA
Input: PB6
Input: PB7
LOW: PC0 No Change 12 mA
LOW: PC1 No Change 12 mA
LOW: PC2 No Change 12 mA
LOW: PC3 No Change 12 mA
LOW: PC4 No Change 12 mA
LOW: PC5 No Change 12 mA
STANDBY
STATE
LOW if
UART3 is
Enabled,
otherwise
No Change
Input if SMB
is Enabled,
otherwise
No Change
Input if SMB
is Enabled,
otherwise
No Change
OUTPUT
DRIVE
8 mA
8 mA
8 mA
Preliminary Data Sheet 12/8/03 7
LH7A400 32-Bit System-on-Chip
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
T2 R2 PC6/LCDHRLP
R2 N5 PC7/LCDSPL
M11 M9 PD0/LCDVD8
L11 K10 PD1/LCDVD9 LOW: PD1
K8 P10 PD2/LCDVD10 LOW: PD2
N11 T11 PD3/LCDVD11 LOW: PD3
R9 T12 PD4/LCDVD12 LOW: PD4
T9 R11 PD5/LCDVD13 LOW: PD5
P10 R12 PD6/LCDVD14 LOW: PD6
R10 T13 PD7/LCDVD15 LOW: PD7
L10 T9 PE0/LCDVD4
N10 K9 PE1/LCDVD5 Input: PE1
M9 T10 PE2/LCDVD6 Input: PE2
M10 R10 PE3/LCDVD7 Input: PE3
A6 A5 PF0/INT0
B6 B4 PF1/INT1
C6 E7 PF2/INT2
H8 B3 PF3/INT3
B5 C5
D6 D6
E6 A4
C5 A3
R3 M6 PG0/nPCOE
T3 T1 PG1/nPCWE
PIN
SIGNAL DESCRIPTION
• GPIO Port C
• LCD Latch Pulse
• GPIO Port C
• LCD Start Pulse Left
• GPIO Port D
• LCD Video Data Bus
• GPIO Port E
• LCD Video Data Bus
• GPIO Port F
• External FIQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• GPIO Port F
• External IRQ Interrupts. Interrupts can be level
or edge triggered and are internally debounced.
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• GPIO Port F
PF4/INT4/
SCVCCEN
PF5/INT5/
SCDETECT
PF6/INT6/
PCRDY1
PF7/INT7/
PCRDY2
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• Smart Card Supply Voltage Enable
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• Smart Card Detection
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• Ready for Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• Ready for Card 2 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port G
• Output Enable for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port G
• Write Enable for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
RESET
STATE
LOW: PC6 No Change 12 mA
LOW: PC7 No Change 12 mA
LOW: PD0
Input: PE0 LOW if 8-bit
Input: PF0
(Schmitt)
Input: PF1
(Schmitt)
Input: PF2
(Schmitt)
Input: PF3
(Schmitt)
Input: PF4
(Schmitt)
Input: PF5
(Schmitt)
Input: PF6
(Schmitt)
Input: PF7
(Schmitt)
LOW: PG0 No Change 8 mA
LOW: PG1 No Change 8 mA
STANDBY
STATE
LOW if
Dual-Panel
LCD is
Enabled;
otherwise,
No Change
LCD is
Enabled,
otherwise
No Change
No Change 8 mA
No Change 8 mA
No Change 8 mA
No Change 8 mA
LOW if SCI
is Enabled;
otherwise,
No Change
No Change 8 mA
No Change 8 mA
No Change 8 mA
OUTPUT
DRIVE
12 mA
12 mA
8 mA
8 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
L6 P4 PG2/nPCIOR
M6 R3 PG3/nPCIOW
N6 T2 PG4/nPCREG
M7 P5 PG5/nPCCE1
M8 R4 PG6/nPCCE2
N4 T3 PG7/PCDIR
P4 P6
R4 T4
T4 M7
N7 T5
P8 R6
P5 R7
PIN
SIGNAL DESCRIPTION
PH0/
PCRESET1
PH1/CFA8/
PCRESET2
PH2/
nPCSLOTE1
PH3/CFA9/
PCMCIAA25/
nPCSLOTE2
PH4/
nPCWAIT1
PH5/CFA10/
PCMCIAA24/
nPCWAIT2
• GPIO Port G
• I/O Read Strobe for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port G
• I/O Write Strobe for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port G
• Register Memory Access for PC Card (PCMCIA
or CompactFlash) in single or dual card mode
• GPIO Port G
• Card Enable 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal and nPCCE2 are used by the PC
Card for decoding low and high byte accesses.
• GPIO Port G
• Card Enable 2 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal and nPCCE1 are used by the PC
Card for decoding low and high byte accesses.
• GPIO Port G
• Direction for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port H
• Reset Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• GPIO Port H
• Address Bit 8 for PC Card (CompactFlash) in
single card mode
• Reset Card 2 for PC Card (PCMCIA or
CompactFlash) in dual card mode
• GPIO Port H
• Enable Card 1 for PC Card (PCMCIA or
CompactFlash) in single or dual card mode.
This signal is used for gating other control signals to the appropriate PC Card.
• GPIO Port H
• Address Bit 9 for PC Card (CompactFlash) in
single card mode
• Address Bit 25 for PC Card (PCMCIA) in single
card mode
• Enable Card 2 for PC Card (PCMCIA or
CompactFlash) in dual card mode. This signal
is used for gating other control signals to the
appropriate PC Card.
• GPIO Port H
• WAIT Signal for Card 1 for PC Card (PCMCIA
or CompactFlash) in single or dual card mode
• GPIO Port H
• Address Bit 10 for PC Card (CompactFlash) in
single card mode
• Address Bit 24 for PC Card (PCMCIA) in single
card mode
• WAIT Signal f o r Ca r d 2 for PC Card (PCMCIA
or CompactFlash) in dual card mode
RESET
STATE
LOW: PG2 No Change 8 mA
LOW: PG3 No Change 8 mA
LOW: PG4 No Change 8 mA
LOW: PG5 No Change 8 mA
LOW: PG6 No Change 8 mA
LOW: PG7 No Change 8 mA
Input: PH0 No Change 8 mA
Input: PH1 No Change 8 mA
Input: PH2 No Change 8 mA
Input: PH3 No Change 8 mA
Input: PH4 No Change 8 mA
Input: PH5 No Change 8 mA
STANDBY
STATE
OUTPUT
DRIVE
Preliminary Data Sheet 12/8/03 9
LH7A400 32-Bit System-on-Chip
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
R5 P7
T5 T6
R6 T7 LCDFP LCD Frame Synchronization pulse LOW LOW 12 mA
R8 R9 LCDLP LCD Line Synchronization pulse LOW LOW 12 mA
P9 P9
N9 N9 LCDDCLK LCD Data Clock LOW LOW 12 mA
P7 M8 LCDVD0
R7 P8 LCDVD1
T7 R8 LCDVD2
N8 T8 LCDVD3
T15 T16 USBDP USB Data Positive (Differential Pair) Input Input
T16 R16 USBDN USB Data Negative (Differential Pair) Input Input
E7 C7 nPWME0
D7 A6 nPWME1
C7 B6 PWM0
B7 B5 PWM1
C4 A2 ACBITCLK
D5 A1 ACOUT
B4 B2 ACSYNC
A4 E6 ACIN
A3 C3
B3 B1
A2 D4
E2 E1 UARTCTS2
E3 F3 UARTDCD2
E5 G4 UARTDSR2 UART2 Data Set Ready Signal Input Input
F2 G5 UARTIRTX1 IrDA Transmit LOW LOW 8 mA
F3 G6 UARTIRRX1
F4 F1 UARTTX2 UART2 Transmit Data Output HIGH HIGH 8 mA
PIN
SIGNAL DESCRIPTION
PH6/
AC97RESET
PH7/nPCSTATRE
LCDENAB/
LCDM
MMCCLK/
MMSPICLK
MMCCMD/
MMSPIDIN
MMCDATA/
MMSPIDOUT
• GPIO Port H
• Audio Codec (AC97) Reset
• GPIO Port H
• Status Read Enable for PC Card (PCMCIA or
CompactFlash) in single or dual card mode
• LCD TFT Data Enable
• LCD STN AC Bias
LCD Video Data Bus LOW LOW 12 mA
DC-DC Converter Pulse Width
Modulator 0 Enable
DC-DC Converter Pulse Width
Modulator 1 Enable
DC-DC Converter Pulse Width
Modulator 0 Output during normal operation and
Polarity Selection input at reset
DC-DC Converter Pulse Width
Modulator 1 Output during normal operation and
Polarity Selection input at reset
• Audio Codec (AC97) Clock
• Audio Codec (ACI) Clock
• Audio Codec (AC97) Output
• Audio Codec (ACI) Output
• Audio Codec (AC97) Synchronization
• Audio Codec (ACI) Synchronization
• Audio Codec (AC97) Input
• Audio Codec (ACI) Input
• MultiMediaCard Clock (20 MHz MAX.)
• MultiMediaCard SPI Mode Clock
• MultiMediaCard Command
• MultiMediaCard SPI Mode Data Input
• MultiMediaCard Data
• MultiMediaCard SPI Mode Data Output
UART2 Clear to Send Signal. This pin is an output for JTAG boundary scan only.
UART2 Data Carrier Detect Signal. This pin is output for JTAG boundary scan only.
IrDA Receive. This pin is an output for JTAG
boundary scan only.
RESET
STATE
Input: PH6 No Change 8 mA
Input: PH7 No Change 8 mA
LOW:
LCDENAB
Input Input
Input Input
Input Input 8 mA
Input Input 8 mA
Input Input
LOW LOW 8 mA
LOW LOW 8 mA
Input Input
LOW:
MMCCLK
Input:
MMCCMD
Input:
MMCDATA
Input Input
Input Input
Input Input
STANDBY
STATE
LOW 12 mA
LOW 8 mA
Input 8 mA
Input 8 mA
OUTPUT
DRIVE
75 mA
(NOM.)
75 mA
(NOM.)
10 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 1. Functional Pin List (Cont’d)
PBGA
CABGA
PIN
J7 G3 UARTRX2
H4 J3 SSPCLK Synchronous Serial Port Clock LOW LOW 8 mA
J1 J6 SSPRX Synchronous Serial Port Receive Input Input
J2 J7 SSPTX Synchronous Serial Port Transmit LOW LOW 8 mA
J3 J2
F6 G2 COL0
F5 G1 COL1
G1 H3 COL2
G2 H5 COL3
G4 H6 COL4
G5 H7 COL5
H1 H2 COL6
H2 H1 COL7
H3 J1 TBUZ Timer Buzzer (254 kHz MAX.) LOW LOW 8 mA
C3 F5 MEDCHG
P11 T14 WIDTH0
R12 T15 WIDTH1
D1 E3 BATOK Battery OK Input (Schmitt) Input
D2 F6 nBATCHG Battery Change Input (Schmitt) Input
A1 E5 TDI
B1 C2 TCK
B2 D3 TDO
C1 C1 TMS
T12 P15 nTEST0
R15 P13 nTEST1
PIN
SIGNAL DESCRIPTION
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
SSPFRM/
nSSPFRM
Synchronous Serial Port Frame Sync
Keyboard Interface HIGH HIGH 8 mA
Boot Device Media Change. Used with the
WIDTH0 and WIDTH1 pins to specify boot memory device.
External Memory Width Pins. Also, used with
MEDCHG to specify the boot memory device size.
JTAG Data In. This signal is internally pulled-up
to VDD.
JTAG Clock. This signal should be externally
pulled-up to VDD.
JTAG Data Out. This signal should be externally
pulled up to VDD with a 33 k
JTAG Test Mode select. This signal is internally
pulled-up to VDD.
Test Pin 0. Internally pulled up to VDD. For Normal
mode, leave open. For JTAG mode, tie to GND.
See Table 2.
Test Pin 1. internally pulled up to VDD. For Normal
and JTAG mode, leave open. See Table 2.
Ω resistor.
RESET
STATE
Input Input
Input:
nSSPFRM
Input (Schmitt) Input
Input (Schmitt) Input
Input with
Pull-up
Input Input
Input No Change 4 mA
Input with
Pull-up
Input with
Pull-up
Input with
Pull-up
STANDBY
STATE
Input 8 mA
Input with
Pull-up
Input with
Pull-up
Input with
Pull-up
Input with
Pull-up
OUTPUT
DRIVE
NOTES: *Signals beginning with ‘n’ are Active LOW.
Table 2. nTest Pin Function
MODE nTEST0 nTEST1 nURESET
JTAG 0 1 1
Normal 1 1 x
Preliminary Data Sheet 12/8/03 11
LH7A400 32-Bit System-on-Chip
Table 3. LCD Data Multiplexing
STN
PBGA
CABGA
PIN
K1 K2 LCDVD17 LOW
J5 K1 LCDVD16 LOW
R10 T13 LCDVD15 MLSTN7 CLSTN7 Intensity Intensity
P10 R12 LCDVD14 MLSTN6 CLSTN6 BLUE4 BLUE4
T9 R11 LCDVD13 MLSTN5 CLSTN5 BLUE3 BLUE3
R9 T12 LCDVD12 MLSTN4 CLSTN4 BLUE2 BLUE2
N11 T11 LCDVD11 MLSTN3 CLSTN3 BLUE1 BLUE1
K8 P10 LCDVD10 MLSTN2 CLSTN2 BLUE0 BLUE0
L11 K10 LCDVD9 MLSTN1 CLSTN1 GREEN4 GREEN4
M11 M9 LCDVD8 MLSTN0 CLSTN0 GREEN3 GREEN3
M10 R10 LCDVD7 MLSTN3 MUSTN7 MUSTN7 CUSTN7 CUSTN7 GREEN2 GREEN2
M9 T10 LCDVD6 MLSTN2 MUSTN6 MUSTN6 CUSTN6 CUSTN6 GREEN1 GREEN1
N10 K9 LCDVD5 MLSTN1 MUSTN5 MUSTN5 CUSTN5 CUSTN5 GREEN0 GREEN0
L10 T9 LCDVD4 MLSTN0 MUSTN4 MUSTN4 CUSTN4 CUSTN4 RED4 RED4
N8 T8 LCDVD3 MUSTN3 MUSTN3 MUSTN3 MUSTN3 CUSTN3 CUSTN3 RED3 RED3
T7 R8 LCDVD2 MUSTN2 MUSTN2 MUSTN2 MUSTN2 CUSTN2 CUSTN2 RED2 RED2
R7 P8 LCDVD1 MUSTN1 MUSTN1 MUSTN1 MUSTN1 CUSTN1 CUSTN1 RED1 RED1
P7 M8 LCDVD0 MUSTN0 MUSTN0 MUSTN0 MUSTN0 CUSTN0 CUSTN0 RED0 RED0
PIN
LCD
DATA
SIGNAL
MONO 4-BIT MONO 8-BIT COLOR
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
TFT
AD-TFT/
HR-TFT
NOTES:
1. The Intensity bit is identically generated for all three colors.
2. MU = Monochrome Upper
3. CU = Color Upper
4. CL = Color Lower
12 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 4. 256-Ball PBGA Package Numerical Pin List
BGA PIN SIGNAL RESET STATE STANDBY STATE
A1 TDI Input with Pull-up Input with Pull-up
A2 MMCDATA/MMSPIDOUT Input: MMSPIDOUT LOW
A3 MMCCLK/MMSPICLK LOW: MMSPICLK LOW
A4 ACIN Input Input
A5 VSS
A6 PF0/INT0 Input: PF0 No Change
A7 VDDC
A8 A27/SCRST LOW: A27 LOW
A9 DQM0 HIGH LOW
A10 SCLK LOW LOW
A11 VSS
A12 nSCS3 HIGH HIGH
A13 A24 LOW LOW
A14 D24 LOW LOW
A15 A23 LOW LOW
A16 D23 LOW LOW
B1 TCK Input Input
B2 TDO Input No Change
B3 MMCCMD/MMSPIDIN Input: MMSPIDIN LOW
B4 ACSYNC LOW LOW
B5 PF4/INT4/SCVCCEN Input: PF4 LOW if SCI is Enabled; otherwise, No Change
B6 PF1/INT1 Input: PF1 No Change
B7 PWM1 Input Input
B8 VDD
B9 DQM1 HIGH LOW
B10 CS6/SCKE1_2 LOW: CS6 LOW
B11 D30 LOW LOW
B12 D29 LOW LOW
B13 D25 LOW LOW
B14 VDD
B15 VSSC
B16 A22 LOW LOW
C1 TMS Input with Pull-up Input with Pull-up
C2 nEXTPWR Input Input
C3 MEDCHG Input Input
C4 ACBITCLK Input Input
C5 PF7/INT7/PCRDY2 Input: PF7 No Change
C6 PF2/INT2 PF2/INT2 No Change
C7 PWM0 Input Input
C8 nWE0 HIGH HIGH
C9 VSSC
C10 CS7/SCKE0 LOW: CS7 LOW
C11 nCAS HIGH HIGH
C12 nSWE HIGH HIGH
C13 D26 LOW LOW
Preliminary Data Sheet 12/8/03 13
LH7A400 32-Bit System-on-Chip
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d)
BGA PIN SIGNAL RESET STATE STANDBY STATE
C14 nSCS0 HIGH HIGH
C15 VSS
C16 A21 LOW LOW
D1 BATOK Input Input
D2 nBATCHG Input Input
D3 nPOR Input Input
D4 WAKEUP Input Input
D5 ACOUT LOW LOW
D6 PF5/INT5/SCDETECT Input: PF5 No Change
D7 nPWME1 Input Input
D8 nOE HIGH HIGH
D9 DQM2 HIGH LOW
D10 nWE3 HIGH HIGH
D11 D31 LOW LOW
D12 VDDC
D13 nSCS1 HIGH HIGH
D14 D21 LOW LOW
D15 A20 LOW LOW
D16 D19 LOW LOW
E1 VDDC
E2 UARTCTS2 Input Input
E3 UARTDCD2 Input Input
E4 nPWRFL Input Input
E5 UARTDSR2 Input Input
E6 PF6/INT6/PCRDY1 Input: PF6 No Change
E7 nPWME0 Input Input
E8 VSS
E9 DQM3 HIGH LOW
E10 VDD
E11 nSCS2 HIGH HIGH
E12 D27 LOW LOW
E13 A18 LOW LOW
E14 D18 LOW LOW
E15 VDDC
E16 A17/SB1 LOW: SBANK1 LOW
F1 VDD
F2 UARTIRTX1 LOW LOW
F3 UARTIRRX1 Input Input
F4 UARTTX2 HIGH HIGH
F5 COL1 HIGH HIGH
F6 COL0 HIGH HIGH
F7 VSS
F8 A26/SCCLK LOW: A26 LOW
F9 nRAS HIGH HIGH
F10 D22 LOW LOW
14 12/8/03 Preliminary Data Sheet
32-Bit System-on-Chip LH7A400
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d)
BGA PIN SIGNAL RESET STATE STANDBY STATE
F11 A19 LOW LOW
F12 D17 LOW LOW
F13 VDD
F14 A16/SB0 LOW: SBANK0 LOW
F15 D16 LOW LOW
F16 A15/SA13 LOW: SA13 LOW
G1 COL2 HIGH HIGH
G2 COL3 HIGH HIGH
G3 VSS
G4 COL4 HIGH HIGH
G5 COL5 HIGH HIGH
G6 VSSC
G7 VDD
G8 A25/SCIO LOW: A25 LOW
G9 SCKE3 LOW LOW
G10 D28 LOW LOW
G11 D14 LOW LOW
G12 D15 LOW LOW
G13 A14/SA12 LOW: SA12 LOW
G14 A13/SA11 LOW: SA11 LOW
G15 D13 LOW LOW
G16 A12/SA10 LOW: SA10 LOW
H1 COL6 HIGH HIGH
H2 COL7 HIGH HIGH
H3 TBUZ LOW LOW
H4 SSPCLK LOW LOW
H5 VSSC
H6 nURESET Input Input
H7 VSS
H8 PF3/INT3 Input: PF3 No Change
H9 VSS
H10 D20 LOW LOW
H11 D6 LOW LOW
H12 VSSC
H13 D12 LOW LOW
H14 A11/SA9 LOW: SA9 LOW
H15 D11 LOW LOW
H16 A10/SA8 LOW: SA8 LOW
J1 SSPRX Input Input
J2 SSPTX LOW LOW
J3 SSPFRM/nSSPFRM Input: nSSPFRM Input
J4 VDDC
J5 PA0/LCDVD16 Input: PA0 No Change
J6 PGMCLK LOW LOW
J7 UARTRX2 Input Input
Preliminary Data Sheet 12/8/03 15
LH7A400 32-Bit System-on-Chip
Table 4. 256-Ball PBGA Package Numerical Pin List (Cont’d)
BGA PIN SIGNAL RESET STATE STANDBY STATE
J8 A6/SA4 LOW: SA4 LOW
J9 A9/SA7 LOW: SA7 LOW
J10 D10 LOW LOW
J11 VDD
J12 VDD
J13 D9 LOW LOW
J14 A8/SA6 LOW: SA6 LOW
J15 D8 LOW LOW
J16 A7/SA5 LOW: SA5 LOW
K1 PA1/LCDVD17 Input: PA1 No Change
K2 PA2 Input No Change
K3 PA3 Input No Change
K4 VSS
K5 PA4 Input No Change
K6 PC3/LCDREV LOW: PC3 No Change
K7 VDD
K8 PD2/LCDVD10 LOW: PD2
K9 VDDC
K10 nCS1 HIGH HIGH
K11 nCS0 HIGH HIGH
K12 D7 LOW LOW
K13 VSS
K14 A5/SA3 LOW: SA3 LOW
K15 A4/SA2 LOW: SA2 LOW
K16 A3/SA1 LOW: SA1 LOW
L1 PA5 Input No Change
L2 PA6 Input No Change
L3 PA7 Input No Change
L4 PB0/UARTRX1 Input: PB0 No Change
L5 PB1/UARTTX3 Input: PB1 LOW if UART3 is Enabled, otherwise No Change
L6 PG2/nPCIOR LOW: PG2 No Change
L7 PB2/UARTRX3 Input: PB2 No Change
L8 PC4/LCDSPS LOW: PC4 No Change
L9 VSSC
L10 PE0/LCDVD4 Input: PE0 LOW if 8-bit LCD is Enabled, otherwise No Change
L11 PD1/LCDVD9 LOW: PD1
L12 D0 LOW LOW
L13 VDDC
L14 D5 LOW LOW
L15 D4 LOW LOW
L16 D3 LOW LOW
M1 VDD
M2 PB3/UARTCTS3 Input: PB3 No Change
M3 VSSC
LOW if Dual-Panel LCD is Enabled; otherwise,
No Change
LOW if Dual-Panel LCD is Enabled; otherwise,
No Change
16 12/8/03 Preliminary Data Sheet
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