Sharp LH79524, LH79525 User Manual

LH79524/LH79525

User’s Guide

Version 1.0

Specifications are subject to change without notice.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.

Purchase of I Companies conveys a license under the Philips I components in an I

C components from SHARP Corporation or one of its sublicensed Associated

C system, provided that the system conforms to the I2C Standard Specification

C Patent. Rights are granted to use these

as defined by Philips.

Preface

Conventions and Terms......................................................................................xxxv

Unconnected (Floating) Inputs........................................................................xxxv

Multiplexed Pins ..............................................................................................xxxv

Pin Names......................................................................................................xxxvi

Peripheral Devices .........................................................................................xxxvi

Numeric Values.............................................................................................xxxviii

Block Diagrams .............................................................................................xxxviii

What’s in This User’s Guide......................................................................................xl

Chapter 1 – Overview............................................................................................xl

Chapter 2 – ADC and Brownout Detector.............................................................xl

Chapter 3 – Boot Controller...................................................................................xl

Chapter 4 – Color LCD Controller .........................................................................xl

Chapter 5 – DMA Controller..................................................................................xl

Chapter 6 – Ethernet MAC....................................................................................xl

Chapter 7 – External Memory Controller..............................................................xli

Chapter 8 – General Purpose Input/Output..........................................................xli

Chapter 9 – I2C Interface.....................................................................................xli

Chapter 10 – I2S Converter .................................................................................xli

Chapter 11 – I/O Configuration ............................................................................xli

Chapter 12 – Real Time Clock .............................................................................xli

Chapter 13 – Reset, Clock Generation and Power Control..................................xli

Chapter 14 – Synchronous Serial Port.................................................................xli

Chapter 15 – Timers............................................................................................xlii

Chapter 16 – UARTs...........................................................................................xlii

Chapter 17 – USB Device ...................................................................................xlii

Chapter 18 – Vectored Interrupt Controller .........................................................xlii

Chapter 19 – Watchdog Timer............................................................................xlii

Appendix – Glossary ...........................................................................................xlii

Chapter 1 – Overview

1.1 Bus Architecture...............................................................................................1-3

1.2 Power Supply...................................................................................................1-3

1.2.1 Linear Regulator........................................................................................1-3

1.2.2 Phase Locked Loop Power .......................................................................1-3

1.3 Clock Strategy..................................................................................................1-4

1.3.1 Bus Clocking Modes..................................................................................1-6

1.3.1.1 Standard Bus Clocking Modes...........................................................1-6

1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes......................1-7

1.3.1.3 Fastbus Extension Bus Clocking Mode..............................................1-7

1.4 Reset Strategy..................................................................................................1-8

1.4.1 Resetting the Test Access Port Controller ................................................1-9

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1.4.2 Hardware Requirements at Reset...........................................................1-10

1.4.2.1 Floating Inputs..................................................................................1-10

1.4.2.2 Test Pins...........................................................................................1-10

1.4.2.3 Active Pull Ups .................................................................................1-11

1.5 AHB Bus Master Priority and Arbitration........................................................1-12

1.6 Memory Interface Architecture.......................................................................1-12

1.7 Instruction and Data Cache............................................................................1-17

1.8 Memory Management Unit (MMU).................................................................1-17

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

2.1 Theory of Operation .........................................................................................2-1

2.1.1 Operational Summary ...............................................................................2-1

2.1.2 Bias-and-Control Network.........................................................................2-3

2.1.3 Clock Generator........................................................................................2-5

2.1.4 Brownout Detector.....................................................................................2-5

2.1.5 SAR Architecture.......................................................................................2-5

2.1.6 Battery Control Feature.............................................................................2-7

2.1.7 Timing Formulas........................................................................................2-8

2.1.8 Interrupts...................................................................................................2-8

2.1.8.1 Brownout Interrupt..............................................................................2-8

2.1.8.2 Pen Interrupt.......................................................................................2-9

2.1.8.3 End-of-Sequence Interrupt.................................................................2-9

2.1.8.4 FIFO Watermark Interrupt ..................................................................2-9

2.1.8.5 FIFO Overrun Interrupt.......................................................................2-9

2.1.9 Application Details.....................................................................................2-9

2.2 Register Reference ........................................................................................2-10

2.2.1 Memory Map ...........................................................................................2-10

2.2.2 Register Descriptions ..............................................................................2-11

2.2.2.1 High Word Register (HW).................................................................2-11

2.2.2.2 Low Word Register (LW)..................................................................2-13

2.2.2.3 Results Register (RR).......................................................................2-14

2.2.2.4 Interrupt Mask Register (IM).............................................................2-15

2.2.2.5 Power Configuration Register (PC)..................................................2-16

2.2.2.6 General Configuration Register (GC)...............................................2-18

2.2.2.7 General Status Register (GS)...........................................................2-19

2.2.2.8 Interrupt Status Register (IS)............................................................2-20

2.2.2.9 FIFO Status Register (FS)................................................................2-21

2.2.2.10 Control Bank Registers...................................................................2-22

2.2.2.11 Idle High Word Register (IHWCTRL)..............................................2-23

2.2.2.12 Idle Low Word Register (ILWCTRL)...............................................2-24

2.2.2.13 Masked Interrupt Status Register (MIS).........................................2-25

2.2.2.14 Interrupt Clear Register (IC)...........................................................2-26

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Chapter 3 – Boot Controller

3.1 Theory of Operation .........................................................................................3-2

3.1.1 Boot Device Determination........................................................................3-2

3.1.1.1 NAND Flash Operation.......................................................................3-4

3.1.2 Hardware Design Considerations..............................................................3-4

3.1.2.1 Active Pullups To Signal Boot Mode ..................................................3-4

3.1.2.2 NAND Flash Hardware Design...........................................................3-5

3.1.3 Booting Using the I2C Interface ................................................................3-6

3.1.4 Booting from UART ...................................................................................3-7

3.2 Register Reference ..........................................................................................3-7

3.2.1 Memory Map .............................................................................................3-7

3.2.2 Register Definitions ...................................................................................3-8

3.2.2.1 Power-up Boot Configuration Register (PBC)....................................3-8

3.2.3 nCS1 Override Register (CS1OV).............................................................3-9

3.2.4 External Peripheral Mapping Register (EPM) .........................................3-10

Chapter 4 – Color Liquid Crystal Display Controller

4.1 Introduction.......................................................................................................4-1

4.1.1 LCD Panel Architecture.............................................................................4-2

4.2 CLCDC Features..............................................................................................4-3

4.3 Theory of Operation .........................................................................................4-3

4.3.1 Supported Displays and Panels................................................................4-5

4.3.2 Frame Buffer .............................................................................................4-5

4.3.3 LCD DMA FIFOs .......................................................................................4-5

4.3.4 Pixel Serializer...........................................................................................4-6

4.3.5 How Pixels are Stored in Memory.............................................................4-6

4.3.6 Palette RAM ..............................................................................................4-8

4.3.6.1 Grayscale Algorithm...........................................................................4-9

4.3.6.2 Interrupts ............................................................................................4-9

4.3.6.3 LCD Panel Resolutions ......................................................................4-9

4.3.7 LCD Data Multiplexing.............................................................................4-12

4.3.8 LCD Interface Timing Signals..................................................................4-13

4.3.8.1 LCD Horizontal Timing Signals.........................................................4-13

4.3.8.2 LCD Vertical Timing Signals.............................................................4-14

4.3.9 LCD Power Sequencing at Turn-On and Turn-Off..................................4-15

4.3.9.1 Minimizing a Retained Image on the LCD........................................4-16

4.3.10 Interrupts...............................................................................................4-16

4.4 Advanced LCD Interface................................................................................4-17

4.4.1 ALI Theory of Operation..........................................................................4-18

4.4.2 ALI Operating Modes ..............................................................................4-18

4.4.2.1 Bypass Mode....................................................................................4-18

4.4.2.2 Active Mode......................................................................................4-18

4.5 CLCDC Register Reference...........................................................................4-19

4.5.1 Enabling the CLCDC...............................................................................4-19

4.5.2 CLCDC Memory Map..............................................................................4-19

4.5.3 CLCDC Register Descriptions.................................................................4-20

4.5.3.1 Horizontal Timing Panel Control Register (TIMING0) ......................4-20

4.5.3.2 Vertical Timing Panel Control Register (TIMING1)...........................4-22

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4.5.3.3 Clock and Signal Polarity Control Register (TIMING2).....................4-24

4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE)........4-26

4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) ........4-27

4.5.3.6 Interrupt Enable Register (INTREN).................................................4-28

4.5.3.7 CLCDC Control Register (CTRL) .....................................................4-29

4.5.3.8 Raw Interrupt Status Register (STATUS) .........................................4-32

4.5.3.9 Masked Interrupt Status Register (INTERRUPT).............................4-33

4.5.3.10 Interrupt Clear Register (INTCLR) ..................................................4-34

4.5.3.11 LCD Upper Panel and Lower Panel Frame Buffer Current

Address Register (UPCURR and LPCURR) ............................................4-35

4.5.3.12 256 × 16-bit Color Palette Register (PALETTE).............................4-36

4.5.4 ALI Register Reference...........................................................................4-38

4.5.5 ALI Memory Map.....................................................................................4-38

4.5.6 ALI Register Descriptions........................................................................4-38

4.5.6.1 Setup Register (ALISETUP).............................................................4-38

4.5.6.2 Control Register (ALICTRL) .............................................................4-39

4.5.6.3 Timing Delay Register 1 (ALITIMING1)............................................4-40

4.5.6.4 Timing Delay Register 2 (ALITIMING2)............................................4-41

4.6 Timing Waveforms .........................................................................................4-42

4.6.1 STN Horizontal Timing ............................................................................4-42

4.6.2 STN Vertical Timing ................................................................................4-42

4.6.3 TFT Horizontal Timing.............................................................................4-42

4.6.4 TFT Vertical Timing.................................................................................4-42

4.6.5 AD-TFT/HR-TFT Horizontal Timing Waveforms......................................4-42

4.6.6 AD-TFT/HR-TFT Vertical Timing Waveforms..........................................4-42

Chapter 5 – Direct Memory Access Controller

5.1 Theory Of Operation.........................................................................................5-2

5.1.1 Use for SSP and UART.............................................................................5-3

5.1.2 Changing Mode from Memory to Peripheral .............................................5-3

5.1.3 Interrupt, Error, and Status Registers........................................................5-4

5.1.3.1 Interrupts ............................................................................................5-4

5.1.4 External DMA Handshake Signal Timing..................................................5-4

5.2 Register Reference ..........................................................................................5-5

5.2.1 Memory Map .............................................................................................5-5

5.2.2 Register Definitions ...................................................................................5-6

5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI)....................5-6

5.2.2.2 Destination Base Registers (DESTLO and DESTHI).........................5-7

5.2.2.3 Maximum Count Register (MAX)........................................................5-8

5.2.2.4 Control Register (CTRL).....................................................................5-9

5.2.2.5 Current Source Registers (CURSHI and CURSLO).........................5-12

5.2.2.6 Current Destination Registers (CURDHI and CURDLO)..................5-13

5.2.2.7 Terminal Count Register (TCNT)......................................................5-14

5.2.2.8 Interrupt Mask Register (MASK).......................................................5-15

5.2.2.9 Interrupt Clear Register (CLR)..........................................................5-16

5.2.2.10 Status Register (STATUS) .............................................................5-17

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Chapter 6 – Ethernet MAC Controller

6.1 Theory of Operation .........................................................................................6-2

6.1.1 Operational Overview................................................................................6-3

6.1.1.1 Setup..................................................................................................6-4

6.1.1.2 Statistics.............................................................................................6-4

6.1.1.3 Detailed Descriptions..........................................................................6-4

6.1.2 Memory Interface ......................................................................................6-4

6.1.2.1 FIFO ...................................................................................................6-4

6.1.2.2 Receive Buffers..................................................................................6-4

6.1.2.3 Transmit Buffer...................................................................................6-7

6.1.3 Receive Block............................................................................................6-9

6.1.4 Transmit Block...........................................................................................6-9

6.1.4.1 Pause Frame Support ......................................................................6-10

6.1.5 Address Checking Block .........................................................................6-11

6.1.5.1 Broadcast Address...........................................................................6-12

6.1.5.2 Hash Addressing..............................................................................6-12

6.1.5.3 Copy All Frames (Promiscuous Mode).............................................6-12

6.1.5.4 Type ID Checking.............................................................................6-13

6.1.5.5 VLAN Support...................................................................................6-13

6.2 Programming Model.......................................................................................6-13

6.2.1 Initialization..............................................................................................6-14

6.2.1.1 Receive Buffer List ...........................................................................6-14

6.2.1.2 Transmit Buffer List ..........................................................................6-16

6.2.1.3 Transmitting Frames.........................................................................6-16

6.2.1.4 Local Loop Back Mode.....................................................................6-16

6.2.1.5 PHY Maintenance.............................................................................6-17

6.2.1.6 Interrupts ..........................................................................................6-17

6.3 Register Reference ........................................................................................6-18

6.3.1 Memory Map ...........................................................................................6-18

6.3.2 Control, Configuration, And Status Register Definitions..........................6-20

6.3.2.1 Network Control Register (NETCTL)................................................6-20

6.3.2.2 Network Configuration Register (NETCONFIG)...............................6-22

6.3.2.3 Network Status Register (NETSTATUS)..........................................6-24

6.3.2.4 Transmit Status Register (TXSTATUS)............................................6-25

6.3.2.5 Receive Buffer Queue Pointer (RXBQP) ..........................................6-27

6.3.2.6 Transmit Buffer Queue Pointer (TXBQP).........................................6-28

6.3.2.7 Receive Status Register (RXSTATUS) ............................................6-29

6.3.2.8 Interrupt Status Register (INSTATUS) .............................................6-30

6.3.2.9 Interrupt Enable Register (ENABLE)................................................6-32

6.3.2.10 Interrupt Disable Register (DISABLE)............................................6-33

6.3.2.11 Interrupt Mask Register (MASK).....................................................6-34

6.3.2.12 PHY Maintenance Register (PHYMAINT)......................................6-35

6.3.2.13 Pause Time Register (PAUSETIME)..............................................6-36

6.3.2.14 Transmit Pause Quantum (TXPAUSEQUAN)................................6-36

6.3.3 Statistics Register Definitions..................................................................6-37

6.3.3.1 Pause Frames Received (PAUSEFRRX).........................................6-37

6.3.3.2 Frames Transmitted OK (FRMTXOK)..............................................6-38

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6.3.3.3 Single Collision Frames (SINGLECOL)............................................6-38

6.3.3.4 Multiple Collision Frames (MULTFRM) ............................................6-39

6.3.3.5 Frames Received OK (FRMRXOK)..................................................6-39

6.3.3.6 Frame Check Sequence Errors (FRCHK)........................................6-40

6.3.3.7 Alignment Errors (ALIGNERR).........................................................6-40

6.3.3.8 Deferred Transmission Frames (DEFTXFRM).................................6-41

6.3.3.9 Late Collisions (LATECOL) ..............................................................6-41

6.3.3.10 Excessive Collisions (EXCOL) .......................................................6-42

6.3.3.11 Transmit Underrun Errors (TXUNDER)..........................................6-42

6.3.3.12 Carrier Sense Errors (SENSERR)..................................................6-43

6.3.3.13 Receive Resource Errors (RXRERR).............................................6-44

6.3.3.14 Receive Overrun Errors (RXOVERR).............................................6-44

6.3.3.15 Receive Symbol Errors (RXSYMERR)...........................................6-45

6.3.3.16 Excessive Length Error Register (LENERR)..................................6-45

6.3.3.17 Receive Jabbers (RXJAB)..............................................................6-46

6.3.3.18 Undersize Frames (UNDERFRM)..................................................6-46

6.3.3.19 SQE Test Errors (SQERR).............................................................6-47

6.3.3.20 Received Length Field Mismatch (RXLEN)....................................6-47

6.3.3.21 Transmitted Pause Frames (TXPAUSEFM)...................................6-48

6.3.4 Matching Registers..................................................................................6-49

6.3.4.1 Hash Register Bottom (HASHBOT)..................................................6-49

6.3.4.2 Hash Register Top (HASHTOP).......................................................6-49

6.3.4.3 Specific Address 1 Bottom (SPECAD1BOT)....................................6-50

6.3.4.4 Specific Address 1 Top (SPECAD1TOP).........................................6-50

6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT)....................................6-51

6.3.4.6 Specific Address 2 Top (SPECAD2TOP).........................................6-51

6.3.4.7 Specific Address 3 Bottom (SPECAD3BOT)....................................6-52

6.3.4.8 Specific Address 3 Top (SPECAD3TOP).........................................6-52

6.3.4.9 Specific Address 4 Bottom (SPECAD4BOT)....................................6-53

6.3.4.10 Specific Address 4 Top (SPECAD4TOP).......................................6-53

6.3.4.11 Type ID Checking (IDCHK) ............................................................6-54

Chapter 7 – External Memory Controller

7.1 Theory of Operation .........................................................................................7-1

7.1.1 External Memory Map ...............................................................................7-3

7.1.1.1 nCS1 Memory Configuration..............................................................7-3

7.2 Static Memory ..................................................................................................7-3

7.2.1 Static Memory Operation...........................................................................7-3

7.2.2 Hardware Design.......................................................................................7-5

7.2.2.1 Address Connectivity..........................................................................7-5

7.2.3 Software Design........................................................................................7-9

7.2.3.1 Simple Shifting Subroutine.................................................................7-9

7.2.4 Static Memory Device Selection..............................................................7-10

7.2.4.1 Static Memory Timing Control..........................................................7-10

7.2.4.2 Bus Turnaround................................................................................7-16

7.2.4.3 Byte Lane Control.............................................................................7-16

7.2.4.4 Write Protection................................................................................7-16

7.2.4.5 nWAIT Transfers ..............................................................................7-16

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7.2.4.6 Extended Wait Transfers..................................................................7-17

7.3 Interfacing with NAND Flash..........................................................................7-17

7.3.1 Booting Example .....................................................................................7-17

7.3.2 General NAND Flash Access..................................................................7-20

7.3.2.1 Transaction Example........................................................................7-20

7.3.2.2 16-bit Example Transaction..............................................................7-21

7.3.2.3 Address Examples............................................................................7-21

7.4 Dynamic Memory ...........................................................................................7-22

7.4.1 Write-protection.......................................................................................7-22

7.4.2 Access Sequencing and Memory Width..................................................7-22

7.4.3 Bus Address Mapping .............................................................................7-22

7.4.4 Data Mask Signals ..................................................................................7-27

7.5 Register Reference ........................................................................................7-28

7.5.1 Memory Map ...........................................................................................7-28

7.5.2 Register Definitions .................................................................................7-30

7.5.2.1 Control Register (CONTROL)...........................................................7-30

7.5.2.2 Status Register (STATUS) ...............................................................7-31

7.5.2.3 Configuration Register (CONFIG) ....................................................7-32

7.5.2.4 Dynamic Memory Control Register (DYNMCTRL)...........................7-33

7.5.2.5 Dynamic Refresh Register (DYNMREF) ..........................................7-34

7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON).......7-35

7.5.2.7 Dynamic Precharge Command Period Register (PRECHARGE) ....7-36

7.5.2.8 Dynamic Memory Active to Precharge Command Period

7.5.2.9 Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)........7-38

7.5.2.10 Dynamic Memory Last Data Out to Active Time

7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE).....7-40

7.5.2.12 Dynamic Memory Write Recovery Time Register (DWRT) ............7-41

7.5.2.13 Dynamic Memory Active to Active Command

Period Register (DYNACTCMD) ..............................................................7-42

7.5.2.14 Dynamic Memory Auto-Refresh Period, and Auto-Refresh

to Active Command Period Register (DYNAUTO) ...................................7-43

7.5.2.15 Dynamic Memory Exit Self-Refresh to Active Command

Time Register (DYNREFEXIT).................................................................7-44

7.5.2.16 Dynamic Memory Active Bank A to Active Bank B

Time Register (DYNACTIVEAB) ..............................................................7-45

7.5.2.17 Dynamic Memory Load Mode Register to

Active Command Time Register (DYNAMICTMRD) ................................7-46

7.5.2.18 Static Memory Extended Wait Register (WAIT) .............................7-47

7.5.2.19 Dynamic Configuration Register for nDCS0

and nDCS1 (DYNCFGx)...........................................................................7-48

7.5.2.20 Dynamic Memory RAS and CAS Delay Register for

nDCS0 and nDCS1 (DYNRASCASx).......................................................7-51

7.5.2.21 Static Memory Configuration Register (SCONFIGx)......................7-52

7.5.2.22 Static Memory Write Enable Delay Registers (SWAITWENx)........7-54

7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx)......7-55

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7.5.2.24 Static Memory Read Delay Registers (SWAITRDx).......................7-56

7.5.2.25 Static Memory Page Mode Read Delay Registers

(SWAITPAGEx)........................................................................................7-57

7.5.2.26 Static Memory Write Delay Registers (SWAITWRx)......................7-58

7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)................7-59

Chapter 8 – General Purpose Input/Output

8.1 Theory of Operation .........................................................................................8-1

8.1.1 Port Configuration .....................................................................................8-1

8.1.1.1 Multiplexing.........................................................................................8-2

8.2 Register Reference ..........................................................................................8-7

8.2.1 Memory Map .............................................................................................8-7

8.2.2 Register Descriptions ................................................................................8-8

8.2.2.1 Port A/C/E/G/I/K/M Data Registers (P1DRx)......................................8-8

8.2.2.2 Port B/D/F/H/J/L/N Data Register (P2DRx)........................................8-9

8.2.2.3 Port A/C/E/G/I/K Data Direction Register (P1DDRx)........................8-10

8.2.2.4 Port B/D/F/H/L/N Data Direction Register ........................................8-11

Chapter 9 – I2C Module

9.1 Theory of Operation .........................................................................................9-2

9.1.1 Setting I

9.1.2 Interrupt Handling......................................................................................9-4

9.1.3 Slave Mode ...............................................................................................9-5

9.1.4 Master Mode .............................................................................................9-5

9.1.5 Resetting a Locked Slave..........................................................................9-5

9.2 Register Reference ..........................................................................................9-6

9.2.1 Memory Map .............................................................................................9-6

9.2.2 Register Definitions ...................................................................................9-7

9.2.2.1 I

9.2.2.2 I

9.2.2.3 I

9.2.2.4 I

9.2.2.5 I

9.2.2.6 I

9.2.2.7 I

C Clock Timing ...........................................................................9-3

C Configuration Register (ICCON)...................................................9-7

C Slave Address Register (ICSAR) .................................................9-8

C Upper Slave Address Register (ICUSAR)....................................9-9

C Data Register (ICDATA)...............................................................9-9

C Clock High Time Register (ICHCNT)..........................................9-10

C Clock Low Time Register (ICLCNT)...........................................9-10

C Status Register (ICSTAT)...........................................................9-11

Chapter 10 – I2S Converter

10.1 Theory of Operation .....................................................................................10-3

10.1.1 Conversion ............................................................................................10-3

10.1.2 Driving/Latching Edges .........................................................................10-4

10.1.3 Transmission.........................................................................................10-5

10.1.3.1 Master Mode Transmission............................................................10-5

10.1.3.2 Slave Mode Transmission..............................................................10-6

10.1.4 Reception ..............................................................................................10-7

10.1.4.1 Master Mode Reception .................................................................10-7

10.1.4.2 Slave Mode Reception ...................................................................10-9

10.1.5 Suppression of SSPFSSIN..................................................................10-10

10.1.6 Channel Management.........................................................................10-10

10.1.7 Interrupts.............................................................................................10-11

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10.1.7.1 SSP Protocol Error Interrupt.........................................................10-11

10.1.7.2 External Codec Protocol Error Interrupt .......................................10-11

10.1.7.3 Transmit FIFO Underrun Interrupt................................................10-11

10.1.7.4 Receive Interrupt..........................................................................10-12

10.1.7.5 Transmit Interrupt.........................................................................10-12

10.1.7.6 Receive Overrun Interrupt............................................................10-12

10.1.7.7 Receive Timeout Interrupt............................................................10-12

10.1.7.8 I

SINTR........................................................................................10-12

10.2 Register Reference ....................................................................................10-13

10.2.1 Memory Map .......................................................................................10-13

10.2.2 Register Descriptions..........................................................................10-14

10.2.2.1 Control Register (CTRL)...............................................................10-14

10.2.2.2 Status Register (STAT) ................................................................10-16

10.2.2.3 Interrupt Mask Set or Clear Register (IMSC)................................10-17

10.2.2.4 Raw Interrupt Status Register (RIS).............................................10-18

10.2.2.5 Masked Interrupt Status Register (MIS).......................................10-19

10.2.2.6 Interrupt Clear Register (ICR).......................................................10-20

Chapter 11 – I/O Configuration

11.1 Theory of Operation .....................................................................................11-1

11.2 Register Reference ......................................................................................11-2

11.2.1 Memory Map .........................................................................................11-2

11.2.2 Register Definitions...............................................................................11-4

11.2.2.1 Multiplexing Control 1 Register (MUXCTL1) ..................................11-4

11.2.2.2 Resistor Configuration Control 1 Register (RESCTL1) ..................11-5

11.2.2.3 Multiplexing Control 3 Register (MUXCTL3) ..................................11-6

11.2.2.4 Resistor Configuration Control 3 Register (RESCTL3) ..................11-6

11.2.2.5 Multiplexing Control 4 Register (MUXCTL4) ..................................11-7

11.2.2.6 Resistor Configuration Control 4 Register (RESCTL4) ..................11-8

11.2.2.7 Multiplexing Control 5 Register (MUXCTL5) ..................................11-9

11.2.2.8 Resistor Configuration Control 5 Register (RESCTL5) ................11-10

11.2.2.9 Multiplexing Control 6 Register (MUXCTL6) ................................11-12

11.2.2.10 Resistor Configuration Control 6 Register (RESCTL6) ..............11-13

11.2.2.11 Multiplexing Control 7 Register (MUXCTL7) ..............................11-14

11.2.2.12 Resistor Configuration Control 7 Register (RESCTL7) ..............11-16

11.2.2.13 Multiplexing Control 10 Register (MUXCTL10) ..........................11-18

11.2.2.14 Resistor Configuration Control 10 Register (RESCTL10)..........11-20

11.2.2.15 Multiplexing Control 11 Register (MUXCTL11) ..........................11-22

11.2.2.16 Resistor Configuration Control 11 Register (RESCTL11)..........11-24

11.2.2.17 Multiplexing Control 12 Register (MUXCTL12) ..........................11-26

11.2.2.18 Resistor Configuration Control 12 Register (RESCTL12)..........11-27

11.2.2.19 Resistor Configuration Control 13 Register (RESCTL13)..........11-29

11.2.2.20 Multiplexing Control 14 Register (MUXCTL14) ..........................11-30

11.2.2.21 Multiplexing Control 15 Register (MUXCTL15) ..........................11-32

11.2.2.22 Resistor Configuration Control 15 Register (RESCTL15)..........11-32

11.2.2.23 Resistor Configuration Control 17 Register (RESCTL17)..........11-33

11.2.2.24 Multiplexing Control 19 Register (MUXCTL19) ..........................11-34

11.2.2.25 Resistor Configuration Control 19 Register (RESCTL19)..........11-36

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11.2.2.26 Multiplexing Control 20 Register (MUXCTL20) ..........................11-38

11.2.2.27 Resistor Configuration Control 20 Register (RESCTL20)..........11-40

11.2.2.28 Multiplexing Control 21 Register (MUXCTL21) ..........................11-42

11.2.2.29 Resistor Configuration Control 21 Register (RESCTL21)..........11-43

11.2.2.30 Multiplexing Control 22 Register (MUXCTL22) ..........................11-44

11.2.2.31 Resistor Configuration Control 22 Register (RESCTL22)..........11-46

11.2.2.32 Multiplexing Control 23 Register (MUXCTL23) ..........................11-48

11.2.2.33 Resistor Configuration Control 23 Register (RESCTL23)..........11-50

11.2.2.34 Multiplexing Control 24 Register (MUXCTL24) ..........................11-52

11.2.2.35 Resistor Configuration Control 24 Register (RESCTL24)..........11-53

11.2.2.36 Multiplexing Control 25 Register (MUXCTL25) ..........................11-54

Chapter 12 – Real Time Clock

12.1 Theory of Operation .....................................................................................12-1

12.1.1 Configuring the RTC for Use.................................................................12-2

12.2 Register Reference ......................................................................................12-3

12.2.1 Memory Map .........................................................................................12-3

12.2.2 Register Descriptions............................................................................12-3

12.2.2.1 Data Register (DR).........................................................................12-3

12.2.2.2 Match Register (MR) ......................................................................12-4

12.2.2.3 Load Register (LR).........................................................................12-4

12.2.2.4 Control Register (CR).....................................................................12-5

12.2.2.5 Interrupt Mask Set or Clear Register (IMSC)..................................12-5

12.2.2.6 Raw Interrupt Status Register (RIS)...............................................12-6

12.2.2.7 Masked Interrupt Status Register (MIS).........................................12-6

12.2.2.8 Interrupt Clear Register (ICR).........................................................12-7

Chapter 13 – Reset, Clock, and Power Controller

13.1 Theory of Operation .....................................................................................13-2

13.1.1 System PLL and USB PLL Reset..........................................................13-3

13.1.2 Reset Generation..................................................................................13-3

13.1.3 Clock Generation...................................................................................13-3

13.1.3.1 Enabling Clocks Prior to Programming Registers ..........................13-3

13.1.3.2 Peripheral Block Clocks..................................................................13-4

13.1.3.3 External Clock Generation (CLKOUT)............................................13-4

13.1.4 Power Modes ........................................................................................13-6

13.1.4.1 Active Mode....................................................................................13-6

13.1.4.2 Standby Mode ................................................................................13-6

13.1.4.3 Sleep Mode ....................................................................................13-6

13.1.4.4 Stop1 Mode....................................................................................13-6

13.1.4.5 Stop2 Mode....................................................................................13-7

13.1.4.6 Power Control in JTAG Mode.........................................................13-7

13.2 Register Reference ......................................................................................13-8

13.2.1 Memory Map .........................................................................................13-8

13.2.2 Register Descriptions............................................................................13-8

13.2.2.1 Control Register (CTRL).................................................................13-9

13.2.2.2 Identification Register (CHIPID)...................................................13-10

13.2.2.3 Remap Control Register (REMAP)...............................................13-11

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13.2.2.4 Software Reset Register (SOFTRESET)......................................13-14

13.2.2.5 Reset Status Register (RSTSTATUS)..........................................13-15

13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR).........................13-16

13.2.2.7 System Clock Prescaler Register (SYSCLKPRE)........................13-17

13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE)............................13-18

13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0).....................13-19

13.2.2.10 Peripheral Clock Control Register 1 (PCLKCTRL1)...................13-20

13.2.2.11 AHB Clock Control Register (AHBCLKCTRL)............................13-21

13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0).......................13-22

13.2.2.13 Peripheral Clock Select Register 1 (PCLKSEL1).......................13-23

13.2.2.14 Silicon Revision Register (SILICONREV)...................................13-24

13.2.2.15 LCD Clock Prescaler Register (LCDPRE)..................................13-25

13.2.2.16 SSP Clock Prescaler Register (SSPPRE)..................................13-26

13.2.2.17 ADC Clock Prescaler Register (ADCPRE).................................13-27

13.2.2.18 USB Clock Prescaler Register (USBPRE) .................................13-28

13.2.2.19 External Interrupt Configuration Register (INTCONFIG)............13-29

13.2.2.20 External Interrupt Clear Register (INTCLR)................................13-31

13.2.2.21 Core Clock Configuration Register (CORECONFIG).................13-32

13.2.2.22 System PLL Control Register (SYSPLLCTL) .............................13-33

13.2.2.23 USB PLL Control Register (USBPLLCTL)..................................13-34

Chapter 14 – Synchronous Serial Port

14.1 Theory of Operation .....................................................................................14-1

14.1.1 Timing Waveforms ................................................................................14-3

14.1.2 Motorola SPI Frame Format..................................................................14-4

14.1.3 Texas Instruments Frame Format.........................................................14-5

14.1.4 National Semiconductor Frame Format ................................................14-6

14.1.5 Clock Generation...................................................................................14-7

14.1.6 Interrupts...............................................................................................14-7

14.1.6.1 Receive Interrupt............................................................................14-7

14.1.6.2 Transmit Interrupt...........................................................................14-8

14.1.6.3 Receive Overrun Interrupt..............................................................14-8

14.1.6.4 Receive Timeout Interrupt..............................................................14-8

14.1.6.5 SSPINTR........................................................................................14-8

14.2 Register Reference ......................................................................................14-9

14.2.1 Memory Map .........................................................................................14-9

14.2.2 Register Descriptions..........................................................................14-10

14.2.2.1 Control Register 0 (CTRL0)..........................................................14-10

14.2.2.2 Control Register 1 (CTRL1)..........................................................14-12

14.2.2.3 Data Register – Receive/Transmit FIFO Register (DR)...............14-13

14.2.2.4 Status Register (SR).....................................................................14-14

14.2.2.5 Clock Prescale Register (CPSR)..................................................14-15

14.2.2.6 Interrupt Mask Set and Clear Register (IMSC).............................14-16

14.2.2.7 Raw Interrupt Status Register (RIS).............................................14-17

14.2.2.8 Masked Interrupt Status Register (MIS).......................................14-18

14.2.2.9 Interrupt Clear Register (ICR).......................................................14-19

14.2.2.10 DMA Control Register (DCR) .....................................................14-20

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Chapter 15 – Timers

15.1 Theory of Operation .....................................................................................15-2

15.1.1 Counter Clear Upon Compare Match....................................................15-3

15.1.2 Capture Signal Sampling.......................................................................15-4

15.1.3 PWM Mode............................................................................................15-4

15.1.3.1 Timer Interrupts..............................................................................15-5

15.2 Register Reference ......................................................................................15-6

15.2.1 Memory Map .........................................................................................15-6

15.2.2 Register Descriptions............................................................................15-7

15.2.2.1 Timer 0 Control Register (CTRL0)..................................................15-7

15.2.2.2 Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0) 15-8

15.2.2.3 Timer 0 Interrupt Control Register (INTEN0)................................15-10

15.2.2.4 Timer 0 Status Register (STATUS0)............................................15-11

15.2.2.5 Timer 0 Counter Register (CNT0) ................................................15-12

15.2.2.6 Timer 0 Compare Registers (T0CMPn)........................................15-13

15.2.2.7 Timer 0 Capture Registers (CAPn)...............................................15-14

15.2.2.8 Timer 1 Control Register (CTRL1)................................................15-15

15.2.2.9 Timer 1 Interrupt Control Register (INTEN1)................................15-17

15.2.2.10 Timer 1 Status Register (STATUS1)..........................................15-18

15.2.2.11 Timer 1 Counter Register (CNT1) ..............................................15-19

15.2.2.12 Timer 1 Compare Registers (T1CMPn)......................................15-20

15.2.2.13 Timer 1 Capture Registers (T1CAPn) ........................................15-21

15.2.2.14 Timer 2 Control Register (CTRL2)..............................................15-22

15.2.2.15 Timer 2 Interrupt Control Register (INTEN2)..............................15-24

15.2.2.16 Timer 2 Status Register (STATUS2)..........................................15-25

15.2.2.17 Timer 2 Counter Register (CNT2) ..............................................15-26

15.2.2.18 Timer 2 Compare Registers (T2CMPn)......................................15-27

15.2.2.19 Timer 2 Capture Registers (T2CAPn) ........................................15-28

Chapter 16 – UARTs

16.1 Theory of Operation .....................................................................................16-2

16.1.1 Transmitting Data..................................................................................16-3

16.1.2 Receive Data Frame .............................................................................16-3

16.1.3 Nine-bit Mode........................................................................................16-4

16.1.4 Status Conditions ..................................................................................16-4

16.1.5 On-Chip DMA Capabilities ....................................................................16-5

16.1.6 Programming the SIR............................................................................16-5

16.1.7 Hardware Flow Control..........................................................................16-6

16.1.7.1 RTS Flow Control...........................................................................16-6

16.1.7.2 CTS Flow Control...........................................................................16-6

16.1.8 Programming Control Registers............................................................16-6

16.2 Interrupts......................................................................................................16-7

16.2.1 UARTINTR ............................................................................................16-7

16.3 Register Reference ......................................................................................16-7

16.3.1 Memory Map .........................................................................................16-7

16.3.2 Register Definitions...............................................................................16-8

16.3.2.1 Data Register (UARTDR)...............................................................16-8

16.3.2.2 Receive Status/Error Clear Register (UARTRSR/UARTECR).......16-9

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16.3.2.3 Flag Register (UARTFR)..............................................................16-11

16.3.2.4 IrDA Low-Power Counter Register (UARTILPR)..........................16-12

16.3.2.5 Integer Baud Rate Divisor Register (UARTIBRD)........................16-13

16.3.2.6 Fractional Baud Rate Divisor Register (UARTFBRD) ..................16-14

16.3.2.7 Line Control Register (UARTLCR_H)...........................................16-15

16.3.2.8 UART Control Register (UARTCR) ..............................................16-17

16.3.2.9 Interrupt FIFO Level Select Register (UARTIFLS).......................16-19

16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC)........................16-20

16.3.2.11 Raw Interrupt Status Register (UARTRIS).................................16-22

16.3.2.12 Masked Interrupt Status Register (UARTMIS) ...........................16-24

16.3.2.13 Interrupt Clear Register (UARTICR)...........................................16-26

16.3.2.14 UART0 DMA Control Register (DMACTRL)...............................16-27

Chapter 17 – Universal Serial Bus Device

17.1 Theory of Operation .....................................................................................17-1

17.1.1 Endpoints ..............................................................................................17-2

17.1.1.1 Isochronous Endpoints...................................................................17-3

17.1.2 FIFOs ....................................................................................................17-3

17.1.3 Serial Interface Engine (SIE).................................................................17-3

17.1.3.1 OUT_PKT_RDY Interrupt Operation for Endpoint 0.......................17-3

17.1.4 DMA Interface .......................................................................................17-4

17.1.4.1 DMA Modes....................................................................................17-4

17.1.4.2 DMA Bus Cycles.............................................................................17-4

17.1.4.3 Bus Errors.......................................................................................17-4

17.1.5 DMA Operation......................................................................................17-5

17.1.5.1 DMA Mode 0: OUT Endpoints........................................................17-5

17.1.5.2 DMA Mode 0: IN Endpoints............................................................17-5

17.1.5.3 DMA Mode 1: OUT Endpoints........................................................17-6

17.1.5.4 DMA Mode 1: IN Endpoints............................................................17-7

17.1.6 Remote Wakeup....................................................................................17-7

17.2 Register Reference ......................................................................................17-8

17.2.1 Memory Map .........................................................................................17-8

17.2.2 Register Definitions.............................................................................17-10

17.2.2.1 Function Address Register (FAR).................................................17-10

17.2.2.2 Power Management Register (PMR)............................................17-11

17.2.2.3 Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR).......................17-12

17.2.2.4 Interrupt Register for OUT Endpoint 1 and 2 (OIR)......................17-13

17.2.2.5 Interrupt Register for common USB interrupts (UIR)....................17-14

17.2.2.6 IN Interrupt Enable Register (IIE).................................................17-15

17.2.2.7 OUT Interrupt Enable Register (OIE) ...........................................17-16

17.2.2.8 Interrupt Enable Register (UIE)....................................................17-17

17.2.2.9 Frame Number Registers (FRAMEx) ...........................................17-18

17.2.3 Indexed Registers ...............................................................................17-19

17.2.3.1 Index Register (INDEX)................................................................17-19

17.2.3.2 IN Maximum Packet Size Register (INMAXP)..............................17-20

17.2.3.3 Control Status Register for EP 0 (CSR0) .....................................17-21

17.2.3.4 Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1)...........17-23

17.2.3.5 Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2)...........17-25

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17.2.3.6 OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)...17-26

17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR 1)..17-27

17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2) . ..17-29

17.2.3.9 Count 0 Register (OUTCOUNT0).................................................17-30

17.2.3.10 Count 1 Register (OUTCOUNT1)...............................................17-30

17.2.3.11 Out Count 2 Register (OUTCOUNT2)........................................17-31

17.2.3.12 FIFOs for Endpoints 0-3 (FIFOx)................................................17-31

17.2.3.13 Pending DMA Interrupts Register (INTR)...................................17-32

17.2.3.14 DMA Channel x Control Register (CNTLx).................................17-33

17.2.3.15 DMA Channel x AHB Memory Address Register.......................17-34

17.2.3.16 DMA Channel x Byte Count Register (COUNTx).......................17-34

Chapter 18 – Vectored Interrupt Controller

18.1 Theory of Operation .....................................................................................18-1

18.1.1 VIC Interrupt Listing...............................................................................18-2

18.1.2 Vectored Interrupts................................................................................18-3

18.1.3 External Interrupts.................................................................................18-3

18.1.4 Clearing Interrupts.................................................................................18-4

18.1.5 Priority ...................................................................................................18-4

18.1.6 External Level-Sensitive Interrupts........................................................18-4

18.1.7 Software Guidelines ..............................................................................18-4

18.2 Register Reference ......................................................................................18-5

18.2.1 Memory Map .........................................................................................18-5

18.2.2 Register Descriptions............................................................................18-6

18.2.2.1 IRQ Status Register (IRQSTATUS)................................................18-6

18.2.2.2 FIQ Status Register (FIQSTATUS) ................................................18-7

18.2.2.3 Raw Interrupt Status Register (RAWINTR)....................................18-7

18.2.2.4 Interrupt Select Register (INTSELECT)..........................................18-8

18.2.2.5 Interrupt Enable Register (INTENABLE)........................................18-8

18.2.2.6 Interrupt Enable Clear Register (INTENCLEAR)............................18-9

18.2.2.7 Software Interrupt Register (SOFTINT)........................................18-10

18.2.2.8 Software Interrupt Clear Register (SOFTINTCLEAR)..................18-11

18.2.2.9 Vector Address Register (VECTADDR) .......................................18-12

18.2.2.10 Default Vector Address Register (DEFVECTADDR)..................18-12

18.2.2.11 Vector Address Registers (VECTADDRx)..................................18-13

18.2.2.12 Vector Control Registers (VECTCTRLx)....................................18-14

18.2.2.13 Interrupt Test Output Register (ITOP)........................................18-15

Chapter 19 – Watchdog Timer

19.1 Theory of Operation .....................................................................................19-1

19.1.1 WDT Operation Details .........................................................................19-3

19.2 Register Reference ......................................................................................19-4

19.2.1 Memory Map .........................................................................................19-4

19.2.2 Register Descriptions............................................................................19-5

19.2.2.1 Control Register (CTL) ...................................................................19-5

19.2.2.2 Counter Reset Register (RST) .......................................................19-6

19.2.2.3 Status Register (STATUS) .............................................................19-7

19.2.2.4 Current Watchdog Count Registers (COUNT[3:0]) ........................19-8

Chapter 20 – Glossary

xiv Version 1.0

List of Figures

Preface

Figure 1. Multiplexer...............................................................................................xxxviii

Figure 2. Register with Bit-Field Named..................................................................xxxix

Figure 3. Register with Multiple Bit-Fields Named ..................................................xxxix

Figure 4. Register with Bit-Field Numbered ............................................................xxxix

Chapter 1 – Overview

Figure 1-1. LH79524/LH79525 Block Diagram ..........................................................1-2

Figure 1-2. Standard Clocking Modes........................................................................1-6

Figure 1-3. Fastbus Clocking Mode ...........................................................................1-7

Figure 1-4. Reset Circuit for TAP Controller...............................................................1-9

Figure 1-5. Reset Circuit for TAP Controller Including a Push Button......................1-10

Figure 1-6. Active Pullup Circuit...............................................................................1-11

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

Figure 2-1. ADC Block Diagram.................................................................................2-2

Figure 2-2. Bias-and-Control Network Block Diagram ...............................................2-4

Figure 2-3. Simplified N-bit SAR Architecture............................................................2-5

Figure 2-4. Example of a 4-bit SAR ADC Operation..................................................2-6

Figure 2-5. Use of the BATCNTL Pin.........................................................................2-7

Chapter 3 – Boot Controller

Figure 3-1. Boot Controller Block Diagram.................................................................3-1

Figure 3-2. Active Pullup Circuit.................................................................................3-5

Chapter 4 – Color Liquid Crystal Display Controller

Figure 4-1. LH79524/LH79525 LCD System, Simplified Block Diagram....................4-1

Figure 4-2. Block Diagram of a Typical Advanced LCD Panel...................................4-2

Figure 4-3. Color LCD Controller Block Diagram.......................................................4-4

Figure 4-4. LCD Panel Power Sequencing ..............................................................4-15

Figure 4-5. ALI Simplified Block Diagram.................................................................4-17

Figure 4-6. STN Horizontal Timing Diagram............................................................4-43

Figure 4-7. STN Vertical Timing Diagram ................................................................4-44

Figure 4-8. TFT Horizontal Timing Diagram.............................................................4-45

Figure 4-9. TFT Vertical Timing Diagram.................................................................4-46

Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram......................................4-47

Figure 4-11. AD-TFT, HR-TFT Vertical Timing Diagram..........................................4-47

Chapter 5 – Direct Memory Access Controller

Figure 5-1. Basic DMA Timing ...................................................................................5-4

Chapter 6 – Ethernet MAC Controller

Figure 6-1. EMAC Block Diagram..............................................................................6-2

Figure 6-2. Address Matching..................................................................................6-15

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List of Figures LH79524/LH79252 User’s Guide

Chapter 7 – External Memory Controller

Figure 7-1. External Memory Controller Block Diagram.............................................7-2

Figure 7-2. Automatic Address Shifting......................................................................7-4

Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices.............................7-6

Figure 7-4. 16-bit Memory Bank Constructed From 8-bit Devices.............................7-6

Figure 7-5. 8-bit Memory Bank...................................................................................7-6

Figure 7-6. 32-bit (left) and 16-bit (right) Memory Banks Constructed

From 16-bit Devices...............................................................................................7-7

Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device...............7-7

Figure 7-8. Typical Memory Connection Diagram......................................................7-8

Figure 7-9. Pre-shifting Routine .................................................................................7-9

Figure 7-10. Static Read Transaction with Zero Wait States ...................................7-11

Figure 7-11. Static Read Transaction with Three Wait States .................................7-12

Figure 7-12. Static Write Transaction with Zero Wait States....................................7-13

Figure 7-13. Static Write Transaction with Two Wait States....................................7-15

Figure 7-14. Connection to NAND Flash..................................................................7-19

Figure 7-15. NAND Flash Timing Example..............................................................7-21

Chapter 9 – I2C Module

Figure 9-1. I2C Module Block Diagram.......................................................................9-1

Figure 9-2. I

C Bus Protocol ......................................................................................9-2

Chapter 10 – I2S Converter

Figure 10-1. I2S Converter Block Diagram...............................................................10-2

Figure 10-2. TI SSP Frame Format..........................................................................10-3

Figure 10-3. I

S Format............................................................................................10-3

Figure 10-4. Driving/Latching Diagram.....................................................................10-4

Figure 10-5. I Figure 10-6. I Figure 10-7. I Figure 10-8. I Figure 10-9. I Figure 10-10. I Figure 10-11. I Figure 10-12. I

S Master Mode Transmission Block Diagram...................................10-5

S Master Mode Transmission Timing Diagram.................................10-5

S Slave Mode Transmission Block Diagram.....................................10-6

S Slave Mode Transmission Timing Diagram...................................10-7

S Master Mode Reception Block Diagram ........................................10-8

S Master Mode Reception Timing Diagram ....................................10-8

S Slave Mode Reception Block Diagram ........................................10-9

S Slave Mode Reception Timing Diagram ......................................10-9

Chapter 12 – Real Time Clock

Figure 12-1. RTC Block Diagram.............................................................................12-1

Chapter 13 – Reset, Clock, and Power Controller

Figure 13-1. RCPC Block Diagram ..........................................................................13-2

Figure 13-2. USB Clock Divider Chain.....................................................................13-4

Figure 13-3. Remap = 0b00...................................................................................13-11

Figure 13-4. Remap = 0b01...................................................................................13-12

Figure 13-5. Remap = 0b10...................................................................................13-12

Figure 13-6. Remap = 0b11...................................................................................13-13

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Chapter 14 – Synchronous Serial Port

Figure 14-1. SSP Timing Waveform Parameters.....................................................14-3

Figure 14-2. Motorola SPI Frame Format (Continuous Transfer) ............................14-4

Figure 14-3. Motorola SPI Frame Format with SPH = 0 ..........................................14-4

Figure 14-4. Texas Instruments Synchronous Serial Frame Format

(Single Transfer)...................................................................................................14-5

Figure 14-5. Texas Instruments Synchronous Serial Frame Format

(Continuous Transfers).........................................................................................14-5

Figure 14-6. Microwire Frame Format (Single Transfer)..........................................14-6

Figure 14-7. Microwire Frame Format (Continuous Transfers)................................14-7

Chapter 15 – Timers

Figure 15-1. Timer Block Diagram ...........................................................................15-2

Figure 15-2. Count Clock Timing (HCLK in Phase with CTCLK) .............................15-3

Figure 15-3. Count Clock Timing (HCLK not in Phase with CTCLK).......................15-3

Figure 15-4. Capture Signal Synchronization Timing...............................................15-4

Figure 15-5. PWM Output Signal Timing..................................................................15-5

Chapter 16 – UARTs

Figure 16-1. UART0, UART1, and UART2 Block Diagram......................................16-2

Chapter 17 – Universal Serial Bus Device

Figure 17-1. USB Block Diagram.............................................................................17-1

Figure 17-2. USB Communication Endpoints...........................................................17-2

Chapter 19 – Watchdog Timer

Figure 19-1. Watchdog Timer Block Diagram..........................................................19-2

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List of Tables

Preface

Table 1. Register Name ......................................................................................... xxxvii

Table 2. Bit Fields...................................................................................................xxxvii

Chapter 1 – Overview

Table 1-1. LH79524/LH79525 Differences.................................................................1-1

Table 1-2. Clock Descriptions ....................................................................................1-4

Table 1-3. Port C Settings For Boot...........................................................................1-8

Table 1-4. Default Bus Master Priority .....................................................................1-12

Table 1-5. AHB Memory Mapping............................................................................1-13

Table 1-6. External Static Memory Section Mapping...............................................1-13

Table 1-8. Internal SRAM Memory Section Mapping...............................................1-14

Table 1-9. Boot ROM Memory Section Mapping......................................................1-14

Table 1-7. SDRAM Memory Section Mapping .........................................................1-14

Table 1-11. Primary AHB Peripheral Register Mapping...........................................1-15

Table 1-10. AHB Memory Map on Power-up when Boot Configuration = 0bX1XX..1-15

Table 1-12. APB Peripheral Register Mapping ........................................................1-16

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

Table 2-1. ADC Register Summary..........................................................................2-10

Table 2-2. HW Register............................................................................................2-11

Table 2-3. HW Fields................................................................................................2-11

Table 2-4. In + Mux Definition..................................................................................2-12

Table 2-5. LW Register ............................................................................................2-13

Table 2-6. LW Fields................................................................................................2-13

Table 2-7. RR Register.............................................................................................2-14

Table 2-8. RR Fields ................................................................................................2-14

Table 2-9. IM Register..............................................................................................2-15

Table 2-10. IM Fields................................................................................................2-15

Table 2-11. PC Register...........................................................................................2-16

Table 2-12. PC Fields...............................................................................................2-16

Table 2-13. Touch Screen Controller Power Modes................................................2-17

Table 2-14. GC Register ..........................................................................................2-18

Table 2-15. GC Fields..............................................................................................2-18

Table 2-16. GS Register...........................................................................................2-19

Table 2-17. GS Fields ..............................................................................................2-19

Table 2-18. IS Register ............................................................................................2-20

Table 2-19. IS Fields................................................................................................2-20

Table 2-20. FS Register...........................................................................................2-21

Table 2-21. FS Fields...............................................................................................2-21

Table 2-22. Sample Entries for Control Bank...........................................................2-22

Table 2-23. IHWCTRL Register ...............................................................................2-23

Table 2-24. IHWCTRL Fields...................................................................................2-23

Table 2-25. ILWCTRL Register................................................................................2-24

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Table 2-26. ILWCTRL Fields....................................................................................2-24

Table 2-27. MIS Register .........................................................................................2-25

Table 2-28. MIS Fields.............................................................................................2-25

Table 2-29. IC Register............................................................................................2-26

Table 2-30. IC Fields................................................................................................2-26

Chapter 3 – Boot Controller

Table 3-1. Boot Configuration for Silicon Version A.0................................................3-3

Table 3-2. Boot Configuration for Silicon Version A.1................................................3-3

Table 3-3. Alternate Pin Function During NAND Flash Booting.................................3-5

Table 3-4. Boot Parameters for I2C ...........................................................................3-6

Table 3-5. Supported Devices....................................................................................3-6

Table 3-6. UART0 Boot Parameters ..........................................................................3-7

Table 3-7. Boot Controller Register Summary ...........................................................3-7

Table 3-8. PBC Register ............................................................................................3-8

Table 3-9. PBC Fields................................................................................................3-8

Table 3-10. CS1OV Register......................................................................................3-9

Table 3-11. CS1OV Fields .........................................................................................3-9

Table 3-12. EPM Register........................................................................................3-10

Table 3-13. EPM Fields............................................................................................3-10

Chapter 4 – Color Liquid Crystal Display Controller

Table 4-1. Pixel Display Arrangement........................................................................4-6

Table 4-2. Frame Buffer Pixel Storage Format [31:16] ..............................................4-6

Table 4-3. Frame Buffer Pixel Storage Format [15:0] ................................................4-7

Table 4-4. Palette Data Storage (LH79525 with 12-Bit CLCDC)................................4-8

Table 4-5. Palette Data Storage (LH79524 with 16-Bit CLCDC)................................4-8

Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels...............................4-10

Table 4-7. Supported Color STN LCD Panels (LH79524 only)................................4-10

Table 4-8. Supported Mono-STN LCD Panels.........................................................4-10

Table 4-9. Color STN Intensities From Gray-Scale Modulation...............................4-11

Table 4-10. LH79524 LCD Data Multiplexing...........................................................4-12

Table 4-11. LH79525 LCD Data Multiplexing...........................................................4-13

Table 4-12. Usable Minimum Values Affecting STN Back Porch Width...................4-14

Table 4-13. CLCDC Register Summary...................................................................4-19

Table 4-14. TIMING0 Register.................................................................................4-20

Table 4-15. TIMING0 Fields.....................................................................................4-20

Table 4-16. TIMING1 Register.................................................................................4-22

Table 4-17. TIMING1 Fields.....................................................................................4-22

Table 4-18. TIMING2 Register.................................................................................4-24

Table 4-19. TIMING2 Fields.....................................................................................4-24

Table 4-20. UPBASE Register.................................................................................4-26

Table 4-21. UPBASE Fields.....................................................................................4-26

Table 4-22. LPBASE Register..................................................................................4-27

Table 4-23. LPBASE Register Fields.......................................................................4-27

Table 4-24. INTREN Register ..................................................................................4-28

Table 4-25. INTREN Fields......................................................................................4-28

Table 4-26. CTRL Register ......................................................................................4-29

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Table 4-27. CTRL Fields..........................................................................................4-30

Table 4-28. STATUS Register..................................................................................4-32

Table 4-29. STATUS Fields .....................................................................................4-32

Table 4-30. INTERRUPT Register...........................................................................4-33

Table 4-31. INTERRUPT Fields...............................................................................4-33

Table 4-32. INTCLR Register...................................................................................4-34

Table 4-33. INTCLR Fields.......................................................................................4-34

Table 4-34. UPCURR Register ................................................................................4-35

Table 4-35. UPCURR Fields....................................................................................4-35

Table 4-36. LPCURR Register.................................................................................4-35

Table 4-37. LCDLPCURR Fields..............................................................................4-35

Table 4-38. PALETTE Register (LH79525 with 12-Bit CLCDC)...............................4-36

Table 4-39. PALETTE Fields (LH79525 with 12-Bit CLCDC) ..................................4-36

Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)...............................4-37

Table 4-41. PALETTE Fields (LH79524 with 16-Bit CLCDC) ..................................4-37

Table 4-42. ALI Register Summary..........................................................................4-38

Table 4-43. ALISETUP Register ..............................................................................4-38

Table 4-44. ALISETUP Fields..................................................................................4-38

Table 4-45. ALICTRL Register.................................................................................4-39

Table 4-46. ALICTRL Fields.....................................................................................4-39

Table 4-47. ALITIMING1 Register............................................................................4-40

Table 4-48. ALITIMING1 Fields................................................................................4-40

Table 4-49. ALITIMING2 Register............................................................................4-41

Table 4-50. ALITIMING2 Fields................................................................................4-41

Chapter 5 – Direct Memory Access Controller

Table 5-1. DMA Controller Stream Assignments and Request Priority......................5-1

Table 5-2. DMA Memory Map....................................................................................5-5

Table 5-3. DMA Data Stream Register Summary

(One Set of Registers for Each of the Four Data Streams in Table 5-2)................5-5

Table 5-4. SOURCELO Register................................................................................5-6

Table 5-5. SOURCELO Fields ...................................................................................5-6

Table 5-6. SOURCEHI Register.................................................................................5-6

Table 5-7. SOURCEHI Fields.....................................................................................5-6

Table 5-8. DESTLO Register .....................................................................................5-7

Table 5-9. DESTLO Fields.........................................................................................5-7

Table 5-10. DESTHI Register.....................................................................................5-7

Table 5-11. DESTHI Fields ........................................................................................5-7

Table 5-12. MAX Register..........................................................................................5-8

Table 5-13. MAX Fields..............................................................................................5-8

Table 5-14. CTRL Register ........................................................................................5-9

Table 5-15. CTRL Fields............................................................................................5-9

Table 5-16. DMA Data Width ...................................................................................5-10

Table 5-17. DMA Burst Size.....................................................................................5-10

Table 5-18. Constraints on CTRL Field Values Based on Stream Type..................5-11

Table 5-19. CURSHI Register..................................................................................5-12

Table 5-20. CURSHI Fields......................................................................................5-12

Table 5-21. CURSLO Register.................................................................................5-12

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Table 5-22. CURSLO Fields.....................................................................................5-12

Table 5-23. CURDHI Register..................................................................................5-13

Table 5-24. CURDHI Fields......................................................................................5-13

Table 5-25. CURDLO Register.................................................................................5-13

Table 5-26. CURDLO Fields ....................................................................................5-13

Table 5-27. TCNT Register......................................................................................5-14

Table 5-28. TCNT Fields..........................................................................................5-14

Table 5-29. MASK Register......................................................................................5-15

Table 5-30. MASK Fields .........................................................................................5-15

Table 5-31. CLR Register.........................................................................................5-16

Table 5-32. CLR Fields ............................................................................................5-16

Table 5-33. STATUS Register..................................................................................5-17

Table 5-34. STATUS Fields .....................................................................................5-17

Chapter 6 – Ethernet MAC Controller

Table 6-1. Receive Buffer Descriptor LIst ..................................................................6-5

Table 6-2. Transmit Buffer Descriptor List..................................................................6-7

Table 6-3. Pause Frame Support.............................................................................6-10

Table 6-4. VLAN Support.........................................................................................6-13

Table 6-5. EMAC Register Summary.......................................................................6-18

Table 6-6. NETCTL Register ....................................................................................6-20

Table 6-7. NETCTL Fields........................................................................................6-20

Table 6-8. NETCONFIG Register.............................................................................6-22

Table 6-9. NETCONFIG Fields ................................................................................6-22

Table 6-10. NETSTATUS Register ..........................................................................6-24

Table 6-11. NETSTATUS Fields..............................................................................6-24

Table 6-12. TXSTATUS Register.............................................................................6-25

Table 6-13. TXSTATUS Fields.................................................................................6-25

Table 6-14. RXBQP Register...................................................................................6-27

Table 6-15. RXBQP Fields.......................................................................................6-27

Table 6-16. TXBQP Register....................................................................................6-28

Table 6-17. TXBQP Fields .......................................................................................6-28

Table 6-18. RXSTATUS Register.............................................................................6-29

Table 6-19. RXSTATUS Fields ................................................................................6-29

Table 6-20. INSTATUS Register..............................................................................6-30

Table 6-21. INSTATUS Fields..................................................................................6-30

Table 6-22. ENABLE Register..................................................................................6-32

Table 6-23. ENABLE Fields .....................................................................................6-32

Table 6-24. DISABLE Register.................................................................................6-33

Table 6-25. DISABLE Fields ....................................................................................6-33

Table 6-26. MASK Register......................................................................................6-34

Table 6-27. MASK Fields .........................................................................................6-34

Table 6-28. PHYMAINT Register.............................................................................6-35

Table 6-29. PHYMAINT Fields.................................................................................6-35

Table 6-30. PAUSETIME Register...........................................................................6-36

Table 6-31. PAUSETIME Fields...............................................................................6-36

Table 6-32. TXPAUSEQUAN Register.....................................................................6-36

Table 6-33. TXPAUSEQUAN Fields ........................................................................6-36

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Table 6-34. PAUSEFRRX Register..........................................................................6-37

Table 6-35. PAUSEFRRX Fields..............................................................................6-37

Table 6-36. FRMTXOK Register..............................................................................6-38

Table 6-37. FRMTXOK Fields..................................................................................6-38

Table 6-38. SINGLECOL Register...........................................................................6-38

Table 6-39. SINGLECOL Fields...............................................................................6-38

Table 6-40. MULTFRM Register..............................................................................6-39

Table 6-41. MULTFRM Fields..................................................................................6-39

Table 6-42. FRMRXOK Register..............................................................................6-39

Table 6-43. FRMRXOK Fields..................................................................................6-39

Table 6-44. FRCHK Register ...................................................................................6-40

Table 6-45. FRCHK Fields.......................................................................................6-40

Table 6-46. ALIGNERR Register .............................................................................6-40

Table 6-47. ALIGNERR Fields.................................................................................6-40

Table 6-48. DEFTXFRM Register............................................................................6-41

Table 6-49. DEFTXFRM Fields................................................................................6-41

Table 6-50. LATECOL Register ...............................................................................6-41

Table 6-51. LATECOL Fields...................................................................................6-41

Table 6-52. EXCOL Register....................................................................................6-42

Table 6-53. EXCCOL Fields.....................................................................................6-42

Table 6-54. TXUNDER Register ..............................................................................6-42

Table 6-55. TXUNDER Fields..................................................................................6-42

Table 6-56. SENSERR Register ..............................................................................6-43

Table 6-57. SENSERR Fields..................................................................................6-43

Table 6-58. RXRERR Register.................................................................................6-44

Table 6-59. RXRERR Fields ....................................................................................6-44

Table 6-60. RXOVERR Register..............................................................................6-44

Table 6-61. RXOVERR Fields..................................................................................6-44

Table 6-62. RXSYMERR Register ...........................................................................6-45

Table 6-63. RXSYMERR Fields...............................................................................6-45

Table 6-64. LENERR Register.................................................................................6-45

Table 6-65. LENERR Fields.....................................................................................6-45

Table 6-66. RXJAB Register....................................................................................6-46

Table 6-67. RXJAB Fields........................................................................................6-46

Table 6-68. UNDERFRM Register...........................................................................6-46

Table 6-69. UNDERFRM Fields...............................................................................6-46

Table 6-70. SQERR Register...................................................................................6-47

Table 6-71. SQERR Fields.......................................................................................6-47

Table 6-72. RXLEN Register....................................................................................6-47

Table 6-73. RXLEN Fields........................................................................................6-47

Table 6-74. TXPAUSEFM Register..........................................................................6-48

Table 6-75. TXPAUSEFM Fields..............................................................................6-48

Table 6-76. HASHBOT Register ..............................................................................6-49

Table 6-77. HASHBOT Fields..................................................................................6-49

Table 6-78. HASHTOP Register ..............................................................................6-49

Table 6-79. HASHTOP Fields..................................................................................6-49

Table 6-80. SPECAD1BOT Register........................................................................6-50

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Table 6-81. SPECAD1BOT Fields ...........................................................................6-50

Table 6-82. SPECAD1TOP Register........................................................................6-50

Table 6-83. SPECAD1TOP Fields ...........................................................................6-50

Table 6-84. SPECAD2BOT Register........................................................................6-51

Table 6-85. SPECAD2BOT Fields ...........................................................................6-51

Table 6-86. SPECAD2TOP Register........................................................................6-51

Table 6-87. SPECAD2TOP Fields ...........................................................................6-51

Table 6-88. SPECAD3BOT Register........................................................................6-52

Table 6-89. SPECAD3BOT Fields ...........................................................................6-52

Table 6-90. SPECAD3TOP Register........................................................................6-52

Table 6-91. SPECAD3TOP Fields ...........................................................................6-52

Table 6-92. SPECAD4BOT Register........................................................................6-53

Table 6-93. SPECAD4BOT Fields ...........................................................................6-53

Table 6-94. SPECAD4TOP Register........................................................................6-53

Table 6-95. SPECAD4TOP Fields ...........................................................................6-53

Table 6-96. IDCHK Register.....................................................................................6-54

Table 6-97. TypeIDCheck Fields..............................................................................6-54

Chapter 7 – External Memory Controller

Table 7-1. Static Memory Configurations.................................................................7-10

Table 7-2. Boot Configuration for Silicon Version A.0..............................................7-18

Table 7-3. Boot Configuration for Silicon Version A.1..............................................7-18

Table 7-4. 16-bit Address Mapping..........................................................................7-20

Table 7-5. 32-bit Wide Data Bus Address Mapping, SDRAM (RBC).......................7-22

Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC).......................7-23

Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC).......................7-25

Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC).......................7-26

Table 7-9. Memory System Examples .....................................................................7-27

Table 7-10. External Memory Controller Register Summary....................................7-28

Table 7-11. CONTROL Register..............................................................................7-30

Table 7-12. CONTROL Fields..................................................................................7-30

Table 7-13. STATUS Register..................................................................................7-31

Table 7-14. STATUS Fields .....................................................................................7-31

Table 7-15. CONFIG Register..................................................................................7-32

Table 7-16. CONFIG Fields......................................................................................7-32

Table 7-17. DYNMCTRL Register............................................................................7-33

Table 7-18. DYNMCTRL Fields................................................................................7-33

Table 7-19. DYNMREF Register..............................................................................7-34

Table 7-20. DYNMREF Fields..................................................................................7-34

Table 7-21. DYNMRCON Register...........................................................................7-35

Table 7-22. DYNMRCON Fields ..............................................................................7-35

Table 7-23. PRECHARGE Register.........................................................................7-36

Table 7-24. PRECHARGE Fields.............................................................................7-36

Table 7-25. DYNM2PRE Register............................................................................7-37

Table 7-26. DYNM2PRE Fields................................................................................7-37

Table 7-27. REFEXIT Register.................................................................................7-38

Table 7-28. REFEXIT Fields ....................................................................................7-38

Table 7-29. DOACTIVE Register .............................................................................7-39

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Table 7-30. DOACTIVE Fields.................................................................................7-39

Table 7-31. DIACTIVE Register...............................................................................7-40

Table 7-32. DIACTIVE Fields...................................................................................7-40

Table 7-33. DWRT Register.....................................................................................7-41

Table 7-34. DWRT Fields.........................................................................................7-41

Table 7-35. DYNACTCMD Register.........................................................................7-42

Table 7-36. DYNACTCMD Fields.............................................................................7-42

Table 7-37. DYNAUTO Register..............................................................................7-43

Table 7-38. DYNAUTO Fields..................................................................................7-43

Table 7-39. DYNREFEXIT Register.........................................................................7-44

Table 7-40. DYNREFEXIT Fields.............................................................................7-44

Table 7-41. DYNACTIVEAB Register ......................................................................7-45

Table 7-42. DYNACTIVEAB Fields..........................................................................7-45

Table 7-43. DYNAMICTMRD Register.....................................................................7-46

Table 7-44. DYNAMICTMRD Fields.........................................................................7-46

Table 7-45. WAIT Register.......................................................................................7-47

Table 7-46. WAIT Fields...........................................................................................7-47

Table 7-47. DYNCFGx Register...............................................................................7-48

Table 7-48. DYNCFGx Fields...................................................................................7-48

Table 7-49. Address Mapping..................................................................................7-49

Table 7-50. DYNRASCASx Register........................................................................7-51

Table 7-51. DYNRASCASx Fields ...........................................................................7-51

Table 7-52. SCONFIGx Register..............................................................................7-52

Table 7-53. SCONFIGx Fields .................................................................................7-52

Table 7-54. SWAITWENx Register..........................................................................7-54

Table 7-55. SWAITWENx Fields..............................................................................7-54

Table 7-56. SWAITOENx Register...........................................................................7-55

Table 7-57. SWAITOENx Fields...............................................................................7-55

Table 7-58. SWAITRDx Register .............................................................................7-56

Table 7-59. SWAITRDx Fields.................................................................................7-56

Table 7-60. SWAITPAGEx Register.........................................................................7-57

Table 7-61. SWAITPAGEx Fields ............................................................................7-57

Table 7-62. SWAITWRx Register.............................................................................7-58

Table 7-63. SWAITWRx Fields ................................................................................7-58

Table 7-64. STURNx Register..................................................................................7-59

Table 7-65. STURNx Fields .....................................................................................7-59

Chapter 8 – General Purpose Input/Output

Table 8-1. GPIO Ports................................................................................................8-1

Table 8-2. LH79524 GPIO Multiplexing......................................................................8-2

Table 8-3. LH79525 GPIO Multiplexing......................................................................8-5

Table 8-4. GPIO Port Memory Map............................................................................8-7

Table 8-5. P1DRx Register ........................................................................................8-8

Table 8-6. P1DRx Fields............................................................................................8-8

Table 8-7. P2DRx Register ........................................................................................8-9

Table 8-8. P2DRx Fields............................................................................................8-9

Table 8-9. P1DDRx Register....................................................................................8-10

Table 8-10. P1DDRx Fields......................................................................................8-10

Table 8-11. P2DDRx Register..................................................................................8-11

Table 8-12. P2DDRx Register Definitions................................................................8-11

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Chapter 9 – I2C Module

Table 9-1. I2C Clock Parameters ...............................................................................9-3

Table 9-2. Sample I Table 9-3. I

C Register Summary..............................................................................9-6

Table 9-4. ICCON Register........................................................................................9-7

Table 9-5. ICCON Fields............................................................................................9-7

Table 9-6. ICSAR Register.........................................................................................9-8

Table 9-7. ICSAR Fields.............................................................................................9-8

Table 9-8. ICUSAR Register......................................................................................9-9

Table 9-9. ICUSAR Fields..........................................................................................9-9

Table 9-10. ICDATA Register.....................................................................................9-9

Table 9-11. ICDATA Fields ........................................................................................9-9

Table 9-12. ICHCNT Register..................................................................................9-10

Table 9-13. ICHCNT Fields......................................................................................9-10

Table 9-14. ICLCNT Register...................................................................................9-10

Table 9-15. ICLCNT Fields.......................................................................................9-10

Table 9-16. ICSTAT Register...................................................................................9-11

Table 9-17. ICSTAT Fields.......................................................................................9-11

C HIGH Period Counts..............................................................9-3

Chapter 10 – I2S Converter

Table 10-1. I2S Converter Register Summary........................................................10-13

Table 10-2. CTRL Register ....................................................................................10-14

Table 10-3. CTRL Register Definitions...................................................................10-14

Table 10-4. WSINV Functionality...........................................................................10-15

Table 10-5. STAT Register.....................................................................................10-16

Table 10-6. STAT Register Definitions...................................................................10-16

Table 10-7. IMSC Register.....................................................................................10-17

Table 10-8. IMSC Register Definitions...................................................................10-17

Table 10-9. RIS Register........................................................................................10-18

Table 10-10. RIS Register Definitions....................................................................10-18

Table 10-11. MIS Register .....................................................................................10-19

Table 10-12. MIS Register Definitions....................................................................10-19

Table 10-13. ICR Register......................................................................................10-20

Table 10-14. ICR Register Definitions....................................................................10-20

Chapter 11 – I/O Configuration

Table 11-1. IOCON Register Summary....................................................................11-2

Table 11-2. MUXCTL1 Register...............................................................................11-4

Table 11-3. MUXCTL1 Fields...................................................................................11-4

Table 11-4. RESCTL1 Register................................................................................11-5

Table 11-5. RESCTL1 Fields ...................................................................................11-5

Table 11-6. MUXCTL3 Register...............................................................................11-6

Table 11-7. MUXCTL3 Fields...................................................................................11-6

Table 11-8. RESCTL3 Register................................................................................11-6

Table 11-9. RESCTL3 Fields ...................................................................................11-6

Table 11-10. MUXCTL4 Register.............................................................................11-7

Table 11-11. MUXCTL4 Fields.................................................................................11-7

Table 11-12. RESCTL4 Register..............................................................................11-8

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Table 11-13. RESCTL4 Fields .................................................................................11-8

Table 11-14. MUXCTL5 Register.............................................................................11-9

Table 11-15. MUXCTL5 Fields.................................................................................11-9

Table 11-16. RESCTL5 Register............................................................................11-10

Table 11-17. RESCTL5 Fields ...............................................................................11-10

Table 11-18. MUXCTL6 Register...........................................................................11-12

Table 11-19. MUXCTL6 Fields...............................................................................11-12

Table 11-20. RESCTL6 Register............................................................................11-13

Table 11-21. RESCTL6 Fields ...............................................................................11-13

Table 11-22. MUXCTL7 Register...........................................................................11-14

Table 11-23. MUXCTL7 Fields...............................................................................11-14

Table 11-24. RESCTL7 Register............................................................................11-16

Table 11-25. RESCTL7 Fields ...............................................................................11-16

Table 11-26. MUXCTL10 Register.........................................................................11-18

Table 11-27. MUXCTL10 Fields.............................................................................11-18

Table 11-28. RESCTL10 Register..........................................................................11-20

Table 11-29. RESCTL10 Fields .............................................................................11-20

Table 11-30. MUXCTL11 Register.........................................................................11-22

Table 11-31. MUXCTL11 Fields.............................................................................11-22

Table 11-32. RESCTL11 Register..........................................................................11-24

Table 11-33. RESCTL11 Fields .............................................................................11-24

Table 11-34. MUXCTL12 Register.........................................................................11-26

Table 11-35. MUXCTL12 Fields.............................................................................11-26

Table 11-36. RESCTL12 Register..........................................................................11-27

Table 11-37. RESCTL12 Fields .............................................................................11-27

Table 11-38. RESCTL13 Register..........................................................................11-29

Table 11-39. RESCTL13 Fields .............................................................................11-29

Table 11-40. MUXCTL14 Register.........................................................................11-30

Table 11-41. MUXCTL14 Fields.............................................................................11-30

Table 11-42. MUXCTL15 Register.........................................................................11-32

Table 11-43. MUXCTL15 Fields.............................................................................11-32

Table 11-44. RESCTL15 Register..........................................................................11-32

Table 11-45. RESCTL15 Fields .............................................................................11-32

Table 11-46. RESCTL17 Register..........................................................................11-33

Table 11-47. RESCTL17 Fields .............................................................................11-33

Table 11-48. MUXCTL19 Register.........................................................................11-34

Table 11-49. MUXCTL19 Fields.............................................................................11-34

Table 11-50. RESCTL19 Register..........................................................................11-36

Table 11-51. RESCTL19 Fields .............................................................................11-36

Table 11-52. MUXCTL20 Register.........................................................................11-38

Table 11-53. MUXCTL20 Fields.............................................................................11-38

Table 11-54. RESCTL20 Register..........................................................................11-40

Table 11-55. RESCTL20 Fields .............................................................................11-40

Table 11-56. MUXCTL21 Register.........................................................................11-42

Table 11-57. MUXCTL21 Fields.............................................................................11-42

Table 11-58. RESCTL21 Register..........................................................................11-43

Table 11-59. RESCTL21 Fields .............................................................................11-43

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Table 11-60. MUXCTL22 Register.........................................................................11-44

Table 11-61. MUXCTL22 Fields.............................................................................11-44

Table 11-62. RESCTL22 Register..........................................................................11-46

Table 11-63. RESCTL22 Fields .............................................................................11-46

Table 11-64. MUXCTL23 Register.........................................................................11-48

Table 11-65. MUXCTL23 Fields.............................................................................11-48

Table 11-66. RESCTL23 Register..........................................................................11-50

Table 11-67. RESCTL23 Fields .............................................................................11-50

Table 11-68. MUXCTL24 Register.........................................................................11-52

Table 11-69. MUXCTL24 Fields.............................................................................11-52

Table 11-70. RESCTL24 Register..........................................................................11-53

Table 11-71. RESCTL24 Fields .............................................................................11-53

Table 11-72. MUXCTL25 Register.........................................................................11-54

Table 11-73. MUXCTL25 Fields.............................................................................11-54

Chapter 12 – Real Time Clock

Table 12-1. RTC Register Summary........................................................................12-3

Table 12-2. DR Register...........................................................................................12-3

Table 12-3. DR Fields ..............................................................................................12-3

Table 12-4. MR Register..........................................................................................12-4

Table 12-5. MR Fields..............................................................................................12-4

Table 12-6. LR Register...........................................................................................12-4

Table 12-7. LR Fields...............................................................................................12-4

Table 12-8. CR Register...........................................................................................12-5

Table 12-9. CR Fields ..............................................................................................12-5

Table 12-10. IMSC Register.....................................................................................12-5

Table 12-11. IMSC Fields.........................................................................................12-5

Table 12-12. RIS Register........................................................................................12-6

Table 12-13. RIS Fields............................................................................................12-6

Table 12-14. MIS Register .......................................................................................12-6

Table 12-15. MIS Fields...........................................................................................12-6

Table 12-16. ICR Register........................................................................................12-7

Table 12-17. ICR Fields ...........................................................................................12-7

Chapter 13 – Reset, Clock, and Power Controller

Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies........................13-5

Table 13-2. Clock and Enable States for Different Power Modes............................13-6

Table 13-3. RCPC Register Summary.....................................................................13-8

Table 13-4. CTRL Register ......................................................................................13-9

Table 13-5. CTRL Fields..........................................................................................13-9

Table 13-6. CHIPID Register..................................................................................13-10

Table 13-7. CHIPID Fields .....................................................................................13-10

Table 13-8. REMAP Register.................................................................................13-11

Table 13-9. REMAP Fields.....................................................................................13-11

Table 13-10. SOFTRESET Register......................................................................13-14

Table 13-11. SOFTRESET Fields..........................................................................13-14

Table 13-12. RSTSTATUS Register ......................................................................13-15

Table 13-13. RSTSTATUS Fields..........................................................................13-15

xxviii Version 1.0

LH79524/LH79252 User’s Guide

Table 13-14. RSTSTATUSCLR Register...............................................................13-16

Table 13-15. RSTSTATUSCLR Fields...................................................................13-16

Table 13-16. SYSCLKPRE Register......................................................................13-17

Table 13-17. SYSCLKPRE Fields..........................................................................13-17

Table 13-18. SYSCLKPRE Register Values..........................................................13-17

Table 13-19. CPUCLKPRE Register......................................................................13-18

Table 13-20. CPUCLKPRE Fields..........................................................................13-18

Table 13-21. CPUCLKPRE Register Values..........................................................13-18

Table 13-22. PCLKCTRL0 Register.......................................................................13-19

Table 13-23. PCLKCTRL0 Fields...........................................................................13-19

Table 13-24. PCLKCTRL1 Register.......................................................................13-20

Table 13-25. PCLKCTRL1 Fields...........................................................................13-20

Table 13-26. AHBCLKCTRL Register....................................................................13-21

Table 13-27. AHBCLKCTRL Fields........................................................................13-21

Table 13-28. PCLKSEL0 Register..........................................................................13-22

Table 13-29. PCLKSEL0 Fields .............................................................................13-22

Table 13-30. PCLKSEL1 Register..........................................................................13-23

Table 13-31. PCLKSEL1 Fields .............................................................................13-23

Table 13-32. SILICONREV Register......................................................................13-24

Table 13-33. SILICONREV Fields..........................................................................13-24

Table 13-34. LCDPRE Register.............................................................................13-25

Table 13-35. LCDPRE Fields.................................................................................13-25

Table 13-36. LCDPRE Register Values.................................................................13-25

Table 13-37. SSPPRE Register.............................................................................13-26

Table 13-38. SSPPRE Fields.................................................................................13-26

Table 13-39. SSPPRE Register Values.................................................................13-26

Table 13-40. ADCPRE Register.............................................................................13-27

Table 13-41. ADCPRE Fields.................................................................................13-27

Table 13-42. ADCPRE Register Values.................................................................13-27

Table 13-43. USBPRE Register.............................................................................13-28

Table 13-44. USBPRE Fields.................................................................................13-28

Table 13-45. USBPRE Register Values.................................................................13-28

Table 13-46. INTCONFIG Register........................................................................13-29

Table 13-47. INTCONFIG Fields............................................................................13-29

Table 13-48. INTCLR Register...............................................................................13-31

Table 13-49. INTCLR Fields...................................................................................13-31

Table 13-50. CORECONFIG Register ...................................................................13-32

Table 13-51. CORECONFIG Fields.......................................................................13-32

Table 13-52. SYSPLLCTL Register .......................................................................13-33

Table 13-53. SYSPLLCTL Fields...........................................................................13-33

Table 13-54. USBPLLCTL Register.......................................................................13-34

Table 13-55. USBPLLCTL Fields...........................................................................13-34

Version 1.0 xxix

+ 525 hidden pages

Sharp LH79524, LH79525 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Figures

List of Tables