Sharp LH79524, LH79525 User Manual

LH79524/LH79525

User’s Guide

Version 1.0

Specifications are subject to change without notice.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special
applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and
exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES,
INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR
A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in
any way responsible, for any incidental or consequential economic or property damage.

Purchase of I
Companies conveys a license under the Philips I
components in an I

2

C components from SHARP Corporation or one of its sublicensed Associated

2

C system, provided that the system conforms to the I2C Standard Specification

2

C Patent. Rights are granted to use these

as defined by Philips.

LH79524/LH79525 SoC User’s Guide
Produced by the SHARP Microelectronics of the Americas MarCom Group.
© 2004-2007 Copyright SHARP Microelectronics of the Americas.
Reference No. SMA04007

Table of Contents

Preface

Conventions and Terms......................................................................................xxxv

Unconnected (Floating) Inputs........................................................................xxxv

Multiplexed Pins ..............................................................................................xxxv

Pin Names......................................................................................................xxxvi

Peripheral Devices .........................................................................................xxxvi

Register Addresses........................................................................................xxxvi

Register Tables............................................................................................. xxxvii

Numeric Values.............................................................................................xxxviii

Block Diagrams .............................................................................................xxxviii

What’s in This User’s Guide......................................................................................xl

Chapter 1 – Overview............................................................................................xl

Chapter 2 – ADC and Brownout Detector.............................................................xl

Chapter 3 – Boot Controller...................................................................................xl

Chapter 4 – Color LCD Controller .........................................................................xl

Chapter 5 – DMA Controller..................................................................................xl

Chapter 6 – Ethernet MAC....................................................................................xl

Chapter 7 – External Memory Controller..............................................................xli

Chapter 8 – General Purpose Input/Output..........................................................xli

Chapter 9 – I2C Interface.....................................................................................xli

Chapter 10 – I2S Converter .................................................................................xli

Chapter 11 – I/O Configuration ............................................................................xli

Chapter 12 – Real Time Clock .............................................................................xli

Chapter 13 – Reset, Clock Generation and Power Control..................................xli

Chapter 14 – Synchronous Serial Port.................................................................xli

Chapter 15 – Timers............................................................................................xlii

Chapter 16 – UARTs...........................................................................................xlii

Chapter 17 – USB Device ...................................................................................xlii

Chapter 18 – Vectored Interrupt Controller .........................................................xlii

Chapter 19 – Watchdog Timer............................................................................xlii

Appendix – Glossary ...........................................................................................xlii

Chapter 1 – Overview

1.1 Bus Architecture...............................................................................................1-3

1.2 Power Supply...................................................................................................1-3

1.2.1 Linear Regulator........................................................................................1-3

1.2.2 Phase Locked Loop Power .......................................................................1-3

1.3 Clock Strategy..................................................................................................1-4

1.3.1 Bus Clocking Modes..................................................................................1-6

1.3.1.1 Standard Bus Clocking Modes...........................................................1-6

1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes......................1-7

1.3.1.3 Fastbus Extension Bus Clocking Mode..............................................1-7

1.4 Reset Strategy..................................................................................................1-8

1.4.1 Resetting the Test Access Port Controller ................................................1-9

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1.4.2 Hardware Requirements at Reset...........................................................1-10

1.4.2.1 Floating Inputs..................................................................................1-10

1.4.2.2 Test Pins...........................................................................................1-10

1.4.2.3 Active Pull Ups .................................................................................1-11

1.5 AHB Bus Master Priority and Arbitration........................................................1-12

1.6 Memory Interface Architecture.......................................................................1-12

1.7 Instruction and Data Cache............................................................................1-17

1.8 Memory Management Unit (MMU).................................................................1-17

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

2.1 Theory of Operation .........................................................................................2-1

2.1.1 Operational Summary ...............................................................................2-1

2.1.2 Bias-and-Control Network.........................................................................2-3

2.1.3 Clock Generator........................................................................................2-5

2.1.4 Brownout Detector.....................................................................................2-5

2.1.5 SAR Architecture.......................................................................................2-5

2.1.6 Battery Control Feature.............................................................................2-7

2.1.7 Timing Formulas........................................................................................2-8

2.1.8 Interrupts...................................................................................................2-8

2.1.8.1 Brownout Interrupt..............................................................................2-8

2.1.8.2 Pen Interrupt.......................................................................................2-9

2.1.8.3 End-of-Sequence Interrupt.................................................................2-9

2.1.8.4 FIFO Watermark Interrupt ..................................................................2-9

2.1.8.5 FIFO Overrun Interrupt.......................................................................2-9

2.1.9 Application Details.....................................................................................2-9

2.2 Register Reference ........................................................................................2-10

2.2.1 Memory Map ...........................................................................................2-10

2.2.2 Register Descriptions ..............................................................................2-11

2.2.2.1 High Word Register (HW).................................................................2-11

2.2.2.2 Low Word Register (LW)..................................................................2-13

2.2.2.3 Results Register (RR).......................................................................2-14

2.2.2.4 Interrupt Mask Register (IM).............................................................2-15

2.2.2.5 Power Configuration Register (PC)..................................................2-16

2.2.2.6 General Configuration Register (GC)...............................................2-18

2.2.2.7 General Status Register (GS)...........................................................2-19

2.2.2.8 Interrupt Status Register (IS)............................................................2-20

2.2.2.9 FIFO Status Register (FS)................................................................2-21

2.2.2.10 Control Bank Registers...................................................................2-22

2.2.2.11 Idle High Word Register (IHWCTRL)..............................................2-23

2.2.2.12 Idle Low Word Register (ILWCTRL)...............................................2-24

2.2.2.13 Masked Interrupt Status Register (MIS).........................................2-25

2.2.2.14 Interrupt Clear Register (IC)...........................................................2-26

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Chapter 3 – Boot Controller

3.1 Theory of Operation .........................................................................................3-2

3.1.1 Boot Device Determination........................................................................3-2

3.1.1.1 NAND Flash Operation.......................................................................3-4

3.1.2 Hardware Design Considerations..............................................................3-4

3.1.2.1 Active Pullups To Signal Boot Mode ..................................................3-4

3.1.2.2 NAND Flash Hardware Design...........................................................3-5

3.1.3 Booting Using the I2C Interface ................................................................3-6

3.1.4 Booting from UART ...................................................................................3-7

3.2 Register Reference ..........................................................................................3-7

3.2.1 Memory Map .............................................................................................3-7

3.2.2 Register Definitions ...................................................................................3-8

3.2.2.1 Power-up Boot Configuration Register (PBC)....................................3-8

3.2.3 nCS1 Override Register (CS1OV).............................................................3-9

3.2.4 External Peripheral Mapping Register (EPM) .........................................3-10

Chapter 4 – Color Liquid Crystal Display Controller

4.1 Introduction.......................................................................................................4-1

4.1.1 LCD Panel Architecture.............................................................................4-2

4.2 CLCDC Features..............................................................................................4-3

4.3 Theory of Operation .........................................................................................4-3

4.3.1 Supported Displays and Panels................................................................4-5

4.3.2 Frame Buffer .............................................................................................4-5

4.3.3 LCD DMA FIFOs .......................................................................................4-5

4.3.4 Pixel Serializer...........................................................................................4-6

4.3.5 How Pixels are Stored in Memory.............................................................4-6

4.3.6 Palette RAM ..............................................................................................4-8

4.3.6.1 Grayscale Algorithm...........................................................................4-9

4.3.6.2 Interrupts ............................................................................................4-9

4.3.6.3 LCD Panel Resolutions ......................................................................4-9

4.3.7 LCD Data Multiplexing.............................................................................4-12

4.3.8 LCD Interface Timing Signals..................................................................4-13

4.3.8.1 LCD Horizontal Timing Signals.........................................................4-13

4.3.8.2 LCD Vertical Timing Signals.............................................................4-14

4.3.9 LCD Power Sequencing at Turn-On and Turn-Off..................................4-15

4.3.9.1 Minimizing a Retained Image on the LCD........................................4-16

4.3.10 Interrupts...............................................................................................4-16

4.4 Advanced LCD Interface................................................................................4-17

4.4.1 ALI Theory of Operation..........................................................................4-18

4.4.2 ALI Operating Modes ..............................................................................4-18

4.4.2.1 Bypass Mode....................................................................................4-18

4.4.2.2 Active Mode......................................................................................4-18

4.5 CLCDC Register Reference...........................................................................4-19

4.5.1 Enabling the CLCDC...............................................................................4-19

4.5.2 CLCDC Memory Map..............................................................................4-19

4.5.3 CLCDC Register Descriptions.................................................................4-20

4.5.3.1 Horizontal Timing Panel Control Register (TIMING0) ......................4-20

4.5.3.2 Vertical Timing Panel Control Register (TIMING1)...........................4-22

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4.5.3.3 Clock and Signal Polarity Control Register (TIMING2).....................4-24

4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE)........4-26

4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) ........4-27

4.5.3.6 Interrupt Enable Register (INTREN).................................................4-28

4.5.3.7 CLCDC Control Register (CTRL) .....................................................4-29

4.5.3.8 Raw Interrupt Status Register (STATUS) .........................................4-32

4.5.3.9 Masked Interrupt Status Register (INTERRUPT).............................4-33

4.5.3.10 Interrupt Clear Register (INTCLR) ..................................................4-34

4.5.3.11 LCD Upper Panel and Lower Panel Frame Buffer Current

Address Register (UPCURR and LPCURR) ............................................4-35

4.5.3.12 256 × 16-bit Color Palette Register (PALETTE).............................4-36

4.5.4 ALI Register Reference...........................................................................4-38

4.5.5 ALI Memory Map.....................................................................................4-38

4.5.6 ALI Register Descriptions........................................................................4-38

4.5.6.1 Setup Register (ALISETUP).............................................................4-38

4.5.6.2 Control Register (ALICTRL) .............................................................4-39

4.5.6.3 Timing Delay Register 1 (ALITIMING1)............................................4-40

4.5.6.4 Timing Delay Register 2 (ALITIMING2)............................................4-41

4.6 Timing Waveforms .........................................................................................4-42

4.6.1 STN Horizontal Timing ............................................................................4-42

4.6.2 STN Vertical Timing ................................................................................4-42

4.6.3 TFT Horizontal Timing.............................................................................4-42

4.6.4 TFT Vertical Timing.................................................................................4-42

4.6.5 AD-TFT/HR-TFT Horizontal Timing Waveforms......................................4-42

4.6.6 AD-TFT/HR-TFT Vertical Timing Waveforms..........................................4-42

Chapter 5 – Direct Memory Access Controller

5.1 Theory Of Operation.........................................................................................5-2

5.1.1 Use for SSP and UART.............................................................................5-3

5.1.2 Changing Mode from Memory to Peripheral .............................................5-3

5.1.3 Interrupt, Error, and Status Registers........................................................5-4

5.1.3.1 Interrupts ............................................................................................5-4

5.1.4 External DMA Handshake Signal Timing..................................................5-4

5.2 Register Reference ..........................................................................................5-5

5.2.1 Memory Map .............................................................................................5-5

5.2.2 Register Definitions ...................................................................................5-6

5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI)....................5-6

5.2.2.2 Destination Base Registers (DESTLO and DESTHI).........................5-7

5.2.2.3 Maximum Count Register (MAX)........................................................5-8

5.2.2.4 Control Register (CTRL).....................................................................5-9

5.2.2.5 Current Source Registers (CURSHI and CURSLO).........................5-12

5.2.2.6 Current Destination Registers (CURDHI and CURDLO)..................5-13

5.2.2.7 Terminal Count Register (TCNT)......................................................5-14

5.2.2.8 Interrupt Mask Register (MASK).......................................................5-15

5.2.2.9 Interrupt Clear Register (CLR)..........................................................5-16

5.2.2.10 Status Register (STATUS) .............................................................5-17

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Chapter 6 – Ethernet MAC Controller

6.1 Theory of Operation .........................................................................................6-2

6.1.1 Operational Overview................................................................................6-3

6.1.1.1 Setup..................................................................................................6-4

6.1.1.2 Statistics.............................................................................................6-4

6.1.1.3 Detailed Descriptions..........................................................................6-4

6.1.2 Memory Interface ......................................................................................6-4

6.1.2.1 FIFO ...................................................................................................6-4

6.1.2.2 Receive Buffers..................................................................................6-4

6.1.2.3 Transmit Buffer...................................................................................6-7

6.1.3 Receive Block............................................................................................6-9

6.1.4 Transmit Block...........................................................................................6-9

6.1.4.1 Pause Frame Support ......................................................................6-10

6.1.5 Address Checking Block .........................................................................6-11

6.1.5.1 Broadcast Address...........................................................................6-12

6.1.5.2 Hash Addressing..............................................................................6-12

6.1.5.3 Copy All Frames (Promiscuous Mode).............................................6-12

6.1.5.4 Type ID Checking.............................................................................6-13

6.1.5.5 VLAN Support...................................................................................6-13

6.2 Programming Model.......................................................................................6-13

6.2.1 Initialization..............................................................................................6-14

6.2.1.1 Receive Buffer List ...........................................................................6-14

6.2.1.2 Transmit Buffer List ..........................................................................6-16

6.2.1.3 Transmitting Frames.........................................................................6-16

6.2.1.4 Local Loop Back Mode.....................................................................6-16

6.2.1.5 PHY Maintenance.............................................................................6-17

6.2.1.6 Interrupts ..........................................................................................6-17

6.3 Register Reference ........................................................................................6-18

6.3.1 Memory Map ...........................................................................................6-18

6.3.2 Control, Configuration, And Status Register Definitions..........................6-20

6.3.2.1 Network Control Register (NETCTL)................................................6-20

6.3.2.2 Network Configuration Register (NETCONFIG)...............................6-22

6.3.2.3 Network Status Register (NETSTATUS)..........................................6-24

6.3.2.4 Transmit Status Register (TXSTATUS)............................................6-25

6.3.2.5 Receive Buffer Queue Pointer (RXBQP) ..........................................6-27

6.3.2.6 Transmit Buffer Queue Pointer (TXBQP).........................................6-28

6.3.2.7 Receive Status Register (RXSTATUS) ............................................6-29

6.3.2.8 Interrupt Status Register (INSTATUS) .............................................6-30

6.3.2.9 Interrupt Enable Register (ENABLE)................................................6-32

6.3.2.10 Interrupt Disable Register (DISABLE)............................................6-33

6.3.2.11 Interrupt Mask Register (MASK).....................................................6-34

6.3.2.12 PHY Maintenance Register (PHYMAINT)......................................6-35

6.3.2.13 Pause Time Register (PAUSETIME)..............................................6-36

6.3.2.14 Transmit Pause Quantum (TXPAUSEQUAN)................................6-36

6.3.3 Statistics Register Definitions..................................................................6-37

6.3.3.1 Pause Frames Received (PAUSEFRRX).........................................6-37

6.3.3.2 Frames Transmitted OK (FRMTXOK)..............................................6-38

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6.3.3.3 Single Collision Frames (SINGLECOL)............................................6-38

6.3.3.4 Multiple Collision Frames (MULTFRM) ............................................6-39

6.3.3.5 Frames Received OK (FRMRXOK)..................................................6-39

6.3.3.6 Frame Check Sequence Errors (FRCHK)........................................6-40

6.3.3.7 Alignment Errors (ALIGNERR).........................................................6-40

6.3.3.8 Deferred Transmission Frames (DEFTXFRM).................................6-41

6.3.3.9 Late Collisions (LATECOL) ..............................................................6-41

6.3.3.10 Excessive Collisions (EXCOL) .......................................................6-42

6.3.3.11 Transmit Underrun Errors (TXUNDER)..........................................6-42

6.3.3.12 Carrier Sense Errors (SENSERR)..................................................6-43

6.3.3.13 Receive Resource Errors (RXRERR).............................................6-44

6.3.3.14 Receive Overrun Errors (RXOVERR).............................................6-44

6.3.3.15 Receive Symbol Errors (RXSYMERR)...........................................6-45

6.3.3.16 Excessive Length Error Register (LENERR)..................................6-45

6.3.3.17 Receive Jabbers (RXJAB)..............................................................6-46

6.3.3.18 Undersize Frames (UNDERFRM)..................................................6-46

6.3.3.19 SQE Test Errors (SQERR).............................................................6-47

6.3.3.20 Received Length Field Mismatch (RXLEN)....................................6-47

6.3.3.21 Transmitted Pause Frames (TXPAUSEFM)...................................6-48

6.3.4 Matching Registers..................................................................................6-49

6.3.4.1 Hash Register Bottom (HASHBOT)..................................................6-49

6.3.4.2 Hash Register Top (HASHTOP).......................................................6-49

6.3.4.3 Specific Address 1 Bottom (SPECAD1BOT)....................................6-50

6.3.4.4 Specific Address 1 Top (SPECAD1TOP).........................................6-50

6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT)....................................6-51

6.3.4.6 Specific Address 2 Top (SPECAD2TOP).........................................6-51

6.3.4.7 Specific Address 3 Bottom (SPECAD3BOT)....................................6-52

6.3.4.8 Specific Address 3 Top (SPECAD3TOP).........................................6-52

6.3.4.9 Specific Address 4 Bottom (SPECAD4BOT)....................................6-53

6.3.4.10 Specific Address 4 Top (SPECAD4TOP).......................................6-53

6.3.4.11 Type ID Checking (IDCHK) ............................................................6-54

Chapter 7 – External Memory Controller

7.1 Theory of Operation .........................................................................................7-1

7.1.1 External Memory Map ...............................................................................7-3

7.1.1.1 nCS1 Memory Configuration..............................................................7-3

7.2 Static Memory ..................................................................................................7-3

7.2.1 Static Memory Operation...........................................................................7-3

7.2.2 Hardware Design.......................................................................................7-5

7.2.2.1 Address Connectivity..........................................................................7-5

7.2.3 Software Design........................................................................................7-9

7.2.3.1 Simple Shifting Subroutine.................................................................7-9

7.2.4 Static Memory Device Selection..............................................................7-10

7.2.4.1 Static Memory Timing Control..........................................................7-10

7.2.4.2 Bus Turnaround................................................................................7-16

7.2.4.3 Byte Lane Control.............................................................................7-16

7.2.4.4 Write Protection................................................................................7-16

7.2.4.5 nWAIT Transfers ..............................................................................7-16

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7.2.4.6 Extended Wait Transfers..................................................................7-17

7.3 Interfacing with NAND Flash..........................................................................7-17

7.3.1 Booting Example .....................................................................................7-17

7.3.2 General NAND Flash Access..................................................................7-20

7.3.2.1 Transaction Example........................................................................7-20

7.3.2.2 16-bit Example Transaction..............................................................7-21

7.3.2.3 Address Examples............................................................................7-21

7.4 Dynamic Memory ...........................................................................................7-22

7.4.1 Write-protection.......................................................................................7-22

7.4.2 Access Sequencing and Memory Width..................................................7-22

7.4.3 Bus Address Mapping .............................................................................7-22

7.4.4 Data Mask Signals ..................................................................................7-27

7.5 Register Reference ........................................................................................7-28

7.5.1 Memory Map ...........................................................................................7-28

7.5.2 Register Definitions .................................................................................7-30

7.5.2.1 Control Register (CONTROL)...........................................................7-30

7.5.2.2 Status Register (STATUS) ...............................................................7-31

7.5.2.3 Configuration Register (CONFIG) ....................................................7-32

7.5.2.4 Dynamic Memory Control Register (DYNMCTRL)...........................7-33

7.5.2.5 Dynamic Refresh Register (DYNMREF) ..........................................7-34

7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON).......7-35

7.5.2.7 Dynamic Precharge Command Period Register (PRECHARGE) ....7-36

7.5.2.8 Dynamic Memory Active to Precharge Command Period

Register (DYNM2PRE).............................................................................7-37

7.5.2.9 Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)........7-38

7.5.2.10 Dynamic Memory Last Data Out to Active Time

Register (DOACTIVE) ..............................................................................7-39

7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE).....7-40

7.5.2.12 Dynamic Memory Write Recovery Time Register (DWRT) ............7-41

7.5.2.13 Dynamic Memory Active to Active Command

Period Register (DYNACTCMD) ..............................................................7-42

7.5.2.14 Dynamic Memory Auto-Refresh Period, and Auto-Refresh

to Active Command Period Register (DYNAUTO) ...................................7-43

7.5.2.15 Dynamic Memory Exit Self-Refresh to Active Command

Time Register (DYNREFEXIT).................................................................7-44

7.5.2.16 Dynamic Memory Active Bank A to Active Bank B

Time Register (DYNACTIVEAB) ..............................................................7-45

7.5.2.17 Dynamic Memory Load Mode Register to

Active Command Time Register (DYNAMICTMRD) ................................7-46

7.5.2.18 Static Memory Extended Wait Register (WAIT) .............................7-47

7.5.2.19 Dynamic Configuration Register for nDCS0

and nDCS1 (DYNCFGx)...........................................................................7-48

7.5.2.20 Dynamic Memory RAS and CAS Delay Register for

nDCS0 and nDCS1 (DYNRASCASx).......................................................7-51

7.5.2.21 Static Memory Configuration Register (SCONFIGx)......................7-52

7.5.2.22 Static Memory Write Enable Delay Registers (SWAITWENx)........7-54

7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx)......7-55

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7.5.2.24 Static Memory Read Delay Registers (SWAITRDx).......................7-56

7.5.2.25 Static Memory Page Mode Read Delay Registers

(SWAITPAGEx)........................................................................................7-57

7.5.2.26 Static Memory Write Delay Registers (SWAITWRx)......................7-58

7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)................7-59

Chapter 8 – General Purpose Input/Output

8.1 Theory of Operation .........................................................................................8-1

8.1.1 Port Configuration .....................................................................................8-1

8.1.1.1 Multiplexing.........................................................................................8-2

8.2 Register Reference ..........................................................................................8-7

8.2.1 Memory Map .............................................................................................8-7

8.2.2 Register Descriptions ................................................................................8-8

8.2.2.1 Port A/C/E/G/I/K/M Data Registers (P1DRx)......................................8-8

8.2.2.2 Port B/D/F/H/J/L/N Data Register (P2DRx)........................................8-9

8.2.2.3 Port A/C/E/G/I/K Data Direction Register (P1DDRx)........................8-10

8.2.2.4 Port B/D/F/H/L/N Data Direction Register ........................................8-11

Chapter 9 – I2C Module

9.1 Theory of Operation .........................................................................................9-2

9.1.1 Setting I

9.1.2 Interrupt Handling......................................................................................9-4

9.1.3 Slave Mode ...............................................................................................9-5

9.1.4 Master Mode .............................................................................................9-5

9.1.5 Resetting a Locked Slave..........................................................................9-5

9.2 Register Reference ..........................................................................................9-6

9.2.1 Memory Map .............................................................................................9-6

9.2.2 Register Definitions ...................................................................................9-7

9.2.2.1 I

9.2.2.2 I

9.2.2.3 I

9.2.2.4 I

9.2.2.5 I

9.2.2.6 I

9.2.2.7 I

2

C Clock Timing ...........................................................................9-3

2

C Configuration Register (ICCON)...................................................9-7

2

C Slave Address Register (ICSAR) .................................................9-8

2

C Upper Slave Address Register (ICUSAR)....................................9-9

2

C Data Register (ICDATA)...............................................................9-9

2

C Clock High Time Register (ICHCNT)..........................................9-10

2

C Clock Low Time Register (ICLCNT)...........................................9-10

2

C Status Register (ICSTAT)...........................................................9-11

Chapter 10 – I2S Converter

10.1 Theory of Operation .....................................................................................10-3

10.1.1 Conversion ............................................................................................10-3

10.1.2 Driving/Latching Edges .........................................................................10-4

10.1.3 Transmission.........................................................................................10-5

10.1.3.1 Master Mode Transmission............................................................10-5

10.1.3.2 Slave Mode Transmission..............................................................10-6

10.1.4 Reception ..............................................................................................10-7

10.1.4.1 Master Mode Reception .................................................................10-7

10.1.4.2 Slave Mode Reception ...................................................................10-9

10.1.5 Suppression of SSPFSSIN..................................................................10-10

10.1.6 Channel Management.........................................................................10-10

10.1.7 Interrupts.............................................................................................10-11

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10.1.7.1 SSP Protocol Error Interrupt.........................................................10-11

10.1.7.2 External Codec Protocol Error Interrupt .......................................10-11

10.1.7.3 Transmit FIFO Underrun Interrupt................................................10-11

10.1.7.4 Receive Interrupt..........................................................................10-12

10.1.7.5 Transmit Interrupt.........................................................................10-12

10.1.7.6 Receive Overrun Interrupt............................................................10-12

10.1.7.7 Receive Timeout Interrupt............................................................10-12

10.1.7.8 I

2

SINTR........................................................................................10-12

10.2 Register Reference ....................................................................................10-13

10.2.1 Memory Map .......................................................................................10-13

10.2.2 Register Descriptions..........................................................................10-14

10.2.2.1 Control Register (CTRL)...............................................................10-14

10.2.2.2 Status Register (STAT) ................................................................10-16

10.2.2.3 Interrupt Mask Set or Clear Register (IMSC)................................10-17

10.2.2.4 Raw Interrupt Status Register (RIS).............................................10-18

10.2.2.5 Masked Interrupt Status Register (MIS).......................................10-19

10.2.2.6 Interrupt Clear Register (ICR).......................................................10-20

Chapter 11 – I/O Configuration

11.1 Theory of Operation .....................................................................................11-1

11.2 Register Reference ......................................................................................11-2

11.2.1 Memory Map .........................................................................................11-2

11.2.2 Register Definitions...............................................................................11-4

11.2.2.1 Multiplexing Control 1 Register (MUXCTL1) ..................................11-4

11.2.2.2 Resistor Configuration Control 1 Register (RESCTL1) ..................11-5

11.2.2.3 Multiplexing Control 3 Register (MUXCTL3) ..................................11-6

11.2.2.4 Resistor Configuration Control 3 Register (RESCTL3) ..................11-6

11.2.2.5 Multiplexing Control 4 Register (MUXCTL4) ..................................11-7

11.2.2.6 Resistor Configuration Control 4 Register (RESCTL4) ..................11-8

11.2.2.7 Multiplexing Control 5 Register (MUXCTL5) ..................................11-9

11.2.2.8 Resistor Configuration Control 5 Register (RESCTL5) ................11-10

11.2.2.9 Multiplexing Control 6 Register (MUXCTL6) ................................11-12

11.2.2.10 Resistor Configuration Control 6 Register (RESCTL6) ..............11-13

11.2.2.11 Multiplexing Control 7 Register (MUXCTL7) ..............................11-14

11.2.2.12 Resistor Configuration Control 7 Register (RESCTL7) ..............11-16

11.2.2.13 Multiplexing Control 10 Register (MUXCTL10) ..........................11-18

11.2.2.14 Resistor Configuration Control 10 Register (RESCTL10)..........11-20

11.2.2.15 Multiplexing Control 11 Register (MUXCTL11) ..........................11-22

11.2.2.16 Resistor Configuration Control 11 Register (RESCTL11)..........11-24

11.2.2.17 Multiplexing Control 12 Register (MUXCTL12) ..........................11-26

11.2.2.18 Resistor Configuration Control 12 Register (RESCTL12)..........11-27

11.2.2.19 Resistor Configuration Control 13 Register (RESCTL13)..........11-29

11.2.2.20 Multiplexing Control 14 Register (MUXCTL14) ..........................11-30

11.2.2.21 Multiplexing Control 15 Register (MUXCTL15) ..........................11-32

11.2.2.22 Resistor Configuration Control 15 Register (RESCTL15)..........11-32

11.2.2.23 Resistor Configuration Control 17 Register (RESCTL17)..........11-33

11.2.2.24 Multiplexing Control 19 Register (MUXCTL19) ..........................11-34

11.2.2.25 Resistor Configuration Control 19 Register (RESCTL19)..........11-36

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11.2.2.26 Multiplexing Control 20 Register (MUXCTL20) ..........................11-38

11.2.2.27 Resistor Configuration Control 20 Register (RESCTL20)..........11-40

11.2.2.28 Multiplexing Control 21 Register (MUXCTL21) ..........................11-42

11.2.2.29 Resistor Configuration Control 21 Register (RESCTL21)..........11-43

11.2.2.30 Multiplexing Control 22 Register (MUXCTL22) ..........................11-44

11.2.2.31 Resistor Configuration Control 22 Register (RESCTL22)..........11-46

11.2.2.32 Multiplexing Control 23 Register (MUXCTL23) ..........................11-48

11.2.2.33 Resistor Configuration Control 23 Register (RESCTL23)..........11-50

11.2.2.34 Multiplexing Control 24 Register (MUXCTL24) ..........................11-52

11.2.2.35 Resistor Configuration Control 24 Register (RESCTL24)..........11-53

11.2.2.36 Multiplexing Control 25 Register (MUXCTL25) ..........................11-54

Chapter 12 – Real Time Clock

12.1 Theory of Operation .....................................................................................12-1

12.1.1 Configuring the RTC for Use.................................................................12-2

12.2 Register Reference ......................................................................................12-3

12.2.1 Memory Map .........................................................................................12-3

12.2.2 Register Descriptions............................................................................12-3

12.2.2.1 Data Register (DR).........................................................................12-3

12.2.2.2 Match Register (MR) ......................................................................12-4

12.2.2.3 Load Register (LR).........................................................................12-4

12.2.2.4 Control Register (CR).....................................................................12-5

12.2.2.5 Interrupt Mask Set or Clear Register (IMSC)..................................12-5

12.2.2.6 Raw Interrupt Status Register (RIS)...............................................12-6

12.2.2.7 Masked Interrupt Status Register (MIS).........................................12-6

12.2.2.8 Interrupt Clear Register (ICR).........................................................12-7

Chapter 13 – Reset, Clock, and Power Controller

13.1 Theory of Operation .....................................................................................13-2

13.1.1 System PLL and USB PLL Reset..........................................................13-3

13.1.2 Reset Generation..................................................................................13-3

13.1.3 Clock Generation...................................................................................13-3

13.1.3.1 Enabling Clocks Prior to Programming Registers ..........................13-3

13.1.3.2 Peripheral Block Clocks..................................................................13-4

13.1.3.3 External Clock Generation (CLKOUT)............................................13-4

13.1.4 Power Modes ........................................................................................13-6

13.1.4.1 Active Mode....................................................................................13-6

13.1.4.2 Standby Mode ................................................................................13-6

13.1.4.3 Sleep Mode ....................................................................................13-6

13.1.4.4 Stop1 Mode....................................................................................13-6

13.1.4.5 Stop2 Mode....................................................................................13-7

13.1.4.6 Power Control in JTAG Mode.........................................................13-7

13.2 Register Reference ......................................................................................13-8

13.2.1 Memory Map .........................................................................................13-8

13.2.2 Register Descriptions............................................................................13-8

13.2.2.1 Control Register (CTRL).................................................................13-9

13.2.2.2 Identification Register (CHIPID)...................................................13-10

13.2.2.3 Remap Control Register (REMAP)...............................................13-11

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13.2.2.4 Software Reset Register (SOFTRESET)......................................13-14

13.2.2.5 Reset Status Register (RSTSTATUS)..........................................13-15

13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR).........................13-16

13.2.2.7 System Clock Prescaler Register (SYSCLKPRE)........................13-17

13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE)............................13-18

13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0).....................13-19

13.2.2.10 Peripheral Clock Control Register 1 (PCLKCTRL1)...................13-20

13.2.2.11 AHB Clock Control Register (AHBCLKCTRL)............................13-21

13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0).......................13-22

13.2.2.13 Peripheral Clock Select Register 1 (PCLKSEL1).......................13-23

13.2.2.14 Silicon Revision Register (SILICONREV)...................................13-24

13.2.2.15 LCD Clock Prescaler Register (LCDPRE)..................................13-25

13.2.2.16 SSP Clock Prescaler Register (SSPPRE)..................................13-26

13.2.2.17 ADC Clock Prescaler Register (ADCPRE).................................13-27

13.2.2.18 USB Clock Prescaler Register (USBPRE) .................................13-28

13.2.2.19 External Interrupt Configuration Register (INTCONFIG)............13-29

13.2.2.20 External Interrupt Clear Register (INTCLR)................................13-31

13.2.2.21 Core Clock Configuration Register (CORECONFIG).................13-32

13.2.2.22 System PLL Control Register (SYSPLLCTL) .............................13-33

13.2.2.23 USB PLL Control Register (USBPLLCTL)..................................13-34

Chapter 14 – Synchronous Serial Port

14.1 Theory of Operation .....................................................................................14-1

14.1.1 Timing Waveforms ................................................................................14-3

14.1.2 Motorola SPI Frame Format..................................................................14-4

14.1.3 Texas Instruments Frame Format.........................................................14-5

14.1.4 National Semiconductor Frame Format ................................................14-6

14.1.5 Clock Generation...................................................................................14-7

14.1.6 Interrupts...............................................................................................14-7

14.1.6.1 Receive Interrupt............................................................................14-7

14.1.6.2 Transmit Interrupt...........................................................................14-8

14.1.6.3 Receive Overrun Interrupt..............................................................14-8

14.1.6.4 Receive Timeout Interrupt..............................................................14-8

14.1.6.5 SSPINTR........................................................................................14-8

14.2 Register Reference ......................................................................................14-9

14.2.1 Memory Map .........................................................................................14-9

14.2.2 Register Descriptions..........................................................................14-10

14.2.2.1 Control Register 0 (CTRL0)..........................................................14-10

14.2.2.2 Control Register 1 (CTRL1)..........................................................14-12

14.2.2.3 Data Register – Receive/Transmit FIFO Register (DR)...............14-13

14.2.2.4 Status Register (SR).....................................................................14-14

14.2.2.5 Clock Prescale Register (CPSR)..................................................14-15

14.2.2.6 Interrupt Mask Set and Clear Register (IMSC).............................14-16

14.2.2.7 Raw Interrupt Status Register (RIS).............................................14-17

14.2.2.8 Masked Interrupt Status Register (MIS).......................................14-18

14.2.2.9 Interrupt Clear Register (ICR).......................................................14-19

14.2.2.10 DMA Control Register (DCR) .....................................................14-20

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Chapter 15 – Timers

15.1 Theory of Operation .....................................................................................15-2

15.1.1 Counter Clear Upon Compare Match....................................................15-3

15.1.2 Capture Signal Sampling.......................................................................15-4

15.1.3 PWM Mode............................................................................................15-4

15.1.3.1 Timer Interrupts..............................................................................15-5

15.2 Register Reference ......................................................................................15-6

15.2.1 Memory Map .........................................................................................15-6

15.2.2 Register Descriptions............................................................................15-7

15.2.2.1 Timer 0 Control Register (CTRL0)..................................................15-7

15.2.2.2 Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0) 15-8

15.2.2.3 Timer 0 Interrupt Control Register (INTEN0)................................15-10

15.2.2.4 Timer 0 Status Register (STATUS0)............................................15-11

15.2.2.5 Timer 0 Counter Register (CNT0) ................................................15-12

15.2.2.6 Timer 0 Compare Registers (T0CMPn)........................................15-13

15.2.2.7 Timer 0 Capture Registers (CAPn)...............................................15-14

15.2.2.8 Timer 1 Control Register (CTRL1)................................................15-15

15.2.2.9 Timer 1 Interrupt Control Register (INTEN1)................................15-17

15.2.2.10 Timer 1 Status Register (STATUS1)..........................................15-18

15.2.2.11 Timer 1 Counter Register (CNT1) ..............................................15-19

15.2.2.12 Timer 1 Compare Registers (T1CMPn)......................................15-20

15.2.2.13 Timer 1 Capture Registers (T1CAPn) ........................................15-21

15.2.2.14 Timer 2 Control Register (CTRL2)..............................................15-22

15.2.2.15 Timer 2 Interrupt Control Register (INTEN2)..............................15-24

15.2.2.16 Timer 2 Status Register (STATUS2)..........................................15-25

15.2.2.17 Timer 2 Counter Register (CNT2) ..............................................15-26

15.2.2.18 Timer 2 Compare Registers (T2CMPn)......................................15-27

15.2.2.19 Timer 2 Capture Registers (T2CAPn) ........................................15-28

Chapter 16 – UARTs

16.1 Theory of Operation .....................................................................................16-2

16.1.1 Transmitting Data..................................................................................16-3

16.1.2 Receive Data Frame .............................................................................16-3

16.1.3 Nine-bit Mode........................................................................................16-4

16.1.4 Status Conditions ..................................................................................16-4

16.1.5 On-Chip DMA Capabilities ....................................................................16-5

16.1.6 Programming the SIR............................................................................16-5

16.1.7 Hardware Flow Control..........................................................................16-6

16.1.7.1 RTS Flow Control...........................................................................16-6

16.1.7.2 CTS Flow Control...........................................................................16-6

16.1.8 Programming Control Registers............................................................16-6

16.2 Interrupts......................................................................................................16-7

16.2.1 UARTINTR ............................................................................................16-7

16.3 Register Reference ......................................................................................16-7

16.3.1 Memory Map .........................................................................................16-7

16.3.2 Register Definitions...............................................................................16-8

16.3.2.1 Data Register (UARTDR)...............................................................16-8

16.3.2.2 Receive Status/Error Clear Register (UARTRSR/UARTECR).......16-9

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16.3.2.3 Flag Register (UARTFR)..............................................................16-11

16.3.2.4 IrDA Low-Power Counter Register (UARTILPR)..........................16-12

16.3.2.5 Integer Baud Rate Divisor Register (UARTIBRD)........................16-13

16.3.2.6 Fractional Baud Rate Divisor Register (UARTFBRD) ..................16-14

16.3.2.7 Line Control Register (UARTLCR_H)...........................................16-15

16.3.2.8 UART Control Register (UARTCR) ..............................................16-17

16.3.2.9 Interrupt FIFO Level Select Register (UARTIFLS).......................16-19

16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC)........................16-20

16.3.2.11 Raw Interrupt Status Register (UARTRIS).................................16-22

16.3.2.12 Masked Interrupt Status Register (UARTMIS) ...........................16-24

16.3.2.13 Interrupt Clear Register (UARTICR)...........................................16-26

16.3.2.14 UART0 DMA Control Register (DMACTRL)...............................16-27

Chapter 17 – Universal Serial Bus Device

17.1 Theory of Operation .....................................................................................17-1

17.1.1 Endpoints ..............................................................................................17-2

17.1.1.1 Isochronous Endpoints...................................................................17-3

17.1.2 FIFOs ....................................................................................................17-3

17.1.3 Serial Interface Engine (SIE).................................................................17-3

17.1.3.1 OUT_PKT_RDY Interrupt Operation for Endpoint 0.......................17-3

17.1.4 DMA Interface .......................................................................................17-4

17.1.4.1 DMA Modes....................................................................................17-4

17.1.4.2 DMA Bus Cycles.............................................................................17-4

17.1.4.3 Bus Errors.......................................................................................17-4

17.1.5 DMA Operation......................................................................................17-5

17.1.5.1 DMA Mode 0: OUT Endpoints........................................................17-5

17.1.5.2 DMA Mode 0: IN Endpoints............................................................17-5

17.1.5.3 DMA Mode 1: OUT Endpoints........................................................17-6

17.1.5.4 DMA Mode 1: IN Endpoints............................................................17-7

17.1.6 Remote Wakeup....................................................................................17-7

17.2 Register Reference ......................................................................................17-8

17.2.1 Memory Map .........................................................................................17-8

17.2.2 Register Definitions.............................................................................17-10

17.2.2.1 Function Address Register (FAR).................................................17-10

17.2.2.2 Power Management Register (PMR)............................................17-11

17.2.2.3 Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR).......................17-12

17.2.2.4 Interrupt Register for OUT Endpoint 1 and 2 (OIR)......................17-13

17.2.2.5 Interrupt Register for common USB interrupts (UIR)....................17-14

17.2.2.6 IN Interrupt Enable Register (IIE).................................................17-15

17.2.2.7 OUT Interrupt Enable Register (OIE) ...........................................17-16

17.2.2.8 Interrupt Enable Register (UIE)....................................................17-17

17.2.2.9 Frame Number Registers (FRAMEx) ...........................................17-18

17.2.3 Indexed Registers ...............................................................................17-19

17.2.3.1 Index Register (INDEX)................................................................17-19

17.2.3.2 IN Maximum Packet Size Register (INMAXP)..............................17-20

17.2.3.3 Control Status Register for EP 0 (CSR0) .....................................17-21

17.2.3.4 Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1)...........17-23

17.2.3.5 Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2)...........17-25

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17.2.3.6 OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)...17-26

17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR 1)..17-27

17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2) . ..17-29

17.2.3.9 Count 0 Register (OUTCOUNT0).................................................17-30

17.2.3.10 Count 1 Register (OUTCOUNT1)...............................................17-30

17.2.3.11 Out Count 2 Register (OUTCOUNT2)........................................17-31

17.2.3.12 FIFOs for Endpoints 0-3 (FIFOx)................................................17-31

17.2.3.13 Pending DMA Interrupts Register (INTR)...................................17-32

17.2.3.14 DMA Channel x Control Register (CNTLx).................................17-33

17.2.3.15 DMA Channel x AHB Memory Address Register.......................17-34

17.2.3.16 DMA Channel x Byte Count Register (COUNTx).......................17-34

Chapter 18 – Vectored Interrupt Controller

18.1 Theory of Operation .....................................................................................18-1

18.1.1 VIC Interrupt Listing...............................................................................18-2

18.1.2 Vectored Interrupts................................................................................18-3

18.1.3 External Interrupts.................................................................................18-3

18.1.4 Clearing Interrupts.................................................................................18-4

18.1.5 Priority ...................................................................................................18-4

18.1.6 External Level-Sensitive Interrupts........................................................18-4

18.1.7 Software Guidelines ..............................................................................18-4

18.2 Register Reference ......................................................................................18-5

18.2.1 Memory Map .........................................................................................18-5

18.2.2 Register Descriptions............................................................................18-6

18.2.2.1 IRQ Status Register (IRQSTATUS)................................................18-6

18.2.2.2 FIQ Status Register (FIQSTATUS) ................................................18-7

18.2.2.3 Raw Interrupt Status Register (RAWINTR)....................................18-7

18.2.2.4 Interrupt Select Register (INTSELECT)..........................................18-8

18.2.2.5 Interrupt Enable Register (INTENABLE)........................................18-8

18.2.2.6 Interrupt Enable Clear Register (INTENCLEAR)............................18-9

18.2.2.7 Software Interrupt Register (SOFTINT)........................................18-10

18.2.2.8 Software Interrupt Clear Register (SOFTINTCLEAR)..................18-11

18.2.2.9 Vector Address Register (VECTADDR) .......................................18-12

18.2.2.10 Default Vector Address Register (DEFVECTADDR)..................18-12

18.2.2.11 Vector Address Registers (VECTADDRx)..................................18-13

18.2.2.12 Vector Control Registers (VECTCTRLx)....................................18-14

18.2.2.13 Interrupt Test Output Register (ITOP)........................................18-15

Chapter 19 – Watchdog Timer

19.1 Theory of Operation .....................................................................................19-1

19.1.1 WDT Operation Details .........................................................................19-3

19.2 Register Reference ......................................................................................19-4

19.2.1 Memory Map .........................................................................................19-4

19.2.2 Register Descriptions............................................................................19-5

19.2.2.1 Control Register (CTL) ...................................................................19-5

19.2.2.2 Counter Reset Register (RST) .......................................................19-6

19.2.2.3 Status Register (STATUS) .............................................................19-7

19.2.2.4 Current Watchdog Count Registers (COUNT[3:0]) ........................19-8

Chapter 20 – Glossary

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List of Figures

Preface

Figure 1. Multiplexer...............................................................................................xxxviii

Figure 2. Register with Bit-Field Named..................................................................xxxix

Figure 3. Register with Multiple Bit-Fields Named ..................................................xxxix

Figure 4. Register with Bit-Field Numbered ............................................................xxxix

Chapter 1 – Overview

Figure 1-1. LH79524/LH79525 Block Diagram ..........................................................1-2

Figure 1-2. Standard Clocking Modes........................................................................1-6

Figure 1-3. Fastbus Clocking Mode ...........................................................................1-7

Figure 1-4. Reset Circuit for TAP Controller...............................................................1-9

Figure 1-5. Reset Circuit for TAP Controller Including a Push Button......................1-10

Figure 1-6. Active Pullup Circuit...............................................................................1-11

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

Figure 2-1. ADC Block Diagram.................................................................................2-2

Figure 2-2. Bias-and-Control Network Block Diagram ...............................................2-4

Figure 2-3. Simplified N-bit SAR Architecture............................................................2-5

Figure 2-4. Example of a 4-bit SAR ADC Operation..................................................2-6

Figure 2-5. Use of the BATCNTL Pin.........................................................................2-7

Chapter 3 – Boot Controller

Figure 3-1. Boot Controller Block Diagram.................................................................3-1

Figure 3-2. Active Pullup Circuit.................................................................................3-5

Chapter 4 – Color Liquid Crystal Display Controller

Figure 4-1. LH79524/LH79525 LCD System, Simplified Block Diagram....................4-1

Figure 4-2. Block Diagram of a Typical Advanced LCD Panel...................................4-2

Figure 4-3. Color LCD Controller Block Diagram.......................................................4-4

Figure 4-4. LCD Panel Power Sequencing ..............................................................4-15

Figure 4-5. ALI Simplified Block Diagram.................................................................4-17

Figure 4-6. STN Horizontal Timing Diagram............................................................4-43

Figure 4-7. STN Vertical Timing Diagram ................................................................4-44

Figure 4-8. TFT Horizontal Timing Diagram.............................................................4-45

Figure 4-9. TFT Vertical Timing Diagram.................................................................4-46

Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram......................................4-47

Figure 4-11. AD-TFT, HR-TFT Vertical Timing Diagram..........................................4-47

Chapter 5 – Direct Memory Access Controller

Figure 5-1. Basic DMA Timing ...................................................................................5-4

Chapter 6 – Ethernet MAC Controller

Figure 6-1. EMAC Block Diagram..............................................................................6-2

Figure 6-2. Address Matching..................................................................................6-15

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List of Figures LH79524/LH79252 User’s Guide

Chapter 7 – External Memory Controller

Figure 7-1. External Memory Controller Block Diagram.............................................7-2

Figure 7-2. Automatic Address Shifting......................................................................7-4

Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices.............................7-6

Figure 7-4. 16-bit Memory Bank Constructed From 8-bit Devices.............................7-6

Figure 7-5. 8-bit Memory Bank...................................................................................7-6

Figure 7-6. 32-bit (left) and 16-bit (right) Memory Banks Constructed

From 16-bit Devices...............................................................................................7-7

Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device...............7-7

Figure 7-8. Typical Memory Connection Diagram......................................................7-8

Figure 7-9. Pre-shifting Routine .................................................................................7-9

Figure 7-10. Static Read Transaction with Zero Wait States ...................................7-11

Figure 7-11. Static Read Transaction with Three Wait States .................................7-12

Figure 7-12. Static Write Transaction with Zero Wait States....................................7-13

Figure 7-13. Static Write Transaction with Two Wait States....................................7-15

Figure 7-14. Connection to NAND Flash..................................................................7-19

Figure 7-15. NAND Flash Timing Example..............................................................7-21

Chapter 9 – I2C Module

Figure 9-1. I2C Module Block Diagram.......................................................................9-1

Figure 9-2. I

2

C Bus Protocol ......................................................................................9-2

Chapter 10 – I2S Converter

Figure 10-1. I2S Converter Block Diagram...............................................................10-2

Figure 10-2. TI SSP Frame Format..........................................................................10-3

Figure 10-3. I

2

S Format............................................................................................10-3

Figure 10-4. Driving/Latching Diagram.....................................................................10-4

Figure 10-5. I
Figure 10-6. I
Figure 10-7. I
Figure 10-8. I
Figure 10-9. I
Figure 10-10. I
Figure 10-11. I
Figure 10-12. I

2

S Master Mode Transmission Block Diagram...................................10-5

2

S Master Mode Transmission Timing Diagram.................................10-5

2

S Slave Mode Transmission Block Diagram.....................................10-6

2

S Slave Mode Transmission Timing Diagram...................................10-7

2

S Master Mode Reception Block Diagram ........................................10-8

2

S Master Mode Reception Timing Diagram ....................................10-8

2

S Slave Mode Reception Block Diagram ........................................10-9

2

S Slave Mode Reception Timing Diagram ......................................10-9

Chapter 12 – Real Time Clock

Figure 12-1. RTC Block Diagram.............................................................................12-1

Chapter 13 – Reset, Clock, and Power Controller

Figure 13-1. RCPC Block Diagram ..........................................................................13-2

Figure 13-2. USB Clock Divider Chain.....................................................................13-4

Figure 13-3. Remap = 0b00...................................................................................13-11

Figure 13-4. Remap = 0b01...................................................................................13-12

Figure 13-5. Remap = 0b10...................................................................................13-12

Figure 13-6. Remap = 0b11...................................................................................13-13

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Chapter 14 – Synchronous Serial Port

Figure 14-1. SSP Timing Waveform Parameters.....................................................14-3

Figure 14-2. Motorola SPI Frame Format (Continuous Transfer) ............................14-4

Figure 14-3. Motorola SPI Frame Format with SPH = 0 ..........................................14-4

Figure 14-4. Texas Instruments Synchronous Serial Frame Format

(Single Transfer)...................................................................................................14-5

Figure 14-5. Texas Instruments Synchronous Serial Frame Format

(Continuous Transfers).........................................................................................14-5

Figure 14-6. Microwire Frame Format (Single Transfer)..........................................14-6

Figure 14-7. Microwire Frame Format (Continuous Transfers)................................14-7

Chapter 15 – Timers

Figure 15-1. Timer Block Diagram ...........................................................................15-2

Figure 15-2. Count Clock Timing (HCLK in Phase with CTCLK) .............................15-3

Figure 15-3. Count Clock Timing (HCLK not in Phase with CTCLK).......................15-3

Figure 15-4. Capture Signal Synchronization Timing...............................................15-4

Figure 15-5. PWM Output Signal Timing..................................................................15-5

Chapter 16 – UARTs

Figure 16-1. UART0, UART1, and UART2 Block Diagram......................................16-2

Chapter 17 – Universal Serial Bus Device

Figure 17-1. USB Block Diagram.............................................................................17-1

Figure 17-2. USB Communication Endpoints...........................................................17-2

Chapter 19 – Watchdog Timer

Figure 19-1. Watchdog Timer Block Diagram..........................................................19-2

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List of Tables

Preface

Table 1. Register Name ......................................................................................... xxxvii

Table 2. Bit Fields...................................................................................................xxxvii

Chapter 1 – Overview

Table 1-1. LH79524/LH79525 Differences.................................................................1-1

Table 1-2. Clock Descriptions ....................................................................................1-4

Table 1-3. Port C Settings For Boot...........................................................................1-8

Table 1-4. Default Bus Master Priority .....................................................................1-12

Table 1-5. AHB Memory Mapping............................................................................1-13

Table 1-6. External Static Memory Section Mapping...............................................1-13

Table 1-8. Internal SRAM Memory Section Mapping...............................................1-14

Table 1-9. Boot ROM Memory Section Mapping......................................................1-14

Table 1-7. SDRAM Memory Section Mapping .........................................................1-14

Table 1-11. Primary AHB Peripheral Register Mapping...........................................1-15

Table 1-10. AHB Memory Map on Power-up when Boot Configuration = 0bX1XX..1-15

Table 1-12. APB Peripheral Register Mapping ........................................................1-16

Chapter 2 – Analog-to-Digital Converter/Brownout Detector

Table 2-1. ADC Register Summary..........................................................................2-10

Table 2-2. HW Register............................................................................................2-11

Table 2-3. HW Fields................................................................................................2-11

Table 2-4. In + Mux Definition..................................................................................2-12

Table 2-5. LW Register ............................................................................................2-13

Table 2-6. LW Fields................................................................................................2-13

Table 2-7. RR Register.............................................................................................2-14

Table 2-8. RR Fields ................................................................................................2-14

Table 2-9. IM Register..............................................................................................2-15

Table 2-10. IM Fields................................................................................................2-15

Table 2-11. PC Register...........................................................................................2-16

Table 2-12. PC Fields...............................................................................................2-16

Table 2-13. Touch Screen Controller Power Modes................................................2-17

Table 2-14. GC Register ..........................................................................................2-18

Table 2-15. GC Fields..............................................................................................2-18

Table 2-16. GS Register...........................................................................................2-19

Table 2-17. GS Fields ..............................................................................................2-19

Table 2-18. IS Register ............................................................................................2-20

Table 2-19. IS Fields................................................................................................2-20

Table 2-20. FS Register...........................................................................................2-21

Table 2-21. FS Fields...............................................................................................2-21

Table 2-22. Sample Entries for Control Bank...........................................................2-22

Table 2-23. IHWCTRL Register ...............................................................................2-23

Table 2-24. IHWCTRL Fields...................................................................................2-23

Table 2-25. ILWCTRL Register................................................................................2-24

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Table 2-26. ILWCTRL Fields....................................................................................2-24

Table 2-27. MIS Register .........................................................................................2-25

Table 2-28. MIS Fields.............................................................................................2-25

Table 2-29. IC Register............................................................................................2-26

Table 2-30. IC Fields................................................................................................2-26

Chapter 3 – Boot Controller

Table 3-1. Boot Configuration for Silicon Version A.0................................................3-3

Table 3-2. Boot Configuration for Silicon Version A.1................................................3-3

Table 3-3. Alternate Pin Function During NAND Flash Booting.................................3-5

Table 3-4. Boot Parameters for I2C ...........................................................................3-6

Table 3-5. Supported Devices....................................................................................3-6

Table 3-6. UART0 Boot Parameters ..........................................................................3-7

Table 3-7. Boot Controller Register Summary ...........................................................3-7

Table 3-8. PBC Register ............................................................................................3-8

Table 3-9. PBC Fields................................................................................................3-8

Table 3-10. CS1OV Register......................................................................................3-9

Table 3-11. CS1OV Fields .........................................................................................3-9

Table 3-12. EPM Register........................................................................................3-10

Table 3-13. EPM Fields............................................................................................3-10

Chapter 4 – Color Liquid Crystal Display Controller

Table 4-1. Pixel Display Arrangement........................................................................4-6

Table 4-2. Frame Buffer Pixel Storage Format [31:16] ..............................................4-6

Table 4-3. Frame Buffer Pixel Storage Format [15:0] ................................................4-7

Table 4-4. Palette Data Storage (LH79525 with 12-Bit CLCDC)................................4-8

Table 4-5. Palette Data Storage (LH79524 with 16-Bit CLCDC)................................4-8

Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels...............................4-10

Table 4-7. Supported Color STN LCD Panels (LH79524 only)................................4-10

Table 4-8. Supported Mono-STN LCD Panels.........................................................4-10

Table 4-9. Color STN Intensities From Gray-Scale Modulation...............................4-11

Table 4-10. LH79524 LCD Data Multiplexing...........................................................4-12

Table 4-11. LH79525 LCD Data Multiplexing...........................................................4-13

Table 4-12. Usable Minimum Values Affecting STN Back Porch Width...................4-14

Table 4-13. CLCDC Register Summary...................................................................4-19

Table 4-14. TIMING0 Register.................................................................................4-20

Table 4-15. TIMING0 Fields.....................................................................................4-20

Table 4-16. TIMING1 Register.................................................................................4-22

Table 4-17. TIMING1 Fields.....................................................................................4-22

Table 4-18. TIMING2 Register.................................................................................4-24

Table 4-19. TIMING2 Fields.....................................................................................4-24

Table 4-20. UPBASE Register.................................................................................4-26

Table 4-21. UPBASE Fields.....................................................................................4-26

Table 4-22. LPBASE Register..................................................................................4-27

Table 4-23. LPBASE Register Fields.......................................................................4-27

Table 4-24. INTREN Register ..................................................................................4-28

Table 4-25. INTREN Fields......................................................................................4-28

Table 4-26. CTRL Register ......................................................................................4-29

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Table 4-27. CTRL Fields..........................................................................................4-30

Table 4-28. STATUS Register..................................................................................4-32

Table 4-29. STATUS Fields .....................................................................................4-32

Table 4-30. INTERRUPT Register...........................................................................4-33

Table 4-31. INTERRUPT Fields...............................................................................4-33

Table 4-32. INTCLR Register...................................................................................4-34

Table 4-33. INTCLR Fields.......................................................................................4-34

Table 4-34. UPCURR Register ................................................................................4-35

Table 4-35. UPCURR Fields....................................................................................4-35

Table 4-36. LPCURR Register.................................................................................4-35

Table 4-37. LCDLPCURR Fields..............................................................................4-35

Table 4-38. PALETTE Register (LH79525 with 12-Bit CLCDC)...............................4-36

Table 4-39. PALETTE Fields (LH79525 with 12-Bit CLCDC) ..................................4-36

Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)...............................4-37

Table 4-41. PALETTE Fields (LH79524 with 16-Bit CLCDC) ..................................4-37

Table 4-42. ALI Register Summary..........................................................................4-38

Table 4-43. ALISETUP Register ..............................................................................4-38

Table 4-44. ALISETUP Fields..................................................................................4-38

Table 4-45. ALICTRL Register.................................................................................4-39

Table 4-46. ALICTRL Fields.....................................................................................4-39

Table 4-47. ALITIMING1 Register............................................................................4-40

Table 4-48. ALITIMING1 Fields................................................................................4-40

Table 4-49. ALITIMING2 Register............................................................................4-41

Table 4-50. ALITIMING2 Fields................................................................................4-41

Chapter 5 – Direct Memory Access Controller

Table 5-1. DMA Controller Stream Assignments and Request Priority......................5-1

Table 5-2. DMA Memory Map....................................................................................5-5

Table 5-3. DMA Data Stream Register Summary

(One Set of Registers for Each of the Four Data Streams in Table 5-2)................5-5

Table 5-4. SOURCELO Register................................................................................5-6

Table 5-5. SOURCELO Fields ...................................................................................5-6

Table 5-6. SOURCEHI Register.................................................................................5-6

Table 5-7. SOURCEHI Fields.....................................................................................5-6

Table 5-8. DESTLO Register .....................................................................................5-7

Table 5-9. DESTLO Fields.........................................................................................5-7

Table 5-10. DESTHI Register.....................................................................................5-7

Table 5-11. DESTHI Fields ........................................................................................5-7

Table 5-12. MAX Register..........................................................................................5-8

Table 5-13. MAX Fields..............................................................................................5-8

Table 5-14. CTRL Register ........................................................................................5-9

Table 5-15. CTRL Fields............................................................................................5-9

Table 5-16. DMA Data Width ...................................................................................5-10

Table 5-17. DMA Burst Size.....................................................................................5-10

Table 5-18. Constraints on CTRL Field Values Based on Stream Type..................5-11

Table 5-19. CURSHI Register..................................................................................5-12

Table 5-20. CURSHI Fields......................................................................................5-12

Table 5-21. CURSLO Register.................................................................................5-12

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Table 5-22. CURSLO Fields.....................................................................................5-12

Table 5-23. CURDHI Register..................................................................................5-13

Table 5-24. CURDHI Fields......................................................................................5-13

Table 5-25. CURDLO Register.................................................................................5-13

Table 5-26. CURDLO Fields ....................................................................................5-13

Table 5-27. TCNT Register......................................................................................5-14

Table 5-28. TCNT Fields..........................................................................................5-14

Table 5-29. MASK Register......................................................................................5-15

Table 5-30. MASK Fields .........................................................................................5-15

Table 5-31. CLR Register.........................................................................................5-16

Table 5-32. CLR Fields ............................................................................................5-16

Table 5-33. STATUS Register..................................................................................5-17

Table 5-34. STATUS Fields .....................................................................................5-17

Chapter 6 – Ethernet MAC Controller

Table 6-1. Receive Buffer Descriptor LIst ..................................................................6-5

Table 6-2. Transmit Buffer Descriptor List..................................................................6-7

Table 6-3. Pause Frame Support.............................................................................6-10

Table 6-4. VLAN Support.........................................................................................6-13

Table 6-5. EMAC Register Summary.......................................................................6-18

Table 6-6. NETCTL Register ....................................................................................6-20

Table 6-7. NETCTL Fields........................................................................................6-20

Table 6-8. NETCONFIG Register.............................................................................6-22

Table 6-9. NETCONFIG Fields ................................................................................6-22

Table 6-10. NETSTATUS Register ..........................................................................6-24

Table 6-11. NETSTATUS Fields..............................................................................6-24

Table 6-12. TXSTATUS Register.............................................................................6-25

Table 6-13. TXSTATUS Fields.................................................................................6-25

Table 6-14. RXBQP Register...................................................................................6-27

Table 6-15. RXBQP Fields.......................................................................................6-27

Table 6-16. TXBQP Register....................................................................................6-28

Table 6-17. TXBQP Fields .......................................................................................6-28

Table 6-18. RXSTATUS Register.............................................................................6-29

Table 6-19. RXSTATUS Fields ................................................................................6-29

Table 6-20. INSTATUS Register..............................................................................6-30

Table 6-21. INSTATUS Fields..................................................................................6-30

Table 6-22. ENABLE Register..................................................................................6-32

Table 6-23. ENABLE Fields .....................................................................................6-32

Table 6-24. DISABLE Register.................................................................................6-33

Table 6-25. DISABLE Fields ....................................................................................6-33

Table 6-26. MASK Register......................................................................................6-34

Table 6-27. MASK Fields .........................................................................................6-34

Table 6-28. PHYMAINT Register.............................................................................6-35

Table 6-29. PHYMAINT Fields.................................................................................6-35

Table 6-30. PAUSETIME Register...........................................................................6-36

Table 6-31. PAUSETIME Fields...............................................................................6-36

Table 6-32. TXPAUSEQUAN Register.....................................................................6-36

Table 6-33. TXPAUSEQUAN Fields ........................................................................6-36

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Table 6-34. PAUSEFRRX Register..........................................................................6-37

Table 6-35. PAUSEFRRX Fields..............................................................................6-37

Table 6-36. FRMTXOK Register..............................................................................6-38

Table 6-37. FRMTXOK Fields..................................................................................6-38

Table 6-38. SINGLECOL Register...........................................................................6-38

Table 6-39. SINGLECOL Fields...............................................................................6-38

Table 6-40. MULTFRM Register..............................................................................6-39

Table 6-41. MULTFRM Fields..................................................................................6-39

Table 6-42. FRMRXOK Register..............................................................................6-39

Table 6-43. FRMRXOK Fields..................................................................................6-39

Table 6-44. FRCHK Register ...................................................................................6-40

Table 6-45. FRCHK Fields.......................................................................................6-40

Table 6-46. ALIGNERR Register .............................................................................6-40

Table 6-47. ALIGNERR Fields.................................................................................6-40

Table 6-48. DEFTXFRM Register............................................................................6-41

Table 6-49. DEFTXFRM Fields................................................................................6-41

Table 6-50. LATECOL Register ...............................................................................6-41

Table 6-51. LATECOL Fields...................................................................................6-41

Table 6-52. EXCOL Register....................................................................................6-42

Table 6-53. EXCCOL Fields.....................................................................................6-42

Table 6-54. TXUNDER Register ..............................................................................6-42

Table 6-55. TXUNDER Fields..................................................................................6-42

Table 6-56. SENSERR Register ..............................................................................6-43

Table 6-57. SENSERR Fields..................................................................................6-43

Table 6-58. RXRERR Register.................................................................................6-44

Table 6-59. RXRERR Fields ....................................................................................6-44

Table 6-60. RXOVERR Register..............................................................................6-44

Table 6-61. RXOVERR Fields..................................................................................6-44

Table 6-62. RXSYMERR Register ...........................................................................6-45

Table 6-63. RXSYMERR Fields...............................................................................6-45

Table 6-64. LENERR Register.................................................................................6-45

Table 6-65. LENERR Fields.....................................................................................6-45

Table 6-66. RXJAB Register....................................................................................6-46

Table 6-67. RXJAB Fields........................................................................................6-46

Table 6-68. UNDERFRM Register...........................................................................6-46

Table 6-69. UNDERFRM Fields...............................................................................6-46

Table 6-70. SQERR Register...................................................................................6-47

Table 6-71. SQERR Fields.......................................................................................6-47

Table 6-72. RXLEN Register....................................................................................6-47

Table 6-73. RXLEN Fields........................................................................................6-47

Table 6-74. TXPAUSEFM Register..........................................................................6-48

Table 6-75. TXPAUSEFM Fields..............................................................................6-48

Table 6-76. HASHBOT Register ..............................................................................6-49

Table 6-77. HASHBOT Fields..................................................................................6-49

Table 6-78. HASHTOP Register ..............................................................................6-49

Table 6-79. HASHTOP Fields..................................................................................6-49

Table 6-80. SPECAD1BOT Register........................................................................6-50

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Table 6-81. SPECAD1BOT Fields ...........................................................................6-50

Table 6-82. SPECAD1TOP Register........................................................................6-50

Table 6-83. SPECAD1TOP Fields ...........................................................................6-50

Table 6-84. SPECAD2BOT Register........................................................................6-51

Table 6-85. SPECAD2BOT Fields ...........................................................................6-51

Table 6-86. SPECAD2TOP Register........................................................................6-51

Table 6-87. SPECAD2TOP Fields ...........................................................................6-51

Table 6-88. SPECAD3BOT Register........................................................................6-52

Table 6-89. SPECAD3BOT Fields ...........................................................................6-52

Table 6-90. SPECAD3TOP Register........................................................................6-52

Table 6-91. SPECAD3TOP Fields ...........................................................................6-52

Table 6-92. SPECAD4BOT Register........................................................................6-53

Table 6-93. SPECAD4BOT Fields ...........................................................................6-53

Table 6-94. SPECAD4TOP Register........................................................................6-53

Table 6-95. SPECAD4TOP Fields ...........................................................................6-53

Table 6-96. IDCHK Register.....................................................................................6-54

Table 6-97. TypeIDCheck Fields..............................................................................6-54

Chapter 7 – External Memory Controller

Table 7-1. Static Memory Configurations.................................................................7-10

Table 7-2. Boot Configuration for Silicon Version A.0..............................................7-18

Table 7-3. Boot Configuration for Silicon Version A.1..............................................7-18

Table 7-4. 16-bit Address Mapping..........................................................................7-20

Table 7-5. 32-bit Wide Data Bus Address Mapping, SDRAM (RBC).......................7-22

Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC).......................7-23

Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC).......................7-25

Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC).......................7-26

Table 7-9. Memory System Examples .....................................................................7-27

Table 7-10. External Memory Controller Register Summary....................................7-28

Table 7-11. CONTROL Register..............................................................................7-30

Table 7-12. CONTROL Fields..................................................................................7-30

Table 7-13. STATUS Register..................................................................................7-31

Table 7-14. STATUS Fields .....................................................................................7-31

Table 7-15. CONFIG Register..................................................................................7-32

Table 7-16. CONFIG Fields......................................................................................7-32

Table 7-17. DYNMCTRL Register............................................................................7-33

Table 7-18. DYNMCTRL Fields................................................................................7-33

Table 7-19. DYNMREF Register..............................................................................7-34

Table 7-20. DYNMREF Fields..................................................................................7-34

Table 7-21. DYNMRCON Register...........................................................................7-35

Table 7-22. DYNMRCON Fields ..............................................................................7-35

Table 7-23. PRECHARGE Register.........................................................................7-36

Table 7-24. PRECHARGE Fields.............................................................................7-36

Table 7-25. DYNM2PRE Register............................................................................7-37

Table 7-26. DYNM2PRE Fields................................................................................7-37

Table 7-27. REFEXIT Register.................................................................................7-38

Table 7-28. REFEXIT Fields ....................................................................................7-38

Table 7-29. DOACTIVE Register .............................................................................7-39

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Table 7-30. DOACTIVE Fields.................................................................................7-39

Table 7-31. DIACTIVE Register...............................................................................7-40

Table 7-32. DIACTIVE Fields...................................................................................7-40

Table 7-33. DWRT Register.....................................................................................7-41

Table 7-34. DWRT Fields.........................................................................................7-41

Table 7-35. DYNACTCMD Register.........................................................................7-42

Table 7-36. DYNACTCMD Fields.............................................................................7-42

Table 7-37. DYNAUTO Register..............................................................................7-43

Table 7-38. DYNAUTO Fields..................................................................................7-43

Table 7-39. DYNREFEXIT Register.........................................................................7-44

Table 7-40. DYNREFEXIT Fields.............................................................................7-44

Table 7-41. DYNACTIVEAB Register ......................................................................7-45

Table 7-42. DYNACTIVEAB Fields..........................................................................7-45

Table 7-43. DYNAMICTMRD Register.....................................................................7-46

Table 7-44. DYNAMICTMRD Fields.........................................................................7-46

Table 7-45. WAIT Register.......................................................................................7-47

Table 7-46. WAIT Fields...........................................................................................7-47

Table 7-47. DYNCFGx Register...............................................................................7-48

Table 7-48. DYNCFGx Fields...................................................................................7-48

Table 7-49. Address Mapping..................................................................................7-49

Table 7-50. DYNRASCASx Register........................................................................7-51

Table 7-51. DYNRASCASx Fields ...........................................................................7-51

Table 7-52. SCONFIGx Register..............................................................................7-52

Table 7-53. SCONFIGx Fields .................................................................................7-52

Table 7-54. SWAITWENx Register..........................................................................7-54

Table 7-55. SWAITWENx Fields..............................................................................7-54

Table 7-56. SWAITOENx Register...........................................................................7-55

Table 7-57. SWAITOENx Fields...............................................................................7-55

Table 7-58. SWAITRDx Register .............................................................................7-56

Table 7-59. SWAITRDx Fields.................................................................................7-56

Table 7-60. SWAITPAGEx Register.........................................................................7-57

Table 7-61. SWAITPAGEx Fields ............................................................................7-57

Table 7-62. SWAITWRx Register.............................................................................7-58

Table 7-63. SWAITWRx Fields ................................................................................7-58

Table 7-64. STURNx Register..................................................................................7-59

Table 7-65. STURNx Fields .....................................................................................7-59

Chapter 8 – General Purpose Input/Output

Table 8-1. GPIO Ports................................................................................................8-1

Table 8-2. LH79524 GPIO Multiplexing......................................................................8-2

Table 8-3. LH79525 GPIO Multiplexing......................................................................8-5

Table 8-4. GPIO Port Memory Map............................................................................8-7

Table 8-5. P1DRx Register ........................................................................................8-8

Table 8-6. P1DRx Fields............................................................................................8-8

Table 8-7. P2DRx Register ........................................................................................8-9

Table 8-8. P2DRx Fields............................................................................................8-9

Table 8-9. P1DDRx Register....................................................................................8-10

Table 8-10. P1DDRx Fields......................................................................................8-10

Table 8-11. P2DDRx Register..................................................................................8-11

Table 8-12. P2DDRx Register Definitions................................................................8-11

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Chapter 9 – I2C Module

Table 9-1. I2C Clock Parameters ...............................................................................9-3

Table 9-2. Sample I
Table 9-3. I

2

C Register Summary..............................................................................9-6

Table 9-4. ICCON Register........................................................................................9-7

Table 9-5. ICCON Fields............................................................................................9-7

Table 9-6. ICSAR Register.........................................................................................9-8

Table 9-7. ICSAR Fields.............................................................................................9-8

Table 9-8. ICUSAR Register......................................................................................9-9

Table 9-9. ICUSAR Fields..........................................................................................9-9

Table 9-10. ICDATA Register.....................................................................................9-9

Table 9-11. ICDATA Fields ........................................................................................9-9

Table 9-12. ICHCNT Register..................................................................................9-10

Table 9-13. ICHCNT Fields......................................................................................9-10

Table 9-14. ICLCNT Register...................................................................................9-10

Table 9-15. ICLCNT Fields.......................................................................................9-10

Table 9-16. ICSTAT Register...................................................................................9-11

Table 9-17. ICSTAT Fields.......................................................................................9-11

2

C HIGH Period Counts..............................................................9-3

Chapter 10 – I2S Converter

Table 10-1. I2S Converter Register Summary........................................................10-13

Table 10-2. CTRL Register ....................................................................................10-14

Table 10-3. CTRL Register Definitions...................................................................10-14

Table 10-4. WSINV Functionality...........................................................................10-15

Table 10-5. STAT Register.....................................................................................10-16

Table 10-6. STAT Register Definitions...................................................................10-16

Table 10-7. IMSC Register.....................................................................................10-17

Table 10-8. IMSC Register Definitions...................................................................10-17

Table 10-9. RIS Register........................................................................................10-18

Table 10-10. RIS Register Definitions....................................................................10-18

Table 10-11. MIS Register .....................................................................................10-19

Table 10-12. MIS Register Definitions....................................................................10-19

Table 10-13. ICR Register......................................................................................10-20

Table 10-14. ICR Register Definitions....................................................................10-20

Chapter 11 – I/O Configuration

Table 11-1. IOCON Register Summary....................................................................11-2

Table 11-2. MUXCTL1 Register...............................................................................11-4

Table 11-3. MUXCTL1 Fields...................................................................................11-4

Table 11-4. RESCTL1 Register................................................................................11-5

Table 11-5. RESCTL1 Fields ...................................................................................11-5

Table 11-6. MUXCTL3 Register...............................................................................11-6

Table 11-7. MUXCTL3 Fields...................................................................................11-6

Table 11-8. RESCTL3 Register................................................................................11-6

Table 11-9. RESCTL3 Fields ...................................................................................11-6

Table 11-10. MUXCTL4 Register.............................................................................11-7

Table 11-11. MUXCTL4 Fields.................................................................................11-7

Table 11-12. RESCTL4 Register..............................................................................11-8

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Table 11-13. RESCTL4 Fields .................................................................................11-8

Table 11-14. MUXCTL5 Register.............................................................................11-9

Table 11-15. MUXCTL5 Fields.................................................................................11-9

Table 11-16. RESCTL5 Register............................................................................11-10

Table 11-17. RESCTL5 Fields ...............................................................................11-10

Table 11-18. MUXCTL6 Register...........................................................................11-12

Table 11-19. MUXCTL6 Fields...............................................................................11-12

Table 11-20. RESCTL6 Register............................................................................11-13

Table 11-21. RESCTL6 Fields ...............................................................................11-13

Table 11-22. MUXCTL7 Register...........................................................................11-14

Table 11-23. MUXCTL7 Fields...............................................................................11-14

Table 11-24. RESCTL7 Register............................................................................11-16

Table 11-25. RESCTL7 Fields ...............................................................................11-16

Table 11-26. MUXCTL10 Register.........................................................................11-18

Table 11-27. MUXCTL10 Fields.............................................................................11-18

Table 11-28. RESCTL10 Register..........................................................................11-20

Table 11-29. RESCTL10 Fields .............................................................................11-20

Table 11-30. MUXCTL11 Register.........................................................................11-22

Table 11-31. MUXCTL11 Fields.............................................................................11-22

Table 11-32. RESCTL11 Register..........................................................................11-24

Table 11-33. RESCTL11 Fields .............................................................................11-24

Table 11-34. MUXCTL12 Register.........................................................................11-26

Table 11-35. MUXCTL12 Fields.............................................................................11-26

Table 11-36. RESCTL12 Register..........................................................................11-27

Table 11-37. RESCTL12 Fields .............................................................................11-27

Table 11-38. RESCTL13 Register..........................................................................11-29

Table 11-39. RESCTL13 Fields .............................................................................11-29

Table 11-40. MUXCTL14 Register.........................................................................11-30

Table 11-41. MUXCTL14 Fields.............................................................................11-30

Table 11-42. MUXCTL15 Register.........................................................................11-32

Table 11-43. MUXCTL15 Fields.............................................................................11-32

Table 11-44. RESCTL15 Register..........................................................................11-32

Table 11-45. RESCTL15 Fields .............................................................................11-32

Table 11-46. RESCTL17 Register..........................................................................11-33

Table 11-47. RESCTL17 Fields .............................................................................11-33

Table 11-48. MUXCTL19 Register.........................................................................11-34

Table 11-49. MUXCTL19 Fields.............................................................................11-34

Table 11-50. RESCTL19 Register..........................................................................11-36

Table 11-51. RESCTL19 Fields .............................................................................11-36

Table 11-52. MUXCTL20 Register.........................................................................11-38

Table 11-53. MUXCTL20 Fields.............................................................................11-38

Table 11-54. RESCTL20 Register..........................................................................11-40

Table 11-55. RESCTL20 Fields .............................................................................11-40

Table 11-56. MUXCTL21 Register.........................................................................11-42

Table 11-57. MUXCTL21 Fields.............................................................................11-42

Table 11-58. RESCTL21 Register..........................................................................11-43

Table 11-59. RESCTL21 Fields .............................................................................11-43

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Table 11-60. MUXCTL22 Register.........................................................................11-44

Table 11-61. MUXCTL22 Fields.............................................................................11-44

Table 11-62. RESCTL22 Register..........................................................................11-46

Table 11-63. RESCTL22 Fields .............................................................................11-46

Table 11-64. MUXCTL23 Register.........................................................................11-48

Table 11-65. MUXCTL23 Fields.............................................................................11-48

Table 11-66. RESCTL23 Register..........................................................................11-50

Table 11-67. RESCTL23 Fields .............................................................................11-50

Table 11-68. MUXCTL24 Register.........................................................................11-52

Table 11-69. MUXCTL24 Fields.............................................................................11-52

Table 11-70. RESCTL24 Register..........................................................................11-53

Table 11-71. RESCTL24 Fields .............................................................................11-53

Table 11-72. MUXCTL25 Register.........................................................................11-54

Table 11-73. MUXCTL25 Fields.............................................................................11-54

Chapter 12 – Real Time Clock

Table 12-1. RTC Register Summary........................................................................12-3

Table 12-2. DR Register...........................................................................................12-3

Table 12-3. DR Fields ..............................................................................................12-3

Table 12-4. MR Register..........................................................................................12-4

Table 12-5. MR Fields..............................................................................................12-4

Table 12-6. LR Register...........................................................................................12-4

Table 12-7. LR Fields...............................................................................................12-4

Table 12-8. CR Register...........................................................................................12-5

Table 12-9. CR Fields ..............................................................................................12-5

Table 12-10. IMSC Register.....................................................................................12-5

Table 12-11. IMSC Fields.........................................................................................12-5

Table 12-12. RIS Register........................................................................................12-6

Table 12-13. RIS Fields............................................................................................12-6

Table 12-14. MIS Register .......................................................................................12-6

Table 12-15. MIS Fields...........................................................................................12-6

Table 12-16. ICR Register........................................................................................12-7

Table 12-17. ICR Fields ...........................................................................................12-7

Chapter 13 – Reset, Clock, and Power Controller

Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies........................13-5

Table 13-2. Clock and Enable States for Different Power Modes............................13-6

Table 13-3. RCPC Register Summary.....................................................................13-8

Table 13-4. CTRL Register ......................................................................................13-9

Table 13-5. CTRL Fields..........................................................................................13-9

Table 13-6. CHIPID Register..................................................................................13-10

Table 13-7. CHIPID Fields .....................................................................................13-10

Table 13-8. REMAP Register.................................................................................13-11

Table 13-9. REMAP Fields.....................................................................................13-11

Table 13-10. SOFTRESET Register......................................................................13-14

Table 13-11. SOFTRESET Fields..........................................................................13-14

Table 13-12. RSTSTATUS Register ......................................................................13-15

Table 13-13. RSTSTATUS Fields..........................................................................13-15

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Table 13-14. RSTSTATUSCLR Register...............................................................13-16

Table 13-15. RSTSTATUSCLR Fields...................................................................13-16

Table 13-16. SYSCLKPRE Register......................................................................13-17

Table 13-17. SYSCLKPRE Fields..........................................................................13-17

Table 13-18. SYSCLKPRE Register Values..........................................................13-17

Table 13-19. CPUCLKPRE Register......................................................................13-18

Table 13-20. CPUCLKPRE Fields..........................................................................13-18

Table 13-21. CPUCLKPRE Register Values..........................................................13-18

Table 13-22. PCLKCTRL0 Register.......................................................................13-19

Table 13-23. PCLKCTRL0 Fields...........................................................................13-19

Table 13-24. PCLKCTRL1 Register.......................................................................13-20

Table 13-25. PCLKCTRL1 Fields...........................................................................13-20

Table 13-26. AHBCLKCTRL Register....................................................................13-21

Table 13-27. AHBCLKCTRL Fields........................................................................13-21

Table 13-28. PCLKSEL0 Register..........................................................................13-22

Table 13-29. PCLKSEL0 Fields .............................................................................13-22

Table 13-30. PCLKSEL1 Register..........................................................................13-23

Table 13-31. PCLKSEL1 Fields .............................................................................13-23

Table 13-32. SILICONREV Register......................................................................13-24

Table 13-33. SILICONREV Fields..........................................................................13-24

Table 13-34. LCDPRE Register.............................................................................13-25

Table 13-35. LCDPRE Fields.................................................................................13-25

Table 13-36. LCDPRE Register Values.................................................................13-25

Table 13-37. SSPPRE Register.............................................................................13-26

Table 13-38. SSPPRE Fields.................................................................................13-26

Table 13-39. SSPPRE Register Values.................................................................13-26

Table 13-40. ADCPRE Register.............................................................................13-27

Table 13-41. ADCPRE Fields.................................................................................13-27

Table 13-42. ADCPRE Register Values.................................................................13-27

Table 13-43. USBPRE Register.............................................................................13-28

Table 13-44. USBPRE Fields.................................................................................13-28

Table 13-45. USBPRE Register Values.................................................................13-28

Table 13-46. INTCONFIG Register........................................................................13-29

Table 13-47. INTCONFIG Fields............................................................................13-29

Table 13-48. INTCLR Register...............................................................................13-31

Table 13-49. INTCLR Fields...................................................................................13-31

Table 13-50. CORECONFIG Register ...................................................................13-32

Table 13-51. CORECONFIG Fields.......................................................................13-32

Table 13-52. SYSPLLCTL Register .......................................................................13-33

Table 13-53. SYSPLLCTL Fields...........................................................................13-33

Table 13-54. USBPLLCTL Register.......................................................................13-34

Table 13-55. USBPLLCTL Fields...........................................................................13-34

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List of Tables LH79524/LH79252 User’s Guide

Chapter 14 – Synchronous Serial Port

Table 14-1. Feature Comparison .............................................................................14-2

Table 14-2. SSP Register Summary........................................................................14-9

Table 14-3. CTRL0 Register ..................................................................................14-10

Table 14-4. CTRL0 Fields......................................................................................14-10

Table 14-5. CTRL1 Register ..................................................................................14-12

Table 14-6. CTRL1 Fields......................................................................................14-12

Table 14-7. DR Register.........................................................................................14-13

Table 14-8. DR Fields ............................................................................................14-13

Table 14-9. SR Register.........................................................................................14-14

Table 14-10. SR Fields...........................................................................................14-14

Table 14-11. CPSR Register..................................................................................14-15

Table 14-12. CPSR Fields......................................................................................14-15

Table 14-13. IMSC Register...................................................................................14-16

Table 14-14. IMSC Fields.......................................................................................14-16

Table 14-15. RIS Register......................................................................................14-17

Table 14-16. RIS Fields..........................................................................................14-17

Table 14-17. MIS Register .....................................................................................14-18

Table 14-18. MIS Fields.........................................................................................14-18

Table 14-19. ICR Register......................................................................................14-19

Table 14-20. ICR Fields .........................................................................................14-19

Table 14-21. DCR Register....................................................................................14-20

Table 14-22. DCR Fields........................................................................................14-20

Chapter 15 – Timers

Table 15-1. Timer 0 Register Summary...................................................................15-6

Table 15-2. Timer 1 Register Summary...................................................................15-6

Table 15-3. Timer 2 Register Summary...................................................................15-6

Table 15-4. CTRL0 Register ....................................................................................15-7

Table 15-5. CTRL0 Register Definitions...................................................................15-7

Table 15-6. CMP_CAP_CTRL0 Register.................................................................15-8

Table 15-7. CMP_CAP_CTRL0 Register Definitions...............................................15-8

Table 15-8. INTEN0 Register.................................................................................15-10

Table 15-9. INTEN0 Register Definitions...............................................................15-10

Table 15-10. STATUS0 Register............................................................................15-11

Table 15-11. STATUS0 Register Definitions..........................................................15-11

Table 15-12. CNT0 Register ..................................................................................15-12

Table 15-13. CNT0 Register Definitions.................................................................15-12

Table 15-14. T0CMPn Registers............................................................................15-13

Table 15-15. T0CMPn Register Definitions............................................................15-13

Table 15-16. CAPn Register ..................................................................................15-14

Table 15-17. CAPn Register Definitions.................................................................15-14

Table 15-18. CTRL1 Register ................................................................................15-15

Table 15-19. CTRL1 Register Definitions...............................................................15-15

Table 15-20. INTEN1 Register...............................................................................15-17

Table 15-21. INTEN1 Register Definitions.............................................................15-17

Table 15-22. STATUS1 Register............................................................................15-18

Table 15-23. STATUS1 Register Definitions..........................................................15-18

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Table 15-24. CNT1 Register ..................................................................................15-19

Table 15-25. CNT1 Register Definitions.................................................................15-19

Table 15-26. T1CMPn Registers............................................................................15-20

Table 15-27. T1CMPn Register Definitions............................................................15-20

Table 15-28. T1CAPn Register..............................................................................15-21

Table 15-29. T1CAPn Register Definitions ............................................................15-21

Table 15-30. CTRL2 Register ................................................................................15-22

Table 15-31. CTRL2 Register Definitions...............................................................15-22

Table 15-32. INTEN2 Register...............................................................................15-24

Table 15-33. INTEN2 Register Definitions.............................................................15-24

Table 15-34. STATUS2 Register............................................................................15-25

Table 15-35. STATUS2 Register Definitions..........................................................15-25

Table 15-36. CNT2 Register ..................................................................................15-26

Table 15-37. CNT2 Register Definitions.................................................................15-26

Table 15-38. T2CMPn Registers............................................................................15-27

Table 15-39. T2CMPn Register Definitions............................................................15-27

Table 15-40. T2CAPn Register..............................................................................15-28

Table 15-41. T2CAPn Register Definitions ............................................................15-28

Chapter 16 – UARTs

Table 16-1. Control bits to enable and disable hardware flow control......................16-6

Table 16-2. UART Register Summary......................................................................16-7

Table 16-3. UARTDR Register.................................................................................16-8

Table 16-4. UARTDR Fields.....................................................................................16-8

Table 16-6. UARTRSR/UARTECR Register (Write Operations)..............................16-9

Table 16-7. UARTRSR/UARTECR Fields (Write Operations) .................................16-9

Table 16-5. Nine-bit Mode/Parity Bit Table..............................................................16-9

Table 16-8. UARTRSR/UARTECR Register (Read Operations) ...........................16-10

Table 16-9. UARTRSR/UARTECR Fields (Read Operations)...............................16-10

Table 16-10. UARTFR Register.............................................................................16-11

Table 16-11. UARTFR Fields.................................................................................16-11

Table 16-12. UARTILPR Register..........................................................................16-12

Table 16-13. UARTILPR Fields..............................................................................16-12

Table 16-14. UARTIBRD Register .........................................................................16-13

Table 16-15. UARTIBRD Fields.............................................................................16-13

Table 16-16. UARTFBRD Register........................................................................16-14

Table 16-17. UARTFBRD Fields............................................................................16-14

Table 16-18. Bit Rates and Their Corresponding Divisors.....................................16-14

Table 16-19. UARTLCR_H Register......................................................................16-15

Table 16-20. UARTLCR_H Fields..........................................................................16-15

Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits.................................16-16

Table 16-22. UARTCR Register.............................................................................16-17

Table 16-23. UARTCR Fields.................................................................................16-17

Table 16-24. UARTIFLS Register ..........................................................................16-19

Table 16-25. UARTIFLS Fields..............................................................................16-19

Table 16-26. UARTIMSC Register.........................................................................16-20

Table 16-27. UARTIMSC Fields.............................................................................16-20

Table 16-28. UARTRIS Register............................................................................16-22

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List of Tables LH79524/LH79252 User’s Guide

Table 16-29. UARTRIS Fields................................................................................16-22

Table 16-30. UARTMIS Register............................................................................16-24

Table 16-31. UARTMIS Fields ...............................................................................16-24

Table 16-32. UARTICR Register............................................................................16-26

Table 16-33. UARTICR Fields................................................................................16-26

Table 16-34. DMACTRL Register ..........................................................................16-27

Table 16-35. DMACTRL Fields..............................................................................16-27

Chapter 17 – Universal Serial Bus Device

Table 17-1. Endpoint Function.................................................................................17-2

Table 17-2. Endpoint FIFO Characteristics..............................................................17-3

Table 17-3. USB Register Summary........................................................................17-8

Table 17-4. FAR Register.......................................................................................17-10

Table 17-5. FAR Fields ..........................................................................................17-10

Table 17-6. PMR Register......................................................................................17-11

Table 17-7. PMR Fields..........................................................................................17-11

Table 17-8. IIR Register.........................................................................................17-12

Table 17-9. IIR Fields.............................................................................................17-12

Table 17-10. OIR Register .....................................................................................17-13

Table 17-11. OIR Fields.........................................................................................17-13

Table 17-12. UIR Register......................................................................................17-14

Table 17-13. UIR Fields .........................................................................................17-14

Table 17-14. IIE Register .......................................................................................17-15

Table 17-15. IIE Fields...........................................................................................17-15

Table 17-16. OIE Register......................................................................................17-16

Table 17-17. OIE Fields .........................................................................................17-16

Table 17-18. UIE Register......................................................................................17-17

Table 17-19. UIE Fields..........................................................................................17-17

Table 17-20. FRAME1 Register.............................................................................17-18

Table 17-21. FRAME2 Register.............................................................................17-18

Table 17-22. FRAME1 Fields.................................................................................17-18

Table 17-23. FRAME2 Fields.................................................................................17-18

Table 17-24. INDEX Register.................................................................................17-19

Table 17-25. INDEX Fields.....................................................................................17-19

Table 17-26. INMAXP Register..............................................................................17-20

Table 17-27. INMAXP Fields..................................................................................17-20

Table 17-28. CSR0 Register..................................................................................17-21

Table 17-29. CSR0 Fields......................................................................................17-21

Table 17-30. INCSR1 Register...............................................................................17-23

Table 17-31. INCSR1 Fields ..................................................................................17-23

Table 17-32. INCSR2 Register...............................................................................17-25

Table 17-33. INCSR2 Fields ..................................................................................17-25

Table 17-34. OUTMAXP Register..........................................................................17-26

Table 17-35. OUTMAXP Fields..............................................................................17-26

Table 17-36. OUTCSR1 Register...........................................................................17-27

Table 17-37. OUTCSR1 Fields ..............................................................................17-27

Table 17-38. OUTCSR2 Register...........................................................................17-29

Table 17-39. OUTCSR2 Fields ..............................................................................17-29

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Table 17-40. OUTCOUNT0 Register .....................................................................17-30

Table 17-41. OUTCOUNT0 Fields.........................................................................17-30

Table 17-42. OUTCOUNT1 Register .....................................................................17-30

Table 17-43. OUTCOUNT1 Fields.........................................................................17-30

Table 17-44. OUTCOUNT2 Register .....................................................................17-31

Table 17-45. OUTCOUNT2 Fields.........................................................................17-31

Table 17-46. FIFO Register....................................................................................17-31

Table 17-47. COUNT1 Fields.................................................................................17-31

Table 17-48. INTR Register ...................................................................................17-32

Table 17-49. INTR Fields.......................................................................................17-32

Table 17-50. CNTLx Register.................................................................................17-33

Table 17-51. CNTLx Fields ....................................................................................17-33

Table 17-52. ADDRx Register................................................................................17-34

Table 17-53. ADDRx Fields....................................................................................17-34

Table 17-54. COUNTx Register.............................................................................17-34

Table 17-55. COUNTx Fields.................................................................................17-34

Chapter 18 – Vectored Interrupt Controller

Table 18-1. Interrupt Assignments...........................................................................18-2

Table 18-2. VIC Register Summary .........................................................................18-5

Table 18-3. IRQSTATUS Register...........................................................................18-6

Table 18-4. IRQSTATUS Fields...............................................................................18-6

Table 18-5. FIQSTATUS Register............................................................................18-7

Table 18-6. FIQSTATUS Fields ...............................................................................18-7

Table 18-7. RAWINTR Register...............................................................................18-7

Table 18-8. RAWINTR Fields...................................................................................18-7

Table 18-9. INTSELECT Register............................................................................18-8

Table 18-10. INTSELECT Fields..............................................................................18-8

Table 18-11. INTENABLE Register..........................................................................18-8

Table 18-12. INTENABLE Fields..............................................................................18-8

Table 18-13. INTENCLEAR Register.......................................................................18-9

Table 18-14. INTENCLEAR Fields...........................................................................18-9

Table 18-15. SOFTINT Register ............................................................................18-10

Table 18-16. SOFTINT Fields................................................................................18-10

Table 18-17. SOFTINTCLEAR Register ................................................................18-11

Table 18-18. SOFTINTCLEAR FIelds....................................................................18-11

Table 18-19. VECTADDR Register........................................................................18-12

Table 18-20. VECTADDR Fields............................................................................18-12

Table 18-21. DEFVECTADDR Register.................................................................18-12

Table 18-22. DEFVECTADDR Fields.....................................................................18-12

Table 18-23. VECTADDRx Registers ....................................................................18-13

Table 18-24. VECTADDRx Fields..........................................................................18-13

Table 18-25. VECTCTRLx Registers.....................................................................18-14

Table 18-26. VECTCTRLx Fields...........................................................................18-14

Table 18-27. ITOP Register ...................................................................................18-15

Table 18-28. ITOP Fields.......................................................................................18-15

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List of Tables LH79524/LH79252 User’s Guide

Chapter 19 – Watchdog Timer

Table 19-1. Watchdog Timer Memory Map..............................................................19-4

Table 19-2. CTL Register.........................................................................................19-5

Table 19-3. CTL Fields.............................................................................................19-5

Table 19-4. RST Description....................................................................................19-6

Table 19-5. RST Field..............................................................................................19-6

Table 19-6. STATUS Description.............................................................................19-7

Table 19-7. STATUS Fields .....................................................................................19-7

Table 19-8. COUNTx Description.............................................................................19-8

Table 19-9. COUNTx Fields.....................................................................................19-8

xxxiv Version 1.0

Preface

The LH79524 and LH79525 are fully-integrated 16/32-bit SoCs based on a 32-bit
ARM720T core. This User’s Guide is the principal technical reference for these devices.
This document assumes the reader is familiar with ARM720T programming. For more
information on programming the ARM720T core, see the library of methods and down­loads available from ARM Ltd., at http://www.arm.com.

For an abridged version of this User’s Guide, consult the LH79524/LH79525 Data Sheet
and the single page Product Brief. For details, contact a SHARP representative or see the
SHARP Microelectronics of the Americas website (http://www.sharpsma.com).

Application Notes and further information on connecting, programming and implementing
the LH79524/LH79525, along with suggestions for companion parts, can be found on
SHARP's website (http://www.sharpsma.com).

IMPORTANT: The following sections contain important design information about the LH79524/LH79525.

Please take a moment to read the ‘Conventions and Terms’ section in its entirety.

Conventions and Terms

For information on specific terms and acronyms see the Glossary in this User’s Guide.

Unconnected (Floating) Inputs

Many applications employing the LH79524/LH79525 require extremely low standby and
operating current consumption, especially in battery operated devices. To achieve mini­mum current, unused inputs must never be left floating (unconnected). Each input must be
pulled up or pulled down with a 33 kΩ resistor (or smaller). In addition to terminating input
pins, this also allows the designer to specify the reset state of input pins by selecting pull
up (logical 1 at reset) or pull down (logical 0 at reset) resistors.

Multiplexed Pins

The LH79524 is manufactured in a CABGA package with 208 pins. The LH79525 is man­ufactured in a LQFP package with 176 pins. Some pins have only one function, b ut others
are multiplexed and may carry as many as three functions. Designers must be aware that
multiplexed pins cannot simultaneously support more than one function; a choice is
required prior to designing the SoC into an application.

Version 1.0 xxxv

Preface LH79524/LH79525 User’s Guide

Pin Names

Package pins are named to indicate the signal(s) or functionality available at the pin.
If the signal or function is active LOW, the name is prefixed with a lower-case ‘n’,
such as nSCS2. Multiplexed pins are named to indicate all available functions, such
as Pin D11 (Pin 139 for the LH79525): PE1/LCDDCLK, which can function as either GPIO
Port E bit 1, or LCD Data Clock.

These naming conventions help designers recognize and avoid conflicts between multi­plexed functions but can complicate explanatory text, so this User’s Guide uses the name
appropriate to the context. A discussion about Port E bit 1 would use PE1, for example,
but information about LCD data would refer to signal LCDVD5. Readers must be aware
that these are separate signals, with distinctly different functionality, which happen to be
available on the same pin, although never simultaneously.

Peripheral Devices

The LH79524/LH79525 is an SoC built using the ARM720T RISC core as a base. Objects
within the chip but external to the core processor and its support devices are referred to
throughout this User’s Guide as ‘blocks’ or ‘Peripheral Devices’.

The LH79524/LH79525 includes two buses: an Advanced High-Performance Bus (AHB)
and an Advanced Peripheral Bus (APB). The devices shown on the APB in the block dia­grams are an example of Peripheral Devices in this document. Devices that are external
to the chip are referred to as ‘External Devices’.

Register Addresses

The LH79524/LH79525 is a memory-mapped device with programmable, internal regis­ters that control its operation. Each internal register is located at a unique address in the
memory map and the registers are generally grouped in the map by subsystem.

In this User’s Guide, the addresses for all registers are expressed as a base address and
an offset from that base. The base address indicates where in the map a group of registers
begins and the offset locates a particular register, relative to its base address. Thus, any
register’s absolute address is the sum of its base address and its offset. Programmers will
find this base+offset representation convenient for creating software structures to access
the registers. The absolute addresses are also provided for convenient reference.

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LH79524/LH79525 User’s Guide Preface

Register Tables

All Registers are presented in tabular format. A primary table presents each register’s
name, address, permissions, bit-field names and the register’s contents at reset. Subse­quent tables detail the specific names and function(s) of all bit fields in the register and
explain any important variations that may exist.

An important detail to note is that all registers are not perfectly writable and readable.
Some will exhibit different characteristics on a write, while a read may not return the
expected result. At the same time, there will be registers whose function on a write is to
clear a value or a set of stored values, while on a read will return a specific set of values.
This is particularly true in registers that handle interrupts. Writing to a specific register may
clear a set of interrupts, while reading that same register will yield which interrupts are set.

Similarly, not all bit fields in all registers can be written, nor can all register bit fields yield
useful information when read. These restricted register bit fields will be specifically called
out with three slashes (///) and the word ‘Reserved’, along with their special conditions in
the bit field tables. See Table 1 and Table 2 for examples of this practice.

Table 1. Register Name

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD /// F25 ///
RESET 0000000000000000
TYPE RO RO RO RO RO RO RW RO RO RO RO RO RO RO RO RO
ADDR —
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// F07F06F05F04F03F02F01F00
RESET 0000000000000000
TYPE RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW
ADDR REGISTERBASE + 0x0004

Table 2. Bit Fields

BITS FIELD NAME FUNCTION

31:26 /// Reserved Reading returns 0. Values written cannot be read.

25 F25 Field 25 A description of this bit’s functionality will be found in this space.

24:8 /// Reserved Reading returns 0. Writing to this field will have no effect.

7:0 F7:F0

NOTES:

RO = Read Only
WO = Write Only
RW = Read and Write

Field Bits [7:0] A description of these bits’ functionality will be found in
this space.

Version 1.0 xxxvii

Preface LH79524/LH79525 User’s Guide

Numeric Values

Binary values are prefixed with 0b; for example, 0b00001000.
Hexadecimal values are expressed with UPPERCASE letters and prefixed with 0x; for

example, 0x0FBC.
All numeric values not specifically identified with the above prefixes as either binary or

hexadecimal are decimal values.
Registers and bit fields with 0b0 in all bits are referred to as cleared or as 0. Registers and

bit fields with 0b1 values in all bits are referred to as set or as the binary, hexadecimal, or
decimal value of the entire field or register. When truth tables are used, the ‘0b’ prefix is
omitted for textual clarity.

Block Diagrams

The functional descriptions in this User’s Guide include block diagrams with symbols rep­resenting logical or mathematical operations or selections, usually the result of writing a
value to a register. Figure 1 shows one such multiplexer with three inputs and one output
(the result).

CONTROL SIGNAL or

REGISTER:BITFIELD

INPUT

INPUT

INPUT

FUNCTION

Figure 1. Multiplexer

OUTPUT

7A404-91

xxxviii Version 1.0

LH79524/LH79525 User’s Guide Preface

2

Block diagrams can include symbols representing Registers and the bit fields within them.
Figure 2 shows that the BITFIELDNAME bit field in the REGISTERNAME register enables
or disables the signal named OUTPUT.

REGISTERNAME:BITFIELDNAME

INPUT

f ( )

OUTPUT

LH7A404-9

Figure 2. Register with Bit-Field Named

Figure 3 is similar to Figure 2 except that Figure 3 references multiple (different)
BITFIELDS in the REGISTERNAME register.

REGISTERNAME: 15:3

f ( )

OUTPUTINPUT

LH7A404-93

Figure 3. Register with Multiple Bit-Fields Named

Not all bit fields are named. If a bit field has no name, the Register is shown with numbers
indicating the appropriate bit positions, with the least significant bit on the right, as in
Figure 4. This bit ordering matches that of the Register tables, shown in Table 1.

REGISTERNAME: [BITFIELDNAME, BITFIELDNAME]

f ( )

OUTPUTINPUT

Figure 4. Register with Bit-Field Numbered

Version 1.0 xxxix

7A404-94

Preface LH79524/LH79525 User’s Guide

What’s in This User’s Guide

Chapter 1 – Overview

This Chapter lists the features of the LH79524/LH79525 SoC and presents a simplified
block diagram of the device, with the major architectural features identified. Also presented
is an overview of the ARM720T processor and MMU. The theory of operation covers bus
architecture, bus arbitration, and the base addresses for each of the Advanced High-Per­formance Bus (AHB) and Advanced Peripheral Bus (APB) devices and the APB Bridge.
Coverage of the memory system includes memory mapping, memory remapping, and the
External Bus Interface (EBI). This Chapter provides programmer’s models, programmable
parameters, default memory widths, address mapping, and includes a register summary
and register descriptions.

Chapter 2 – ADC and Brownout Detector

This Chapter describes the 10-channel, 10-bit Analog to Digital Converter, and its associ­ated Brownout Detector. Theory of operation includes both touch-screen application s and
traditional ADC applications. This Chapter provides programmer’s mod els, programmable
parameters, default memory widths, address mapping, and includes a register summary
and register descriptions.

Chapter 3 – Boot Controller

This Chapter describes alternate booting options, their use and configuration. Also
included is a programmer’s model, address mapping, and a register summary and register
descriptions.

Chapter 4 – Color LCD Controller

This Chapter describes the Color LCD Controller (CLCDC) and the Advanced LCD Inter­face Controller (ALI) functional blocks within the LH79524/LH79525. The Chapter includes
a brief overview, lists the types of panels supported, and at what bit-depths. The Chapter
also lists and explains the programmable parameters and includes a register summary.
Register descriptions, with reset values, and horizontal timing restrictions are provided.

Chapter 5 – DMA Controller

This Chapter describes the DMA operations available in the LH79524/LH79525 SoC,
latencies from one process to another, and the interrupts involved. Also included is a pro­grammer’s model, address mapping, and a register summary and register descriptions.

Chapter 6 – Ethernet MAC

Included in this chapter is a description and programming information for the SoC’s Ether­net MAC. Also included is a programmer’s model, address mapping, and a register sum­mary and register descriptions.

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LH79524/LH79525 User’s Guide Preface

Chapter 7 – External Memory Controller

This Chapter presents the theory of operation of the LH79524/LH79525 External Memory
Controller (EMC), including programmable parameters, device selection , memory widths,
and address mapping. This Chapter includes a register summary and register descriptions
for the EMC.

Chapter 8 – General Purpose Input/Output

This Chapter presents the LH79524/LH79525 General Purpose Input/Output (GPIO) sys­tems, beginning with a brief overview, and including a block diagram, programmer’s
model, register summary, and register descriptions.

Chapter 9 – I2C Interface

The I2C Interface is described in this chapter. The Chapter includes a short overview, a
block diagram, programmer’s model, interrupt channel list, register summaries, and regis­ter descriptions.

Chapter 10 – I2S Converter

This Chapter describes the I2S Converter. This peripheral converts a synchronous serial com-

munication stream in Texas Instruments DSP-compatible mode to an I
serial stream. The I

ter includes a short overview, a block diagram, programmer’s model, interrupt channel list,
register summaries, and register descriptions.

2

S converter operates on serial data in both master and slave mode. The Chap-

2

S-compliant synchronous

Chapter 11 – I/O Configuration

This Chapter is an overview of the LH79524/LH79525 I/O Configuration and pin multiplex­ing. The Chapter provides a block diagram, programmer’s model, register summary and
descriptions.

Chapter 12 – Real Time Clock

This Chapter describes the LH79524/LH79525 Real Time Clock (RTC). The Chapter
includes a short overview, a block diagram, a list of clock signals, programmer’s model, sig­nal descriptions, operating sequences, register summaries, register descriptions and inter­face signals.

Chapter 13 – Reset, Clock Generation and Power Control

This chapter provides a short overview of the LH79520 Reset, Clock Generation and
Power Control (RCPC) system, including a block diagram, a list of clock signals, power
control modes, programmer’s model, signal descriptions, power sequences, register sum­maries, register descriptions, and descriptions of interface signals.

Chapter 14 – Synchronous Serial Port

This Chapter presents an overview of the LH79524/LH79525 Synchronous Serial Port, a
block diagram, programmer’s model, register summary, register descriptions, Interrupts,
and register locations.

Version 1.0 xli

Preface LH79524/LH79525 User’s Guide

Chapter 15 – Timers

This Chapter describes the LH79524/LH79525 Timers. The Chapter includes a short over­view and block diagram, signal descriptions, operation sequences, register summaries,
register descriptions, and interface signals.

Chapter 16 – UARTs

This Chapter presents the LH79524/LH79525 UART blocks. The Cha pter includes a brief
overview, block diagram, programmer’s model, programmable parameters, register sum­mary and register descriptions.

Chapter 17 – USB Device

This Chapter presents the LH79524/LH79525 USB Device, beginning with a brief overview,
and including a block diagram, programmer’s model, register summary, and register
descriptions.

Chapter 18 – Vectored Interrupt Controller

This Chapter describes the LH79524/LH79525 Vectored Interrupt Controller. The Chapter
includes a short overview, a block diagram, programmer’s model, interrupt channel list,
register summaries, and register descriptions.

Chapter 19 – Watchdog Timer

This Chapter describes the LH79524/LH79525 Watchdog Timer (WDT). The Chapter
includes a short overview, block diagram, programmer’s model, signal descriptions, oper­ating sequences, register summaries and register descriptions.

Appendix – Glossary

This Chapter contains an alphabetical listing of common terminology appearing in this
User’s Guide.

xlii Version 1.0

Chapter 1

Overview

The LH79524 and LH79525 are fully-integrated 16/32-bit Systems-on-Chip (SoCs) based
on a 32-bit ARM720T core. The 32-bit ARM720T RISC core provides a powerful instruc­tion set and includes Cache RAM, a Write Buffer, Memory-Management Unit (MMU), and
Translation Lookaside Buffer (TLB). Both SoCs include a Color LCD Controller, a Direct
Memory Access Controller, Vectored Interrupt Controller, 16KB of internal Static RAM
(SRAM), and several supporting peripherals. The External Memory Controller (EMC),
provides a glueless interface to external memory.

Supporting function blocks within the LH79524/LH79525 include Serial and Parallel Inter­faces, Counters/Timers, Real Time Clock, Watchdog Timer, Pulse Width Modulators, and
an on-chip Phase-Locked Loop. JTAG support is provided to simplify debugging.

Table 1-1 summarizes the differences in features between the LH79524 and the LH79525 .
All other peripherals and functional blocks are identical (unless noted in the Chapter detail­ing that block’s function). The block diagram for both devices appears in Figure 1-1. Refer
to it when reading sections detailing bus architecture and functional block descriptions.

Table 1-1. LH79524/LH79525 Differences

FEATURE LH79524 LH79525

Package 208 CABGA 176 LQFP
Data Bus Width
Color LCD Controller

(CLCDC)
General Purpose

Input/Output (GPIO)

32-Bit Data Bus that includes
all peripherals

16-bit CLCDC Data 12-bit CLCDC Data
92 GPIO, 8 General Purpose Input onl y (GPI),

8 General Purpose Output only (GPO)

16-bit Data Bus that
includes all peripherals

72 GPIO, 8 GPI, 6 GPO

Version 1.0 1-1

Overview LH79524/LH79525 User’s Guide

ARM720T

CACHE

INTERNAL

INTERRUPTS

INTERNAL

16KB SRAM

BOOT

ROM

EXTERNAL

MEMORY

CONTROLLER

10 - 20 MHz 32.768 kHz

OSCILLATOR,

PLL(2), POWER

MANAGEMENT, and

RESET CONTROL

CONDITIONED
EXTERNAL
INTERRUPTS

VECTORED
INTERRUPT

CONTROLLER

ETHERNET

MAC

BOOT

CONTROLLER

4 CHANNEL

DMA

CONTROLLER

LH79524/LH79525

REAL TIME

CLOCK

GENERAL

PURPOSE I/O

I/O

CONFIGURATION

SYNCHRONOUS

SERIAL PORT

SSP - I2S

CONVERTER

(WITH CODEC

INTERFACE)

COUNTER/

TIMER (3)

WATCHDOG

TIMER

USB

DEVICE

TEST

SUPPORT

LINEAR

REGULATOR

ADVANCED HIGH

PERFORMANCE

ADVANCED
PERIPHERAL
BUS BRIDGE

BUS (AHB)

COLOR

LCD

CONTROLLER

ADVANCED

LCD

INTERFACE

ADVANCED

PERPHERAL

BUS (APB)

UART (3) w/SIR

(WITH TSC and

Figure 1-1. LH79524/LH79525 Block Diagram

2

I

C

16550

10 CHANNEL

10-BIT ADC

BROWNOUT
DETECTOR)

LH79525-1

1-2 Version 1.0

LH79524/LH79525 User’s Guide Overview

1.1 Bus Architecture

The LH79524 and LH79525 both internally employ the ARM Advanced Microprocessor
Bus Architecture (AMBA) 2.0 bus and bus protocol. They have four Bus Masters on the
Advanced High-performance Bus (AHB) that control access to the external memory and
the on-chip peripherals. The AHB Bus Masters are:

• The ARM720T core processor

• Direct Memory Access Controller (DMAC) for transfers between memory and an exter­nal peripheral, or memory.

• Ethernet MAC Controller (EMAC)

• Color LCD Controller (CLDCC).

Except in test mode, the ARM720T processor is the default bus master.
An Advanced Peripheral Bus (APB) bridge is provided to access the various APB periph-

erals. Generally, APB peripherals are serviced by the ARM core, however, if they are DMA
enabled, they would also be serviced by the DMA controller to increase system perfor­mance while the ARM core is running from cache.

1.2 Power Supply

The SoC’s core logic requires a 1.8 V supply. Digital Input/Output pins are 5 V tolerant
and require a 3.3 V supply. They are designed to operate from a single 3.3 V supply. An
on-chip 1.8 V-to-3.3 V linear regulator can be used to generate the 1.8 V needed by
the core logic.

1.2.1 Linear Regulator

When the linear regulator is enabled, the 1.8 V power pins (VDDC) are outputs of the
regulator. This allows regulator operation verification. In addition, an external low-ESR
capacitor must be tied to the regulator output for stability. If the regulator is disabled, the

1.8 V power pins are used as inputs from an external 1.8 V supply.

The linear regulator is enabled by tying the LINREGEN pin to 3.3 V; it is disabled by
holding the LINREGEN pin LOW. Proper power-up sequencing must be considered when
employing the linear regulator. In order to ensure this takes place, nRESETIN must be held
LOW until the linear regulator has ramped up to nominal operating voltage.

The linear regulator must only be used to power the SoC and internal devices; it is not
intended to supply power to off-chip peripherals. Powering external devices can result in
unpredictable behavior or device failure.

1.2.2 Phase Locked Loop Power

Two PLLs provide accurate, on-board clocks (see Section 1.3). The PLLs require a 1.8 V
supply. If the linear regulator is disabled, the supply must come from an external source.
If the linear regulator is enabled, the PLL power supply comes from the internal VDDC
power pins.

Version 1.0 1-3

Overview LH79524/LH79525 User’s Guide

1.3 Clock Strategy

The SoCs have two crystal oscillators. One oscillator, CLK OSC, is used to drive both PLLs
and the three UARTs, among others. This oscillator supports a frequency range from 10
to 20 MHz. The second oscillator, RTC CLK, is a 32.768 kHz oscillator, also requiring a

1.8 V source. This oscillator is used to generate a 1 Hz clock for the Real-time Clock.

The clock circuitry has two PLLs — one for the system clock generation and the other
for the USB clock generation. The output frequency of the PLLs ranges from 20 MHz to

304.819 MHz based on the PLL programmable dividers’ values.

The system clock frequency created in the Reset, Clock, and Power Controller (RCPC)
can be programmed to divide the PLL frequency by 1 or any even divisor between 2 and

30. The maximum ARM720T core operating frequency is 76.205 MHz and maximum sys-

tem operating frequency of 50.803 MHz. If UARTs 0, 1, or 2 are to be used, the system
clock frequency must not be set to less than 50% of the frequency applied to the crystal
input pin (XTALIN) for proper UART operation.

Table 1-2 is a list of the internal clocks with maximum frequency.

Table 1-2. Clock Descriptions

NAME

System Oscillator
Clock (CLK OSC)

32.768 kHz

RTC OSC
1 Hz Clock 1 Hz The 1 Hz Clock is derived by dividing the RTC OSC by 32,768.

PLL System Clock
(CLK PLL)

USB PLL Clock
(USB PLL)

AHB Fast CPU
Clock (FCLK)

AHB Clock (HCLK) 50.803 MHz

USB Clock 48.0 MHz

SSP Clock 50.803 MHz

ADC Clock 50.803 MHz

FREQUENCY

(MAX.)

20 MHz External crystal oscillator input.

32.768 kHz External 32.768 kHz crystal oscillator input.

This is the output from the System PLL. The input for this clock is

304.819 MHz

304.819 MHz

76.205 MHz

CLK OSC, the System Oscillator Clock. The minimum output frequency
is 5 MHz.

This is the output from the USB PLL; the input is CLK OSC. It can be
programmed for any frequency between 5 MHz and 304.819 MHz.

This clock controls the CPU instruction execution speed. It is derived from
the CLK PLL clock, and is prescaled by 2, 4, ...30. The clock is halted
HIGH when the RCPC is in any power down mode other than Standby.

This clock controls the AHB execution speed. It is derived from CLK
PLL and its frequency is CLK PLL divided by 2, 4, ...30. The clock is
halted HIGH when the RCPC is in any power down mode other than
Standby mode. It can be programmed for power savings to turn off
clock individually to DMAC, EMC, EMAC, USB, and CLCDC.

The USB Clock controls the 12 MHz full-speed USB Device interface.
Selectable input from HCLK or USB PLL. Frequency is required to be
48 MHz for proper USB operation (hardware divides by 4).

This clock controls the SSP and the I
HCLK or CLK OSC. Can be divided by 2
individually halted for power savings.

Controls the Touch Screen Controller (TSC) and Brownout Detector. In­put source choice of HCLK or CLK OSC. Source can be divided by 2
(n ≤ 8). This clock can be individually halted for power savings.

DESCRIPTION

2

S interfaces. Source is either

n

(n ≤ 8). This clock can be

n

1-4 Version 1.0

LH79524/LH79525 User’s Guide Overview

Table 1-2. Clock Descriptions (Cont’d)

NAME

CLCD Clock 50.803 MHz

Serial Interface
Clock (UART[2:0] )

Counter/Timer
Clocks

RTC Clock 32.768 kHz

Clock Output
(CLKOUT)

FREQUENCY

(MAX.)

20 MHz

25.415 MHz

50.803 MHz

DESCRIPTION

This clock controls the data rate for pixel transfers to an external LCD
panel. This clock can be separately enabled, disabled and prescaled.
Source can be divided by 2
for power savings.

These clocks control the data transfer rates over the three UART inter­faces. These clocks are all separate and can be separately enabled
and disabled. Clock source can be selected from HCLK or CLK OSC.

These clocks control the transition rates for the internal timers.
The source can be selected from HCLK or the External Timer input
(CTCLK). Each timer is either clocked by CTCLK or HCLK divided by

n

(0 < n ≤ 8).

2
This clock controls the transition rate for the internal real-time clock.

The source can be selected from the 1 Hz Clock, RTC OSC, CLK PLL,
or an External RTC Clock connected to the XTAL32IN pin.

This output clock is available on pin CLKOUT for use with external
peripherals. Input source can be FCLK, HCLK, or CLK OSC.

n

(n ≤ 8). This clock can be individually halted

Version 1.0 1-5

Overview LH79524/LH79525 User’s Guide

1.3.1 Bus Clocking Modes

The ARM720T core (including the cache) and its AHB interface can be operated using
either the Fastbus operation mode or one of two Standard clocking modes (Synchronous
or Asynchronous).

The clocking modes can have significant impact on power consumption and system
throughput, depending upon the application and the speed of external memory. The
ARM720T core and the AHB are clocked by separate signals and the core is capable of
operation at a much higher frequency than the AHB. This higher core speed benefits appli­cations running from cache more than applications requiring frequent AHB access
because each AHB access requires the core and AHB be re-synchronized. Parallel core
and AHB operations can continue with buffered writes to the AHB, but a ll Read accesses
will stall the core until the bus access is completed. Programmers can use the three bus
clocking modes to maximize throughput by reducing the re-synchronization delays (the
number of wait states).

1.3.1.1 Standard Bus Clocking Modes

The Standard bus clocking modes are useful for designs involving low-cost, low-speed
memory, where operation of the core at a faster speed than the AHB is desired. These
modes involve:

• A programmable choice of Synchronous or Asynchronous operation

• Two clocks: HCLK and FCLK.

The AHB interface is controlled by the bus clock (HCLK), qualified by an nWAIT signal.
Figure 1-2 shows the Standard mode clocking arrangement. The core and cache are
driven by FCLK while HCLK drives the bus. FCLK must always be greater than or equal
to HCLK, on a cycle-by-cycle basis. The nWAIT signal can extend a memory access by
inserting entire HCLK cycles into the bus cycle timing.

ARM720T

FCLK

HCLK

WAIT SIGNAL

CORE

INTERFACE

CACHE

AHB

ADVANCED

HIGH-PERFORMANCE

BUS (AHB)

NOTE: This is a conceptual drawing

Figure 1-2. Standard Clocking Modes

1-6 Version 1.0

LH79525-49

LH79524/LH79525 User’s Guide Overview

1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes

Although the frequency of FCLK must always be greater than (or equal to) HCLK, the two
Standard modes vary the relationship between these two clock signals. In the Synchro­nous Mode, the FCLK frequency must be programmed to be an even integer multiple of
the HCLK frequency. Bus accesses in the Synchronous Mode require a re-synchronization
delay of at least one wait state. In the Asynchronous Mode the harmonic relationship
between the clocks need not be maintained; the two clock signals may be of unrelated fre­quency. Bus accesses in the Asynchronous Mode require a minimum re-synchronization
delay of two wait states.

1.3.1.3 Fastbus Extension Bus Clocking Mode

Designs involving frequent accesses of high-speed memory may benefit by using the
Fastbus Extension Mode. This inherently synchronous mode clocks the core, cache, and
AHB at the same frequency. Where the Standard modes utilized two different clo cks, the
Fastbus mode operates the core, cache, and AHB interface with two signals derived from
the same source; essentially the same clock. Figure 1-3 shows the Fastbus Extension
Mode clocking arrangement. The Fastbus Extension Mode does not require re-synchroni­zation delays.

The Fastbus Extension Mode is useful for applications involving frequent AHB accesses.
Although the core’s frequency is limited by the AHB maximum frequency, the Fastbus
Extension Mode avoids the wait-state penalties imposed by the Standard modes.

ARM720T

HCLK_CPU

COMMON CLOCK

SOURCE

NOTE: This is a conceptual drawing

HCLK

CORE

INTERFACE

CACHE

AHB

ADVANCED

HIGH-PERFORMANCE

BUS (AHB)

LH79525-50

Figure 1-3. Fastbus Clocking Mode

Version 1.0 1-7

Overview LH79524/LH79525 User’s Guide

1.4 Reset Strategy

Two external resets, nRESETIN, and nTRST, are used for the LH79524/LH79525. If
nRESETIN is asserted, all internal registers EXCEPT the JTAG circuitry within the
device are set to their default state. The nRESETIN signal should be held LOW for the
crystal stabilization time + 200
power-up. If nTRST is asserted, only the JTAG circuitry is set to its default state.

There are two types of internal resets for the LH79524/LH79525. A software reset resets
all internal registers, except the JTAG circuitry, to their default state. The other internal
reset is the watchdog timer (WDT) reset, which also resets all internal registers, except the
JTAG circuitry, to their default state. For more information on these internal resets, refer to
the Reset, Clock, and Power Controller, and Watchdog Timer chapters.

This document uses the term ‘system reset’ to refer to either an nRESETIN reset, software
reset, or a watchdog timer reset. The system reset is also brought out to an external pin
(nRESETOUT). The nRESETOUT pin is held LOW for 8 HCLKs after HCLK becomes
active following a system reset.

At power-on reset (nRESETIN), the type of memory that the CPU boots from is determined
by the state that PC7, PC6, PC5, and PC4 are externally connected to, as shown in
Table 1-3. If left undriven, the default value is 0x0, as determined by internal pull-down
resistors. If the CPU is to boot from external memory, the nCS1 Chip Select is used. If the
CPU is to boot from UART, UART0 is used.

μs (the time varies depending on crystal used) during

Table 1-3. Port C Settings For Boot

PC[7:4] BOOT CONFIGURATION

0x0 NOR Flash or SRAM; 16-bit data bus; nBLEx is LOW for reads
0x1 NOR Flash or SRAM; 16-bit data bus; nBLEx is HIGH for reads
0x2 NOR Flash or SRAM; 8-bit data bus; nBLEx is LOW for reads
0x3 NOR Flash or SRAM; 8-bit data bus; nBLEx is HIGH for reads
0x4 NAND Flash; 8-bit data bus; 3-byte address
0x5 NAND Flash; 8-bit data bus; 4-byte address
0x6 NAND Flash; 8-bit data bus; 5-byte address
0x7 NAND Flash; 16-bit data bus; 3-byte address
0x8 NOR Flash or SRAM; 32-bit data bus; nBLEx is LOW for reads

0x9 NOR Flash or SRAM; 32-bit data bus; nBLEx is HIGH for reads
0xA Undefined
0xB Undefined
0xC NAND Flash; 16-bit data bus; 4-byte address
0xD NAND Flash; 16-bit data bus; 5-byte address
0xE I
0xF UART0

2

C

1-8 Version 1.0

LH79524/LH79525 User’s Guide Overview

1.4.1 Resetting the Test Access Port Controller

The on-chip Test Access Port (TAP) Controller has an independent reset pin, nTRST.
However, it must also be reset at power on, or any time the SoC is reset to ensure it exits
the power up sequence in Normal Mode.

To ensure this, an external AND gate is necessary to AND nTRST and nRESETIN.
Figure 1-4 illustrates the minimal circuit capable of guaranteeing the proper reset signals.
If the application will require a push button reset, the circuit in Figure 1-5 is recommended.

LH79524 / LH79525

nTRST

nRESETIN

nTRST

nRESETIN

Figure 1-4. Reset Circuit for TAP Controller

LH79525-116

Version 1.0 1-9

Overview LH79524/LH79525 User’s Guide

V+

nRESETIN

V+

PUSHBUTTON

RESET

V+

POWER ON RESET

V+

nTRST

SYSTEM RESET TO

OTHER PERIPHERALS

nRESETIN

nTRST

Figure 1-5. Reset Circuit for TAP Controller Including a Push Button

LH79524 / LH79525

LH79525-118

1.4.2 Hardware Requirements at Reset

A number of pins contain on-chip pull up or pull down resistors that provide a logic state
following reset. Other pins require external pull up or pull down resistors because their
state is read by the core prior to power becoming stable. Thus the state of these pins can­not be guaranteed using the internal resistors.

1.4.2.1 Floating Inputs

Many applications require extremely low standby and operating current consumption,
especially in battery operated devices. For minimum current, unused inputs must never be
left floating (unconnected). Each input must be pulled up or pulled down with a 33 kΩ resis-
tor (or smaller). In addition to terminating input pins, this also allows selecting the reset
state of input pins using pull up (logical 1 at reset) or pull down (logical 0 at reset) resistors.

1.4.2.2 Test Pins

The two test pins, TEST1 and TEST2, require being tied HIGH for the SoC to boot into Nor­mal Operation Mode. Without tying these pins HIGH, the chip may boot into PLL Bypass
Mode. To enter Embedded ICE Mode, TEST1 is pulled LOW and TEST2 pulled HIGH;
nBLE0 has a sufficient internal pull up.

1-10 Version 1.0

LH79524/LH79525 User’s Guide Overview

1.4.2.3 Active Pull Ups

The boot mode — NOR Flash, NAND Flash, SRAM, I2C, or UART — is selected by
the value latched on the rising edge of the nRESETOUT signal from the state of Port C,
pins [7:4]. Pins PC[7:6] are used during NAND Flash booting as control signals, but PC[5:4]
have no other use following the end of reset. Therefore, those two GPIO pins can be used
during normal operation if an active pullup is used, gated by the nRESETOUT signal.

Figure 1-6 shows a schematic representation of one active pullup circuit. One circuit is
required for each PCx pin to be pulled high during reset. nRESETOUT is presented to the
Gate (pin 1) of the P-Channel FET. When active (LOW), nRESETOUT causes the transistor
to turn on, and pull the PCx input HIGH. When nRESETOUT transitions from LOW to HIGH
at the end of the reset period, the value on PC[7:4] is latched and the FET is turned off, thus
allowing those pins to be used for general purpose I/O or as address pins A[21:20]. As shown
in the figure, a common pull up resistor can be used for all of the FETs.

+3.3 V

120 Ω

BSS84

32

1

BSS84

32

1

LH79524/ LH79525

PCx

nRESETOUT

PCy

Figure 1-6. Active Pullup Circuit

LH79525-104

Version 1.0 1-11

Overview LH79524/LH79525 User’s Guide

1.5 AHB Bus Master Priority and Arbitration

The LH79524/LH79525 have five AHB masters - the ARM720T processor, the DMA
Controller, the Color LCD Controller, USB Device, and the Ethernet Controller. Two of the
masters — the ARM
cating with all the memory controllers and peripherals. The LCD Controller, USB Device,
and Ethernet Controller interface to the main AHB bus via a slave interface for program­ming and via a master interface for accessing SDRAM and Static Memory Controllers.

The default priorities for the five different AHB masters are indicated in Table 1-4.

720T processor and the DMA controller — are capable of communi-

Table 1-4. Default Bus Master Priority

PRIORITY BUS MASTER PRIORITY

1 (Highest) CLCD Controller
2 Ethernet
3 USB Device
4 DMA Controller
5 (Lowest) ARM720T Core (Default)

1.6 Memory Interface Architecture

The LH79524/LH79525 provides the following data-path-management resources on chip:

• AHB and APB data buses

• 16KB of internal SRAM accessible by the ARM
Ethernet Controller, or LCD Controller

• A static and dynamic memory controller with a 24-bit address and 16/32-bit data
interface

• A 4-channel general purpose DMA controller

All system resources accessible by the LH79524/LH79525 are memory mapped. These
include external resources (e.g. ROM, PROM, SRAM, SDRAM, External Peripherals) and
internal resources (system configuration registers, peripheral configuration registers, and
internal memory).

The external memory space is partitioned into eight banks. Each bank spans 512MB. The
start address of each bank is fixed and is determined by the three highest order bits of the
32-bit AHB address. These banks define the type of resource being addressed. One bank
can only contain external static memory devices connected to the External Bus Interface
(EBI). Another bank can only contain external SDRAM devices connected to the EBI.
Another bank contains only the internal SRAM, connected to the AHB. Finally, another
bank is reserved for accessing the system configuration registers themselves, as well as
many of the peripheral control registers. See Table 1-5.

720T processor, DMA Controller,

1-12 Version 1.0

LH79524/LH79525 User’s Guide Overview

This memory map partition has four configurations, based on the setting of the REMAP bits
in the Reset, Clock, and Power Controller.

The external static memory bank is divided into four sections, each having a Chip Select
associated with it. Each section has 24 address lines. When using 32-bit wide memories
each section is 64 MB, 16-bit memories have 32 MB sections, and 8-bit memories have 16
MB sections. When the Chip Select doesn’t occupy the complete bank, it is aliased and
doesn’t cause a memory abort. The external SDRAM bank is divided into two 256 MB sec­tions, each having a Chip Select associated with it. The peripheral register section is
divided into 4KB peripheral sections. See Table 1-6 through Table 1-12.

Table 1-5. AHB Memory Mapping

ADDRESS REMAP = 00 REMAP = 01 REMAP = 10 REMAP = 11

0x00000000 - 0x1FFFFFFF nCS1 nDCS0 Internal SRAM nCS0
0x20000000 - 0x3FFFFFFF SDRAM SDRAM SDRAM SDRAM
0x40000000 - 0x5FFFFFFF Static Memory Static Memory Static Memory Static Memory
0x60000000 - 0x7FFFFFFF Internal SRAM Internal SRAM Internal SRAM Internal SRAM

0x80000000 - 0x80001FFF Boot ROM Boot ROM Boot ROM Boot ROM

0x80002000 - 0xFFFBFFFF Invalid Access

NOTES:

1. REMAP is initialized to '00' upon system reset.

2. Right after system reset or when REMAP = 00, external static memory Chip Select 1 is mapped to lower

memory (0x00000000 - 0x1FFFFFFF), which means the same Chip Select (nCS1) can be accessed from
two locations: 0x00000000 and 0x44000000.

3. Programming REMAP to 01 will map SDRAM Chip Select 0 to lower memory, which means the same Chip

Select (nDCS0) can be accessed from two locations: 0x00000000 and 0x20000000.

4. Programming REMAP to 10 will map internal SRAM to lower memory, which means the same physical

memory can be accessed from two locations: 0x00000000 and 0x60000000.

5. Programming REMAP to 11 will map external static memory Chip Select 0 to lower memory, which means

the same Chip Select (nCS0) can be accessed from two locations: 0x00000000 and

6. Invalid Access memory areas will cause a memory abort.

0x40000000.

Table 1-6. External Static Memory Section Mapping

START ADDRESS

REMAP = ‘XX’

0x40000000 - 0x43FFFFFF Chip Select 0 nCS0 1
0x44000000 - 0x47FFFFFF Chip Select 1 nCS1 2
0x48000000 - 0x4BFFFFFF Chip Select 2 nCS2

0x4C000000 - 0x4FFFFFFF Chip Select 3 nCS3

0x50000000 - 0x5FFFFFFF Invalid Access /// 3

NOTES:

1. Also accessible at 0x00000000 when REMAP = 11

2. Also accessible at 0x00000000 when REMAP = 00

3. An access to this area will cause a memory abort

EXTERNAL DEVICE PIN NOTES

Version 1.0 1-13

Overview LH79524/LH79525 User’s Guide

Table 1-7. SDRAM Memory Section Mapping

START ADDRESS

REMAP = ‘XX’

0x20000000 - 0x2FFFFFFF Chip Select 0 nDCS0*
0x30000000 - 0x3FFFFFFF Chip Select 1 nDCS1

NOTE: *Also accessible at 0x00000000 when REMAP = 01.

DEVICE PIN

Table 1-8. Internal SRAM Memory Section Mapping

START ADDRESS

REMAP = ‘XX’

0x60000000 - 0x60003FFF 16 KB Internal SRAM 1

0x60004000 - 0x7FFFFFFF Internal SRAM (mirrored) 2

NOTES:

1. Also accessible at 0x00000000 when REMAP = 10

2. An access to this area is mapped to the lower 16KB and will not cause a memory abort

DESCRIPTION NOTES

Table 1-9. Boot ROM Memory Section Mapping

START ADDRESS

REMAP = ‘XX’

0x80000000 - 0x80001FFF 8 KB Boot ROM

0x80002000 - 0x9FFFFFFF Invalid Access*

DESCRIPTION

NOTE: *An access to this area will cause a memory abort.

If, following system reset, the boot configuration is set to 0bX1XX, an override of nCS1
occurs. In this circumstance, the Boot ROM is selected for the locations in the memory
map where nCS1 is normally selected. This causes the CPU to execute the predefined
code contained in the Boot ROM, allowing booting from NAND Flash, UART, or I

2

C; see
Table 1-10. This override can be disabled by writing a 0 to the nCS1 Override bit
(CS1OV:CS1O) in the Boot Controller. The override can be re-enabled by writing a 1 to
CS1OV:CS1O. If on system reset the boot configuration is set to 0bX0XX, nCS1 remains
mapped as described above and CS1OV:CS1O has no effect on the memory map.

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LH79524/LH79525 User’s Guide Overview

Table 1-10. AHB Memory Map on Power-up when Boot Configuration = 0bX1XX

ADDRESS REMAP = 00

0x00000000 - 0x1FFFFFFF Boot ROM
0x20000000 - 0x2FFFFFFF SDRAM nDCS0
0x30000000 - 0x3FFFFFFF SDRAM nDCS1
0x40000000 - 0x43FFFFFF Static Memory nCS0
0x44000000 - 0x47FFFFFF Boot ROM
0x48000000 - 0x4BFFFFFF Static Memory nCS2

0x4C000000 - 0x4FFFFFFF Static Memory nCS3

0x50000000 - 0x5FFFFFFF Invalid Access*
0x60000000 - 0x7FFFFFFF Internal SRAM

0x80000000 - 0x80000FFF Boot ROM

0x80001000 - 0xFFFBFFFF Invalid Access*

NOTE: *An access to this area will cause a memory abort.

Table 1-11. Primary AHB Peripheral Register Mapping

ADDRESS RANGE DEVICE

0xFFFC0000 - 0xFFFE6FFF APB Bridge

0xFFFF7000 - 0xFFFF0FFF Invalid Access*
0xFFFF1000 - 0xFFFF1FFF External Memory Controller
0xFFFF2000 - 0xFFFF3FFF Invalid Access*
0xFFFF4000 - 0xFFFF4FFF Color LCD Controller

0xFFFF5000 - 0xFFFF5FFF USB Device
0xFFFF6000 - 0xFFFFEFFF Invalid Access*
0xFFFFF000 - 0xFFFFFFFF Vectored Interrupt Controller

NOTE: *An access to this area will cause a memory abort.

Version 1.0 1-15

Overview LH79524/LH79525 User’s Guide

Table 1-12. APB Peripheral Register Mapping

ADDRESS RANGE DEVICE

0xFFFC0000 - 0xFFFC0FFF UART0
0xFFFC1000 - 0xFFFC1FFF UART1
0xFFFC2000 - 0xFFFC2FFF UART2
0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Convertor
0xFFFC4000 - 0xFFFC4FFF Timer Module
0xFFFC5000 - 0xFFFC5FFF I
0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port
0xFFFC7000 - 0xFFFC7FFF Ethernet
0xFFFC8000 - 0xFFFC8FFF I
0xFFFC9000 - 0xFFFD8FFF Reserved*

0xFFFD9000 - 0xFFFD9FFF GPIO Ports M&N
0xFFFDA000 - 0xFFFDAFFF GPIO Ports K&L
0xFFFDB000 - 0xFFFDBFFF GPIO Ports I&J

0xFFFDC000 - 0xFFFDCFFF GPIO Ports G&H
0xFFFDD000 - 0xFFFDDFFF GPIO Ports E&F

0xFFFDE000 - 0xFFFDEFFF GPIO Ports C&D
0xFFFDF000 - 0xFFFDFFFF GPIO Ports A&B

0xFFFE0000 - 0xFFFE0FFF Real Time Clock

0xFFFE1000 - 0xFFFE1FFF DMA Controller

0xFFFE2000 - 0xFFFE2FFF Reset Clock and Power Controller

0xFFFE3000 - 0xFFFE3FFF Watchdog Timer

0xFFFE4000 - 0xFFFE4FFF LCD ICP (AD-TFT/HR-TFT/ALI support)

0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral

0xFFFE6000 - 0xFFFE6FFF Boot Controller

0xFFFE7000 - 0xFFFEFFFF Invalid Access

2

C

2

S Converter

NOTE: *Reads as ‘0’, writes have no effect

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LH79524/LH79525 User’s Guide Overview

1.7 Instruction and Data Cache

The ARM720T Core includes an 8KB Cache, Cache Controller, Memory-Management
Unit (MMU) and Write Buffer. A single cache is used for both instructions and data. The
cache is an important core feature because the AHB carries all Core, DMA, LCD Display,
and Ethernet traffic. For best bandwidth utilization, software should be structured to ensure
that the Core is running from within its cache whenever possible.

At reset, the Write Buffer, Cache, and MMU are disabled and the MMU’s Translation
Lookaside Buffer (TLB) is flushed. If the MMU is utilized, software can determine memory
cachability by bank or by page. For best performance, the Color LCD frame buffer should
not be located in a cachable region.

1.8 Memory Management Unit (MMU)

The ARM720T core in the LH79524/LH79525 includes an MMU that performs three pri­mary functions: It translates virtual addresses into physical addresses, it enables cache
and write buffering for particular ranges of virtual addresses, and it controls memory
access permissions. When the MMU is turned off, as it is at reset, all virtual addresses are
output directly onto the physical address bus (the AHB).

The MMU supports memory accesses based on ‘sections’ or ‘pages’ of memory. Sections
are 1MB blocks of memory; pages can be either small or large. Small pages consist of
4KB blocks of memory. Additional access control mechanisms are extended to 1KB
subpages. Large pages consist of 64KB blocks of memory. Large pages are supported
to allow mapping of a large region of memory while using only a single entry in the
Translation Lookaside Buffer (TLB). Additional access control mechanisms are extended
to 16KB subpages.

For more information about the core, cache, and MMU, refer to the ARM document
‘ARM720T Processor Data Sheet’, at www.arm.com.

Version 1.0 1-17

Chapter 2

Analog-to-Digital Converter/ Brownout Detector

The LH79524/LH79525 incorporate an analog-to-digital converter (ADC) and implements
a touch screen controller (TSC) and brownout detector with interrupt.

2.1 Theory of Operation

The ADC and TSC incorporate:

• 10-bit ADC with integrated sample and hold, and fully-differential high impedance
signals, and single-ended or ratiometric reference inputs

• A 10-channel multiplexer that routes user-selected inputs to the ADC in single-ended
and ratiometric modes

• A 16-entry × 16-bit-wide FIFO containing the 10-bit ADC output

• Active input matrix provides a bias-and-control network for the touch screen interface
and support functions, which are compatible with industry-standard 4-, 5-, 7-, and 8-wire
touch-sensitive panels

• Pen-down sensing circuit and interrupt generator

• Independently-controlled voltage reference generator

• Conversion automation function to minimize controller interrupt overhead

• Three power modes: Off, Standby, and Run

• Brownout detector with interrupt.

2.1.1 Operational Summary

The ADC is an AMBA-compliant SoC peripheral that connects as a slave to the APB. The
ADC block consists of an 10-channel, 10-bit Analog-to-Digital Converter with integrated
Touch Screen Controller. The complete touch screen interface is achieved by combining
the front-end biasing, control circuitry with analog-to-digital conversion, reference genera­tion, and digital control. Figure 2-1 shows a block diagram of the ADC.

The ADC has a bias-and-control network that allows correct operation with 4-, 5 -, 7 -, and
8-wire touch panels. A 16-entry × 16-bit wide FIFO holds a 10-bit ADC output and a 4-bit
tag number. When the screen is touched, it pushes the conductive coating on the cover­sheet against the coating on the glass, making electrical contact. The voltages produced
are the analog representation of the position tou ched. The voltage level of the coversheet
is converted continuously by the ADC and monitored by the system.

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

VLL

BrownOut_INTR

AN0/UL/X+
AN1/UR/X­AN2/IL/Y+
AN3/LR/Y­AN4/WIPER
AN5
AN6/VBAT
AN7
AN8
AN9

EOSINTR

oscen
CLKSEL
PWM

GPI

MUX

8

8

GPEN

GPI

EOCA2DCLK DIGITA

CONTROL BANK STATE MACHINE

Start_acq A2DON

GENERATOR

3

2

ANALOG
BIAS AND
CONTROL

PenIRQ

CLOCK

11-TO-1

MUX

VREF-

PWMpenIRQ

2

14

15

HWR

LWR

A2DCLK DIGITAL
A2DCLK ANALOG

VREF

A2DCLK_ANALOG

CBTAG

4

+IN

10b A/D OUT

-IN
START

A2D0N

ADVANCED

PERIPHERAL

BUS (APB)

AN8/VREF+EXT
AN0/UL/X+

4-TO-1

LL/Y+

MUX

VREF+

+REF

D[9:0]

10

-REF

VREF-EXT
AN1/UR/X-

4-TO-1

AN3/LR/Y-

MUX

VREF-

CBTAG

4

10-BIT

RESULT CBTAGXX

FIFO

FwaterINTR FovmINTR

16

BANDGAPON

VREF+ EN

BGAP
VREF

VREF-

Figure 2-1. ADC Block Diagram

The ADC block can perform a sequence of measurements without intervention from the
ARM core. Examples include:

• Determining touch-screen biasing switch configuration.

• Ascertaining how much settling time is required before making a measurement.

• Determining the ADC input source and ADC reference source.
From 1 to 16 different measurements can be performed in a sequence. The number of

sequence steps is stored in the PC Register.
The biasing switch configuration, settling time, and ADC mux settings fo r each of the 1 to

16 measurements in the sequence are stored in an entry in the Control Bank. The mea­surement sequence can be triggered by either software or a Pen Down Interrupt.

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

The Control Bank state machine fetches each entry from the Control Bank and stores it in
the Low Word register (LW) and High Word register (HW) for the duration of the measure­ment. When the measurement is complete, the Control Bank state machine stores the ADC
result and the Control Bank instruction number in the measurement FIFO, then obtains the
next configuration from the Control Bank and loads it into LW and HW.

When all steps of the sequence are complete, or at a programmed FIFO watermark level,
the Control Bank state machine signals the ARM core to read results from the FIFO.

From the FIFO, software can read each measurement result and corresponding input
configuration, as represented by the Control Bank instruction number. If the FIFO is full
the control bank state machine continues to take measurements and the state machine
triggers the FIFO Overrun Interrupt.

The ADC can be programmed to repeat the measurement sequence indefinitely, or to pause
at the end of a sequence and wait for a new Pen Down Interrupt or software trigger. If the
sequence does not repeat continuously, softw are pro grams t he HW and LW registers with the
contents of the Idle High Word (IHWCTRL) and Idle Low Word (ILWCTRL) register values with
the bias and ADC multiplexer settings until a new measurement sequence is triggered.

2.1.2 Bias-and-Control Network

The bias-and-control network supports 4-, 5-, 7-, and 8-wire touch pane ls. Multiplexers on
the reference inputs enable connection in both single-ended and ratiometric modes.

• For 4-wire operation, connection is to inputs AN/UL/X+, AN1/UR/X-, AN2/LL/Y+, and
AN3/LR/Y-. Pull-up and pull-down FETs allow X and Y coordinate measurement in addi­tion to pen-pressure sensing. The Pen Interrupt line is also available via the Interrupt
Masking/Enabling register (see Section 2.2.2.4).

• For 5-wire operation, panel connections are to AN/UL/X+, AN1/UR/X-, AN2/LL/Y+,
AN3/LR/Y-, and AN4/WIPER inputs. The Pen Interrupt line is also available in this mode.

• For 7-wire operation, connections are the same as the 5-wire touch panel with a second
wire added to the Upper Left and Lower Right corners.

• For 8-wire operation, connections are the same as the 4-wire touch panel with a second
wire added to each of the connections. This configuration also requires a single external
MOSFET.

• Details for wiring 4-, 5-, 7, and 8-wire touch panels appear in the application note ‘Using
the SHARP ADC with Resistive Touch Screens’, available at www.sharpsma.com.

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

3

AVDD

AN0/UL/X+

AN1/UR/X-

AN2/LL/Y+

AN3/LR/Y-

AN4/WIPER

100K

AVDD

AVDD

AVDD

AVDD

PENIRQ

B2

B3

B5

B13

100K

PENIRQ

B12

B4

B6

B7

B8

11-TO-1

ANALOG

MUX

A/D IN+

AN5
AN6
AN7
AN8
AN9

VREF -

A3

TSCHWR[6]

TSCHWR[5]

A2

TSCHWR[4]

Figure 2-2. Bias-and-Control Network Block Diagram

A1

TSCHWR[3]

A0

LH79525-5

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

4

2.1.3 Clock Generator

The ADC has a programmable measurement clock derived from the ADC peripheral clock
generated by the RCPC. The clock source is selectable from HCLK or the System oscilla­tor clock, and can be prescaled. The clock supplies the time base for the measurement
sequencer and the successive-approximation circuitry. Higher clock frequencies allow
faster measurement throughput. Slower clock frequencies allow more settling time for a
measurement and can reduce ADC power consumption. If the clock is too slow, the sam­ple-and-hold amplifier on the ADC input may droop before the measurement is complete.

2.1.4 Brownout Detector

The Brownout Detector is an asynchronous comparator that compares a divided version
of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a
trip point, the Brownout Detector sets a bit in the IS Register (see Section 2.2.2.8). An
interrupt is directly connected to the VIC. This allows the SoC to notify peripherals of an
impending shutdown and provides the ADC with time to save its state.

The Brownout detector also indicates brownout if the clock is off (PWM bits of PC register
are 0b00 or 0b11). In addition, the Brownout Detector indicates a brownout condition on
startup until the VDDA pin rises above the trip point.

2.1.5 SAR Architecture

While there are various SAR implementations, the basic architecture is simple. Figure 2-3
shows this architecture.

VREF

TRACK/HOLDANALOG IN

REGISTER

VIN

VDAC

N-BIT

DAC

N

N-BIT

SAR

LOGIC

COMPARATOR

+

_

DIGITAL DATA OUT

(SERIAL or PARALLEL)

LH79525-5

Figure 2-3. Simplified N-bit SAR Architecture

Version 1.0 2-5

Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

5

The analog input voltage (VIN) is held on a track/hold. The N-bit register is set to midscale
(100...0, where the most-significant bit is set to 1) to implement the binary search algo­rithm. This forces the DAC output (VDAC) to be VREF

÷ 2, where VREF is the reference
voltage provided to the ADC. Then a comparison is performed to determine whether VIN
is less than, or greater than VDAC:

• If VIN is less than VDAC, the comparator output is a logic LOW and the most-significant

bit of the N-bit register is cleared to 0.

• If VIN is greater than VDAC, the comparator output is a logic HIGH (or 1) and the

most-significant bit of the N-bit register remains set to 1.

The SAR control logic then moves to the next bit down, forces that bit HIGH, and conducts
another comparison. The SAR control logic repeats this sequence until it reaches the
least-significant bit. When the conversion is complete, the N-bit digital word is available in
the register.

Figure 2-4 shows an example of a 4-bit conversion. In this figure, the y-axis and the bold
line show the DAC output voltage. In this example:

1. The first comparison shows that VIN < VDAC. Consequently, bit 3 is 0. The DAC is

then set to ob0100 and the second comparison is conducted.

2. In the second comparison, VIN > VDAC , so bit 2 remains at 1. The D A C is then set to

0b0110 and the third comparison is conducted.

3. In the third comparison, bit [1] is set to 0 and the DAC is then set to 0b0101 f or the last

comparison.

4. In the final comparison, bit 0 remains at 1 because VIN

VDAC

VREF

3/4 VREF

1/2 VREF

1/4 VREF

BIT 3 = 0

(MSB)

BIT 2 = 1 BIT 1 = 0 BIT 0 = 1

> VDAC.

(LSB)

VIN

TIME

Figure 2-4. Example of a 4-bit SAR ADC Operation

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

Four comparison periods are necessary for a 4-bit ADC. Generally, an N-bit SAR ADC
requires N comparison periods and will not be ready for the next conversion until the
current conversion is completed.

Another feature of SAR ADCs is that power dissipation scales with the sample rate. By
comparison, flash or pipelined ADCs usually have constant power dissipation as opposed
to sample rate. This SAR ADC feature is especially useful in low-power applications or
applications where data acquisition is not continuous.

2.1.6 Battery Control Feature

The battery control pin (BATCNTL) allows control of external battery circuits by the SoC.
An external resistor divider allows monitoring the external battery voltage, as shown
in Figure 2-5. External switches Q1 and Q2 connect the voltage divider to
the battery. These switches are driven by the BATCNTL pin, which remains HIGH for the
duration of the measurement. R1 and R2 should be chosen so that during normal opera­tion (with BATCNTL LOW), the voltage at VBAT is somewhere within the common mode
input range of the ADC. For example if the battery voltage is 6 V nominal, choose R1= 300
kΩ and R2 = 100 kΩ to give IN+ = 1.5 V at a load of only 15

μA on the battery.

LH79524 /LH79525

R1

AN

x

CTCLK/ INT4/BATCNTL

MUX

IN+

A/D

10

LH79525-119

BATTERY

VBAT

+

_

Q1

R2

Q2

Figure 2-5. Use of the BATCNTL Pin

Note that the BATCNTL pin is only active when making the measurement on that particular
ADC channel. All other times BATCNTL is LOW.

Software can easily configure the ADC for battery voltage measurement. Program the
PC:BATLOC field to correspond to the channel to which the battery voltage measurement
is connected. When HW:INP (the + Input Mux selection) equals the value in PC:BATLOC,
the BATCNTL pin goes HIGH and loads the battery through th e external switch as shown
in Figure 2-5. In addition, PC:BATEN, the Battery Control Enable signal, must be pro­grammed to 1. When the BATCNTL pin is not required to g o HIGH, for example when the
ADC is used in a general purpose application, PC:BATLOC should be programmed so that
it will never equal any of the inputs that will be used in the application e.g. 0b1111. Also
the PC:BATEN can be programmed to 0 to disable this function.

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.1.7 Timing Formulas

The throughput-conversion time consists of one cycle of Get Data state added to 16 cycles
of measurement. Starting from the Idle state, the time for a complete measurement
sequence, in clock cycles, is calculated as:

1CIS + MS × (TCT + STC) + 1CEOS

where:

• 1CIS is one cycle in Idle state

• MS is the number of measurements in the sequence

• TCT is the throughput conversion time of 17 cycles

• STC is the number of settling time cycles per measurement

• 1CEOS is one cycle in the End of Sequence state.
This equals:

• Two cycles, plus

• The number of measurements in sequence times, plus

• The throughput conversion time (17 cycles), plus

• The number of settling time cycles per measurement.

2.1.8 Interrupts

The ADC has five interrupts:

• Brownout Interrupt (BROWNOUTINTR)

• Pen Interrupt (PENIRQ)

• End of Sequence Interrupt

• FIFO Watermark Interrupt

• FIFO Overrun Interrupt
All five interrupts make up the combined interrupt TSCIRQ, and presented to the VIC.
Each of the five individual maskable interrupts, except Brownout, is enabled or disabled by

changing the mask bits in the IM Register (see Section 2.2.2.4). Software can read the
interrupt status bits through the IS Register, even if corresponding mask bits are set (see
Section 2.2.2.8). Clearing the mask bits does not clear the interrupt status.

2.1.8.1 Brownout Interrupt

The Brownout Interrupt (BROWNOUTINTR) is asserted when the supply voltage dips
below the trip-point voltage. This interrupt status is latched in the IS Register. It remains
HIGH until the BOIC bit of the Interrupt Clear (IC) register is asserted. The instantaneous
raw status of the BROWNOUTINTR is stored in the GS Register (see Section 2.2.2.7). The
Brownout Interrupt has its own dedicated output to the VIC.

NOTE: The latency between clearing the latched Brownout Interrupt and the time when it can be set again is

one A2DCLK cycle. Polled systems should use the unlatched Brown-Out Raw Interrupt Status bit
(bit [9]) in the GS register instead of the latched interrupt status in the IS register.

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.1.8.2 Pen Interrupt

The Pen Interrupt (PENIRQ) is enabled when the settings on the bias switches are
switched to the Pen Interrupt Mode configuration and the ADC is set up to trigger a
measurement on PENIRQ. The Pen Interrupt is used by the TSC to start the state
machine. The state machine may begin a sequence of conversions, depending on
the contents of the General Configuration (GC) register, when a Pen Interrupt occurs
(see Section 2.2.2.6). PENIRQ is latched and remains HIGH until the PENIC bit of the
Interrupt Clear (IC) register is asserted (see Section 2.2.2.14). The latched value of the
Pen Interrupt is stored in the Interrupt Status register. The instantaneous raw status of the
Pen Interrupt is stored in the General Status (GS) register (see Section 2.2.2.7).

NOTE: If a measurement sequence is configured to keep the Touch Screen biased for Pen detect on every

measurement, PENIRQ is not generated on every sequence. If, on the other hand, the Pen detect
circuit is disconnected, there will be an edge every time the system enters Idle state.

2.1.8.3 End-of-Sequence Interrupt

The End-of-Sequence Interrupt occurs after the programmed number of conversions
(NOC) occurs. After the ADC converts all the data for a given sequence of conversions,
this interrupt goes HIGH. The End-of-Sequence Interrupt is latched and remains HIGH
until the EOSINTC bit of the IC Register is set.

2.1.8.4 FIFO Watermark Interrupt

The FIFO Watermark Interrupt occurs when the number of entries in the FIFO is greater
than or equal to the programmed watermark level FIFOWMK (GC Register, bits [6:3]). This
interrupt clears when the FIFO contents falls below the watermark level.

2.1.8.5 FIFO Overrun Interrupt

The FIFO Overrun Interrupt occurs when the receiving logic tries to place data into the
FIFO after the FIFO has been completely filled, exceeding the FIFO’s maximum capacity
of 16 entries. The interrupt is cleared when the FIFO is read.

2.1.9 Application Details

An application note entitled ‘Using the SHARP ADC with Resistive Touch Screens’ is avail­able from SHARP that provides more detailed application information dealing with use and
programming of the ADC.

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2 Register Reference

This section provides the ADC and Brownout Detector register memory mapping and
bit fields.

2.2.1 Memory Map

The base address for the ADC is 0xFFFC3000.
Table 2-1 Summarizes the ADC registers. Address offsets in the table are from the base

address. All registers are little endian format.

Table 2-1. ADC Register Summary

ADDRESS

OFFSET

0x00 HW High Word Register
0x04 LW Low Word Register
0x08 RR Results Register

0x0C IM Interrupt Masking Register

0x10 PC Power Configuration Register
0x14 GC General Configuration Register
0x18 GS General Status Register

0x1C IS Interrupt Status Register

0x20 FS FIFO Status Register

0x24 - 0x60 HWCB0 - HWCB15 High Word Control Bank Registers

0x64 - 0xA0 LWCB0 - LWCB15 Low Word Control Bank Registers

0xA4 IHWCTRL Idle High Word Registers
0xA8 ILWCTRL Idle Low Word Registers

0xAC MIS Masked Interrupt Status

0xB0 IC Interrupt Clear Register

NAME DESCRIPTION

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.2.2 Register Descriptions

2.2.2.1 High Word Register (HW)

HW is the High Word Register. This Read Only status register shows the contents of the
current conversion’s high word in the control bank. There is a on e-to-one correspondence
between the contents of the control bank high word and the contents of this register for the
current conversion in progress.

Table 2-2. HW Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD SETTIME INP INM REFP
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x00

Table 2-3. HW Fields

BITS NAME DESCRIPTION

31:16 /// Reserved Reading returns 0. Write the reset value.

Number of Clock Cycles Specifies the number of clock cycles that the ADC

allows for the input signal to settle to within required accuracy before beginning
conversion. Used with bits [10:8] of the PC Register to set the acquire time in
clock cycles (see Section 2.2.2.5).

15:7 SETTIME

6:3 INP

2INM

1:0 REFP

For example, if Frequency In (ƒIN) = 2 MHz (500 ns period):
PC[10:8] = 010 (i.e., divide ƒIN by 4)
HW[15:6] = 000100000 (i.e., 32 cycles)
Therefore, acquire time is 500 ns × 4 × 32 = 64 μs

In+ Mux Determines the signal connected to the positive input of the ADC.
See Table 2-4.

In- Mux Determines the signal connected to the negative input of the ADC.
1 = GND

0 = Ref- (output of the Ref- Mux)
Ref+ Mux Determines the signal connected to the positive reference of the ADC.

00 = VREF+ (positive terminal of the internal bandgap reference)
01 = AN0 (UL/X+)
10 = AN2 (LL/Y+)
11 = AN8

Version 1.0 2-11

Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

Table 2-4. In + Mux Definition

IN+ BIT6 BIT5 BIT4 BIT3

AN0 (UL/X+) 0 0 0 0
AN1 (UR/X-) 0 0 0 1
AN2 (LL/Y+) 0 0 1 0
AN3 (LR/Y-) 0 0 1 1
AN4 (Wiper) 0 1 0 0
AN5 0 1 0 1
AN6 0 1 1 0
AN7 0 1 1 1
AN8 1 0 0 0
AN9 1 0 0 1
VREF - 1 0 1 0
VREF - 1 0 1 1
VREF - 1 1 0 0
VREF - 1 1 0 1
VREF - 1 1 1 0
VREF - 1 1 1 1

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.2.2.2 Low Word Register (LW)

LW is the Control Bank Low Word Register. This Read Only status register displays the
contents of the current conversion’s low word in the control bank. There is a one-to-one
correspondence between the contents of the control bank low word and the contents of
this register for the current conversion in progress.

Table 2-5. LW Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// BIASCON REFM
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x04

Table 2-6. LW Fields

BIT NAME DESCRIPTION

31:14

/// Reserved Reading returns 0. Write the reset value.

Bias Control These bits turn the FETs on and off, as shown in
Figure 2-2. The bit number corresponds to the FET nu m be r in th e figu r e.
IMPORTANT: bits 9-11 must always be written as 0b000. Writing a 1 to an y

13:2 BIASCON

of these three bits can cause unpredictable results.
1 = FET ON

0 = FET OFF
Ref- Mux Determines the signal connected to the negative reference of the

ADC during Idle Mode.

1:0 REFM

00 = VREF- (negative terminal of the internal bandgap reference).
01 = AN1 (UR/X-)
10 = AN3 (LR/Y-)
11 = AN9

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.3 Results Register (RR)

RR is the Results register. This register contains the oldest entry of the 16-entry × 16-bit
wide result FIFO. Its index in the FIFO’s memory array is contained in the Read Pointer
(RDPTR) bit field in the FIFO Status Register (see Section 2.2.2.9). This register contains
the 10-bit ADC output and the 4-bit tag number from the Control Bank State Machine.
When the FIFO is full, further data writes are temporarily blocked until at least one location
is available for a write. Reading from RR removes the oldest entry from the result FIFO and
increments the RDPTR.

Table 2-7. RR Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD ADCOUT /// CBTAG
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x08

Table 2-8. RR Fields

BIT NAME DESCRIPTION

31:16

15:6 ADCOUT ADC Output Contains the 10-bit digital output of the ADC.

5:4 /// Reserved Reading returns 0. Write the reset value.

3:0 CBTAG

/// Reserved Reading returns 0. Write the reset value.

Control Bank Tag Specifies the entry number (HWCTRLBxx or
LWCTRLBxx) of the Control bank. The entry number (x) ranges from 0 to
15, corresponding to the conversion ass oc iat ed with th e bi t re su lt.

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2.2.2.4 Interrupt Mask Register (IM)

IM is the Interrupt Mask / Enable register. The active bits used in this register are Read/
Write and enable the interrupts. Software can read the status of the interrupt bits through
the IS Register, even if corresponding mask bits are set in this register. The Brown Out
enable is unique in that the Brown Out Interrupt can be programmed to be either an FIQ
or an IRQ. That programming is done in this register. The Interrupt Status (IS) and Masked
Interrupt Status (MIS) registers show only the status of the interrupt, not how it is config­ured. Current configuration can be read from this register. Writing a 0 to an IM bit does not
clear the latched interrupt status in the IS register. The IS register is logically ANDed with
the IE register to create the contents of the Masked Interrupt Status (MIS) register.

Table 2-9. IM Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW
ADDR 0xFFFC3000 + 0x0C

///

INTEN

BOIRQ

PMSK

FWMSK

EOSMSK

FOMSK

Table 2-10. IM Fields

BIT NAME DESCRIPTION

31:7 /// Reserved Reading returns 0. Write the reset value.

Interrupt Enable

6 INTEN

5

4 BOIRQ

3 PMSK

2 EOSMSK

1 FWMSK

0 FOMSK

/// Reserved Reading returns 0. Write the reset value.

1 = Global IRQ interrupts enabled
0 = Global IRQ interrupts masked

Brown Out IRQ Enable Enabling this bit allows the brownout detector to generate an
interrupt request as part of the combined TSCINTR input of the VIC.

1 = Enable Brown Out IRQ to VIC
0 = Disable Brown Out IRQ to VIC

Pen IRQ Interrupt Enable

1 = Pen IRQ enabled
0 = Pen IRQ masked

End-of-Sequence Interrupt Enable

1 = EOS IRQ enabled
0 = EOS IRQ masked

FIFO Watermark Interrupt Enable

1 = FIFO Watermark IRQ enabled
0 = FIFO Watermark IRQ masked

FIFO Overrun Interrupt Enable

1 = FIFO Overrun IRQ enabled
0 = FIFO Overrun IRQ masked

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.5 Power Configuration Register (PC)

In this register, the clock divider bits are programmed to set the system clock frequency for
analog operation. Program bits [3:0] to the number of conversions necessary, depending
on the conversion. Bit [4] can be used as an enable for external I/O pads. If this bit is set
to 1, the Battery Control Logic Pin (BATCNTL) will be a valid output. If an external battery
measurement circuit is not used, this bit should be set to 0.

NOTE: Allow two A2DCLK cycles between successive write cycles to this register. Otherwise, ADC behavior

can become erratic.

Table 2-11. PC Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD BATLOC CLKSEL PWM

BATEN

REFEN

RESET 0000000000000000
RW RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFC3000 + 0x10

NOC

Table 2-12. PC Fields

BIT NAME DESCRIPTION

31:15

14:11 BATLOC

10:8 CLKSEL

/// Reserved Reading returns 0. Write the reset value.

Battery Measurement Location Program this field with the
Channel number corresponding to the location programmed into the
HW:INP field for battery measurement. When PC:BATLOC = HW:INP,
the output pin BATCNTL goes HIGH. At all other times, the BATCNTL
pin is LOW.

To disable toggling the BATCNTL pin, program these bits to a value
that will never appear in HW:INP, for example 0b1111.

Clock Select If the nominal value is used, the only valid settings are
011, 100, 101, and 110.

000 = Clock oscillator (nominally 10 to 20 MHz)
001 = Clock oscillator/2
010 = Clock oscillator/4
011 = Clock oscillator/8
100 = Clock oscillator/16
101 = Clock oscillator/32
110 = Clock oscillator/64
111 = Clock oscillator/128

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

Table 2-12. PC Fields (Cont’d)

BIT NAME DESCRIPTION

Touch Screen Controller Power Mode Tis field also affects the of

the A2DCLK, Band Gap, and A2D signals (see Table 2-13).
00 = Turns off Power Mode and clock; sets the BROWNOUT

field (bit [9]) of the GS Register, indicating tha t a brownout is
detected, even if VDDA_ADC is at the correct voltage.

7:6 PWM

5 REFEN

4 BATEN

3:0 NOC

01 = Standby (wake on SSB or Pen Interrupt, co nvert , re tu rn ); clea rs

the GS:BROWNOUT bit, even if VDDA_ADC is correct voltage.

10 = Run (always on); clears the BROWNOUT field (bit [9]) of the

GS Register, even if VDDA_ADC is at the correct voltage.

11 = Turns off Power Mode and clock; sets the BROWNOUT

field (bit [9]) of the GS Register, indicating tha t a brownout is
detected, even if VDDA_ADC is at the correct voltage.

Reference Enable Enables the internal reference buffer so that the
ADC can use the on-chip reference as the positi ve reference.

1 = Enable
0 = Disable

Battery Control Enable

1 = Battery Control Logic Enabled
0 = Battery Control Logic Disabled

Number of Conversions (NOC) in Sequence Actual number of
conversions is NOC + 1, and ranges from 1 to 16.

Table 2-13. Touch Screen Controller Power Modes

PWM BIT VALUES

00 0 0 0 0
00 1 0 0 0
01 0 0 1 0
01 1 1 1 1
10 0 0 1 1
10 1 1 1 1
11 0 0 0 0
11 1 0 0 0

NOTES:

1. nIDLE refers to whether the state machine is in the Idle state:

1 = Control Bank State Machine is in another state besides the Idle state.
0 = Control Bank State Machine is in the Idle state.

2. A2DCLK ENABLE refers to whether the A2DCLK signal is enabled:

1 = Enables the A2DCLK to the analog circuitry.
0 = Disables the A2DCLK to the analog circuitry. (The clock is always enabled to the digital circuitry.)

3. BANDGAPON refers to whether Band Gap is turned on (required for the Brownout Detector):

1 = Turns on the Band Gap. This setting is required for the Brownout Detector to work.
0 = Turns off the Band Gap, disabling the Brownout Detector.

4. A2DON refers to whether the analog circuitry is enabled for the ADC:

1 = Enables the analog circuitry for the ADC.
0 = Disables the analog circuitry for the ADC.

nIDLE

1

A2DCLK ENABLE

2

BANDGAPON

3

A2DON

4

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.6 General Configuration Register (GC)

In this register, the SSM field triggers the state machine to retrieve the data from the
Control Bank and store it in the appropriate registers for the ADC. If the SSM bits are set
to 0b11 at the end of a sequence, the state machine continues to convert data.

If the SSM bits are set to 0b10 and a value of 0b0000110 is written to the GC Register, the
EOS_UM bit (bit [2]) of the Interrupt Status Register may never get set. This is normal
operation. To accommodate this, wait two A2DCLK periods after setting the SSM bit to 10
before setting the SSB bit.

NOTE: Allow two A2DCLK cycles between successive write cycles to this register. Otherwise, ADC behavior

can become erratic.

Table 2-14. GC Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// FIFOWMK SSB SSM
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW
ADDR 0xFFFC3000 + 0x14

Table 2-15. GC Fields

BIT NAME DESCRIPTION

31:7 /// Reserved Reading returns 0. Write the reset value.

FIFO Watermark Programmed to values between 0 and 15. This value

6:3 FIFOWMK

2 SSB

1:0 SSM

corresponds to watermark levels betwee n 1 an d 16, re sp ec tive ly. Wh en
the FIFO fills to this level, the FIFO generates an interrupt.

Start Sequence Bit

1 = SSB will start the conversion sequence
0 = SSB will not start the conversion sequence

Sequence Start Mode To trigger continuous conversions, set these bits
to 0b11, wait one A2DCLK period, and set the SSB bit to 1. Thereafter,
once any conversions occur and SSM is set to 0b00 to stop the conversions,
conversions can be started again by setting SSM to 0b11, without having to
set SSB.

Note that the Pen Interrupt can only be used when the ADC is configured to
start on Pen Down.

00 = SSB or Pen Interrupt starts new conversions
01 = Pen Interrupt starts new conversions
10 = SSB starts new conversions
11 = Continuous conversions

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.2.2.7 General Status Register (GS)

GS is the General Status Register. In this Read Only register, the 4-bit signal CBSTATE
field shows the current state of the Control Bank state machine. The CBTAG signal con­tains the control bank entry number of the conversion that is taking place.

Table 2-16. GS Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

PENIRQ

BRONOUT

RESET 0000001000010000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x18

CBSTATE CBTAG

Table 2-17. GS Fields

BIT NAME DESCRIPTION

31:10 /// Reserved Reading returns 0. Write the reset value.

Brown-Out Raw Interrupt Status

9 BROWNOUT

8 PENIRQ*

7:4 CBSTATE

3:0 CBTAG

1 = Brown-out Interrupt is active.
0 = Brown-out Interrupt is not active.

Pen IRQ Raw Interrupt Status

1 = Pen IRQ Interrupt is active.
0 = Pen IRQ Interrupt is not active.

Control Bank State Machine Status The only valid values are:
0001 = Idle state; waiting for sequence start trigger

0010 = GET_DATA state
0100 = WAIT_CONV state
1000 = END_OF_SEQ state

Current Conversion Tag Number Contains the current conversion tag
number.

NOTE: *If the Idle state is configured to bias a 4-wire Touch Screen for Pen IRQ detect, the PENIRQ bit is

only set during the one A2DCLK period of the GET_DATA state. To determine if the pen has been
down at all, examine the IS:PENSYNC_UM bit. To determine if the pen was down at both the start
and the end of a measurement sequence, use analog measurements of the pen IRQ voltage at the
beginning and the end of the sequence. Then have a software Schmidt Trigger verify the logic level
at the beginning and end of the coordinate-measurement sequence. Install a Pen IRQ handler func­tion that changes the measurement mode to software triggered and disables Pen IRQ interrupts.
Then stop the timer when it expires. N ext, install an end-of-sequence interrupt handler that reads the
measurement results and determines whether the pen is still down. If the pen is down, the handler
starts the timer for triggering the next measurement. The handler discards the first set of measure­ments taken during the initial Pen Down detection. Otherwise, the handler posts the current pen posi­tion to some sort of OS queue. Enable Pen Triggered Measurements to start the system.

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.8 Interrupt Status Register (IS)

IS is the Interrupt Status register. This Read Only register provides the unmasked value
of each interrupt. The BROWNOUT, PENSYNC, and EOS interrupts are latched and must
be cleared by writing to the Interrupt Clear (IC) register. The FWATER and FOVRN inter­rupts are cleared when the contents of the FIFO no longer exceed their thresholds.

Table 2-18. IS Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

EOS_UM

PENSYNC_UM

BROWNOUT_UM

RESET 0000000000010000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x1C

FOVRN_UM

FWATER_UM

Table 2-19. IS Fields

BIT NAME DESCRIPTION

31:5 /// Reserved Reading returns 0. Write the reset value.

Unmasked Brown-Out Interrupt Status

4 BROWNOUT_UM

3 PENSYNC_UM

2 EOS_UM

1 FWATER_UM

0 FOVRN_UM

1 = Brown-out Interrupt is active.
0 = Brown-out Interrupt is not active.

Unmasked Pen Interrupt Status

1 = Pen Interrupt is active.
0 = Pen Interrupt is not active.

Unmasked End-of-Sequence Interrupt Active

1 = EOCIA Interrupt is active.
0 = EOCIA Interrupt is not active.

Unmasked FIFO Watermark Interrupt Active

1 = FIFO Watermark Interrupt is active.
0 = FIFO Watermark Interrupt is not active.

Unmasked FIFO Overrun Interrupt Active

1 = FIFO Overrun Interrupt is active.
0 = FIFO Overrun Interrupt is not active.

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2.2.2.9 FIFO Status Register (FS)

FS is the FIFO Status Register. This Read Only register indicates the FIFO fill status.

Table 2-20. FS Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD /// WRPTR RDPTR FFF

FEMPTY

FOVRNDET

FGTEWATERMRK

RESET 0000000000000100
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0x20

Table 2-21. FS Fields

BIT NAME DESCRIPTION

31:12 /// Reserved Reading returns 0. Write the reset value.

Write Pointer FIFO Location Contains the index of the memory

11:8 WRPTR

7:4 RDPTR

3 FFF

2 FEMPTY

1 FOVRNDET

location in the result FIFO array where the ne xt measurement
result will be stored.

Read Pointer FIFO Location Contains the index to the location
in the result FIFO array where the next measurement result will be
read. Reads from the RR register increment this value.

FIFO Full

1 = FIFO is full
0 = FIFO is not full

FIFO Empty

1 = FIFO is empty
0 = FIFO is not empty

FIFO Overrun Status Bit This bit is 1 when the receive logic tries
to place data into the FIFO after it has been completely filled. When
new data is received, the FOVRNDET bit is asserted and the newly
received data is discarded. This process repeats for each time new
data is received, until at least one empty FIFO entry exists. When
FOVRNDET is set to 1, an interrupt request is generated.

1 = Logic tried to place data into a full receive FIFO and is
0 = FIFO has not experienced an overrun

FIFO at Watermark

0 FGTEWATERMRK

1 = FIFO is at or above watermark level
0 = FIFO has fewer entries than the watermark level

requesting an interrupt

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.10 Control Bank Registers

The Control Bank is a set of 32 16-bit registers. The contents of the registers controls the
switches for the ADC. These registers are typically configured once at startup, dictated by
the physical system. HWCTRLBx and LWCTRLBx are used together and follow the format
of the HW and LW Registers (see Section 2.2.2.1 and Section 2.2.2.2).

HWCTRLB0 (Tag 0b0000 of the High Word Control Bank) contains 16 bits of data for the
4WX (4 wire touch screen, X direction) conversion. The remaining 14 bits of data for the
4WX conversion is in LWCTRLB0 (Tag number 0b0000 of the Low Word Control Bank).
Bits 15 and 14 of the low words are reserved and read as zero. The same logic is used
for 4WY (4 wire touch screen, Y direction).

The same logic is used for the Control Bank Registers HWCBx and LWCBx. The High
Word Registers should contain:

• The settling time

• The In+ bits

• The In- bits

• The Ref+ bits.
The Low Word Registers should contain:

• The bias control settings

• The Ref- bits.
At the end of any given conversion, a 4-digit Tag Number is stored in the FIFO along with

the corresponding 10-bit output of the ADC.
For internal access into the control bank, the data writes to the registers from the APB

data bus. Each entry is a 16-bit register, with its own address space. Table 2-22 shows
sample entries for the Control Bank. More details, and examples can be found in SHARP’s
Application Note ‘Using the Sharp ADC with Resistive Touch Screens’, available at
http://www.sharpsma.com.

Table 2-22. Sample Entries for Control Bank

TAG TYPE TAG NAME CONTENTS

4WX HWCBx0 Settling Time[15:7] In+ [6:3] In- [2] Ref+ [1:0]
4WY HWCBx1 Settling Time[15:7] In+ [6:3] In- [2] Ref+ [1:0]

HWCBx2...HWCBx15
4WX LWCBx0 Bias control[13:2] Ref- [1:0]
4WY LWCBx1 Bias Control[13:2] Ref- [1:0]

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.2.2.11 Idle High Word Register (IHWCTRL)

IHWCTRL is the high word of the Idle Register. The active bits used in this register are
Read/Write.

This register specifies the idle setting time and the inputs connected to th e ADC during the
Idle state. This register is used with the ILWCTRL Register (see Section 2.2.2.12).

Table 2-23. IHWCTRL Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD SETTIME_ID INP_ID

RESET 0000000000000000
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFC3000 + 0xA4

REFP_ID

INM_ID

Table 2-24. IHWCTRL Fields

BIT NAME DESCRIPTION

31:16

15:7 SETTIME_ID

6:3 INP_ID

2 INM_ID

/// Reserved Reading returns 0. Write th e re se t valu e.

Idle Settling Time Specifies the delay, in ADC clock cycles, from when
the state machine enters the Idle state t o when the Pen Interrupt signal
can be activated. Prevents spurious trigger of Pen Inter rupt while analo g
signals set up by the IDLE Register are settling.

Idle In+ Mux Specifies the connection to the positive input of the ADC
during Idle Mode. See Table 2-4.

Idle In- Mux Specifies the connection to the negative input of the ADC
during Idle Mode.

1 = GND
0 = Ref-

Idle Ref+ Mux Specifies the connection to the positive reference of t he
ADC during Idle Mode.

1:0 REFP_ID

00 = VREF+
01 = AN0/UL/X+
10 = AN2/LL/Y+
11 = AN8

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.12 Idle Low Word Register (ILWCTRL)

ILWCTRL is the low word of the Idle Register. The active bits used in this register are
Read/Write.

This register specifies the inputs connected to the ADC during the Idle state. This reg ister
is used with the IHWCTRL Register (see Section 2.2.2.11).

Table 2-25. ILWCTRL Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// BIASCON_ID REFM_ID
RESET 0000000000000000
RW RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW
ADDR 0xFFFC3000 + 0xA8

Table 2-26. ILWCTRL Fields

BIT NAME DESCRIPTION

31:14 /// Reserved Reading returns 0. Write the reset value.

Idle Bias Control These bits turn the FETs on and off, as shown in

13:2 BIASCON_ID

1:0 REFM_ID

IMPORTANT: Bits 9-11 must always be written as 0b000. Writing a 1 to any of these three bits can cause

unpredictable results.

Figure 2-2. The bit number corresponds to the FET number in the figure.
1 = FET on

0 = FET off
Idle Ref- Mux Specifies the connection to the negative reference of

the ADC during Idle Mode.
00 = VREF-

01 = AN1 (UR/X-)
10 = AN3 (LR/Y-)
11 = AN9

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LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector

2.2.2.13 Masked Interrupt Status Register (MIS)

MIS is the Masked Interrupt Status register. This Read Only register gives the masked
value of each interrupt. The BROWNOUT, PENSYNC, and EOS interrupts are latched and
must be cleared by writing to the Interrupt Clear (IC) register. The FWATER and FOVRN
interrupts are cleared when the contents of the FIFO no longer exceed their thresholds.

Table 2-27. MIS Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

EOSINTR

PENSYNC

BROWNOUT

RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFC3000 + 0xAC

FWATERINTR

FOVRNINTR

Table 2-28. MIS Fields

BIT NAME DESCRIPTION

31:5 /// Reserved Reading returns 0. Write the reset value.

Brown-Out Interrupt Status

4 BROWNOUT

3 PENSYNC

2 EOSINTR

1 FWATERINTR

0 FOVRNINTR

1 = Brown-out Interrupt is asserted
0 = Brown-out Interrupt is not active or not enabled

Pen Interrupt Status

1 = Pen Interrupt is asserted
0 = Pen Interrupt is not active or not enabled

End-of-Sequence Interrupt Active

1 = EOSIA Interrupt is asserted
0 = EOSIA Interrupt is not active or not enabled

FIFO Watermark Interrupt Active

1 = FIFO Watermark Interrupt is asserted
0 = FIFO Watermark Interrupt is not active or not enabled

FIFO Overrun Interrupt Active

1 = FIFO Overrun Interrupt is asserted
0 = FIFO Overrun Interrupt is not active or not enabled

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Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide

2.2.2.14 Interrupt Clear Register (IC)

IC is the Interrupt Clear Register. Bits [2:0] of this Write Only register correspond to the
three latched interrupts.Writing a 1 to a bit clears the corresponding interrupt; writing a 0
to a bit has no effect. This register is self-clearing.

Table 2-29. IC Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET ————————————————
RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

RESET ————————————————
RW WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
ADDR 0xFFFC3000 + 0xB0

NOTE: The reset value of this register’s bits is indeterminate.

BOIC

PENIC

EOSINTC

Table 2-30. IC Fields

BITS NAME DESCRIPTION

31:3 /// Reserved Reading returns 0. Write the reset value.

Brown-Out Interrupt Clear

2BOIC

1 PENIC

0EOSINTC

1 = Clears BROWNOUTINTR.
0 = Do not clear BROWNOUTINTR

Pen Interrupt Clear

1 = Clears PENIRQ
0 = Do not clear PENIRQ

End of Sequence Interrupt Clear

1 = Clears EOSINTR
0 = Do not clear EOSINTR

2-26 Version 1.0

Chapter 3

1

Boot Controller

The Boot Controller is the same for both the LH79524 and LH79525. All references in this
chapter apply to both devices.

The Boot Controller provides a glueless interface to external NAND Flash devices and
support for memory-mapped peripherals or NAND flash devices when performing AHB
burst read accesses of undetermined length.

By monitoring external boot pins at power-on reset, the Boot Controller supports:

• Booting from 8-, 16-, or 32-bit memory

• Configuration of the byte-lane boot state for nCS1

• Booting from alternate external devices (e.g., NAND Flash, UART, I
Figure 3-1 shows the Boot Controller block diagram.

2

C).

ADVANCED
PERIPHERAL
BUS (APB)

AMBA

INTERFACE

APB

REGISTER

BLOCK

FROM AHB

DECODER

PC[7:4] EXTERNAL

AHB

CONTROL

ADDRESS and

CONTROL

EXTERNAL

PERIPHERAL

INTERFACE

CONTROL

nCS1

OVERRIDE

BOOT

CONTROL

NAND

FLASH

CONTROL

AHB

CONTROL

TO nCS1
TO BOOT ROM

BOOT

CONTROL

NAND FLASH:
nFRE, nFWE

Figure 3-1. Boot Controller Block Diagram

Version 1.0 3-1

LH79525-6

Boot Controller LH79524/LH79525 User’s Guide

3.1 Theory of Operation

The Boot Controller is a slave module that connects to the APB. It provides hardware sup­port for configuring the External Memory Controller (EMC) interface on power-up, and
allows multiple boot devices and scenarios to be used in different applications. The Boot
Controller employs no error checking other than that specified by a protocol, if applicable,
and does not utilize the MMU or caches.

Booting can occur from one of several devices. The Boot Controller reads the status of
Port C and determines the type of device from which the code will be transferred. Once
the device and location is determined, the Boot Controller reads exactly 4KB (small-block
devices, I
it at physical address 0x60000000. Finally, the Boot Controller transfers control to that
code by setting the Program Counter to 0x60000000 and removes the Boot ROM from the
memory map (the Boot ROM is only visible in the memory map immediatly following reset).

When using small-block devices, the Boot Controller transfers 4KB of code from the bo ot
device. With large-block devices, the Boot Cont roller transfe rs 1KB. This is becaus e
large-block devices send an ECC value at the end of each page, which would corrupt
the code stream.

2

C, or UART) or 1KB (large-block devices) of code from that location and stores

When using either type device, but especially with large-block devices, larger amounts of
boot code can be loaded by writing a bootstrap loader for the initial code, which would then
execute and transfer the balance of the boot code to internal SRAM.

3.1.1 Boot Device Determination

The Boot Controller determines type and location of an external non-volatile device from
which boot code will be loaded for SoC core execution. This location must be within the
nCS1 chip select domain for all devices but NAND Flash.

The booting process is controlled by the initial values of PC[7:4]. The value on these pins at
power-up determines the boot device, data bus width, and configuration of control signals.

The Boot Controller then configures the External Memory Controller for proper accesses.
Table 3-1 lists the configuration ONLY for version A.0 of the SoC. For versions A.1 and
later, refer to Table 3-2.

3-2 Version 1.0

LH79524/LH79525 User’s Guide Boot Controller

Table 3-1. Boot Configuration for Silicon Version A.0

PC[7:4] DEVICE TYP E DATA BUS WIDTH CONTROL

0x0 NOR Flash or SRAM 16-bit nBLEx LOW for Reads
0x1 NOR Flash or SRAM 16-bit nBLEx HIGH for Reads
0x2 NOR Flash or SRAM 8-bit nBLEx LOW for Reads
0x3 NOR Flash or SRAM 8-bit nBLEx HIGH for Reads
0x4 NAND Flash (Small Block) 8-bit 3-byte Address
0x5 NAND Flash (Small Block) 8-bit 4-byte Address
0x6 NAND Flash (Small Block) 8-bit 5-byte Address
0x7 NAND Flash (Small Block) 16-bit 3-byte Address
0x8 NOR Flash or SRAM 32-bit nBLEx LOW for Reads
0x9 NOR Flash or SRAM 32-bit nBLEx HIGH for Reads
0xA RESERVED RE SERVED RESERVED
0xB RESERVED RE SERVED RESERVED
0xC NAND Flash (Small Block) 16-bit 4-byte Address
0xD NAND Flash (Small Block) 16-bit 5-byte Address
0xE RESERVED RE SERVED RESERVED
0xF RESERVED RESERVED RESERVED

Table 3-2. Boot Configuration for Silicon Version A.1

PC[7:4] DEVICE TYP E DATA BUS WIDTH CONTROL

0x0 NOR Flash or SRAM 16-bit nBLEx LOW for Reads
0x1 NOR Flash or SRAM 16-bit nBLEx HIGH for Reads
0x2 NOR Flash or SRAM 8-bit nBLEx LOW for Reads
0x3 NOR Flash or SRAM 8-bit nBLEx HIGH for Reads
0x4 NAND Flash (Small Block) 8-bit 3-byte Address
0x5 NAND Flash (Small Block) 8-bit 4-byte Address
0x6 NAND Flash (Large Block) 8-bit 4/5-byte Address
0x7 NAND Flash (Small Block) 16-bit 3-byte Address
0x8 NOR Flash or SRAM 32-bit nBLEx LOW for Reads
0x9 NOR Flash or SRAM 32-bit nBLEx HIGH for Reads
0xA RESERVED RESERVED RESERVED
0xB RESERVED RESERVED RESERVED
0xC NAND Flash (Small Block) 16-bit 4-byte Address
0xD NAND Flash (Large Block) 16-bit 4/5-byte Address
0xE I
0xF UART — —

2

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Version 1.0 3-3

Boot Controller LH79524/LH79525 User’s Guide

3.1.1.1 NAND Flash Operation

When NAND Flash is detected as the boot code source, the Boot Controller forces an over­ride of nCS1. Instead, the Boot ROM is selected for the locations in the memory map
where nCS1 is normally selected and the Boot Rom code is executed. The Boot ROM cod e
manages the interface to the NAND Flash device. The nCS1 override can be disabled by
writing a 0 to the nCS1 Override Control bit in the CS1OV register.

The Boot Controller generates the control signals on the nFRE and nFWE pins for external
NAND Flash. nFRE is the active LOW signal to the NAND flash Read Enable pin. This sig­nal is the External Memory Controller's nOE, enabled by the signal on external address pin
A23. Note that the LH79524/LH79525 memory controller automatically indexes address
signals on the address pins, depending on the width of the memory devices. For example,
with 8-bit addressing, the A0 signal is presented on pin A0, and the A23 signal is presented
on pin A23. For 16-bit memory, the memory controller automatically shifts the address one
bit to the right so that all addresses fall on half-word boundaries. In this configuration, sig­nal A1 is presented on pin A0, and pin A23 carries the A24 signal. Similarly, for 32-bit
devices, A2 appears on pin A0, and A25 appears on pin A23. For more information on
booting from NAND Flash, refer to Section 7.3.1 and Section 7.3.2.

nFRE is only active (i.e., LOW) when nOE is LOW and the A23 signal (for 8-bit), A24 signal
(for 16-bit), or A25 (for 32-bit) is HIGH. nFWE is the active LOW signal to the NAND flash
Write Enable pin. This signal is the External Memory Controller's nWE signal, enabled by
address signal A23/A24/A25. nFWE is only active (i.e., LOW) when nWE is LOW and
A23/A24/A25 is HIGH. Gating these signals allows normal memory and I/O accesses to
other external devices to occur during extended NAND Flash accesses (when chip select
is held active). These other devices must be mapped to external memory regions where
the address signals are LOW.

3.1.2 Hardware Design Considerations

Using the Boot Controller dictates certain hardware considerations, especially when boot­ing from NAND Flash.

3.1.2.1 Active Pullups To Signal Boot Mode

The boot mode — NOR Flash, NAND Flash, SRAM, I2C, or UART — is selected by the
value latched on the rising edge of the nRESETIN signal from the state of PC[7:4],
shown in Table 3-1 and Table 3-2. PC[7:6] are used during NAND Flash booting as control
signals, but PC[5:4] have no other use following the end of reset. Therefore, those two
GPIO pins can be used during normal operation if an active pullup is used, gated by the
nRESETOUT signal.

Figure 3-2 shows a schematic representation of one active pullup circuit. One circuit is
required for each PCx pin to be pulled high during reset. nRESETOUT is presented to the
Gate (pin 1) of the P-Channel FET. When active (LOW), nRESETout causes the transistor
to turn on, and pull the PCx input HIGH. When nRESETOUT transitions from LOW to HIGH
at the end of the reset period, the value on PC[7:4] is latched and the FET is turned off, thus
allowing those pins to be used for general purpose I/O or as address pins A[21:20].

3-4 Version 1.0

LH79524/LH79525 User’s Guide Boot Controller

+3.3 V

120 Ω

BSS84

32

LH79524/ LH79525

PCx

1

BSS84

32

1

nRESETOUT

PCy

LH79525-104

Figure 3-2. Active Pullup Circuit

3.1.2.2 NAND Flash Hardware Design

The additional NAND Flash control signals are multiplexed with Address lines. Table 3-3
shows the alternate pin functions when using NAND Flash devices.

These alternate pin functions must be considered when designing external interfaces. Fur­ther, the actual address signals presented on the A22, A23, A3 (ALE), and A4 (CLE) pins
are determined by the memory width being addressed, as described in Section 3.1.2.

The A[4:3] address pins must be written with the correct address to make the ALE and CLE
signals TRUE for the given transaction. These address values differ depending on the
NAND Flash device width being used.

Table 3-3. Alternate Pin Function During NAND Flash Booting

PIN

PRIMARY

FUNCTION

PC6/A22/nFWE PC6 A22 nFWE
PC7/A23/nFRE PC7 A23 nFRE

A3 A3* N/A ALE
A4 A4* N/A CLE

nCS0 nCS0 N/A nCE

NOTE: Pins A3 and A4 carry different address signals depending on the width of the memory device. For 8-

bit devices, Pin A3= Address signal A3; Pin A4= Address signal A4. For 16-bit devices, Pin A3=
Address signal A4; Pin A4= Address signal A5. For 32-bit devices, Pin A3= Address signal A5; Pin
A4= Address signal A6. See Section 3.1 and Chapter 7: External Memory Controller.

SECONDARY

FUNCTION

NAND BOOT

FUNCTION

Version 1.0 3-5

Boot Controller LH79524/LH79525 User’s Guide

3.1.2.2.1 NAND Flash Chip Select

Because of the hardware implementation of the NAND Flash signalling, the LH79524/
LH79525 chip select used for NAND Flash addressing must be nCS0 for booting; nCS1
cannot be used. Connect the nCS0 pin to the NAND Flash nCE input pin if that device is
used for booting. If the NAND Flash is not used for booting, it can be located in any chip
select domain.

3.1.3 Booting Using the I2C Interface

Booting can also be done using the I2C interface. When booting from I2C, the device
address that must be used is 0b1010000x. This address is not alterable. The Boot Con­troller will always boot exactly 4Kbytes when using the I2C serial EEPROM.

Interface parameters are shown in Table 3-4 and the list of supported devices is shown
in Table 3-5.

Table 3-4. Boot Parameters for I

PARAMETER VALUE

Communication Speed 400 kHz
Mode of SoC Master Mode
Addressing Mode 7 bit

2

I

C EEPROM Configuration

Slave, addressed at 0b1010000x, where x=0 for Writes and
x=1 for Reads

Table 3-5. Supported Devices

DENSITY ATMEL ST MICRO MICROCHIP

32Kbit (4K × 8) AT24C32 M24C32 24xx32
64Kbit (8K × 8) AT24C32 M24C64 24xx64
128Kbit (16K × 8) AT24C32 M24128 24xx128
256Kbit (32K × 8) AT24C32 M24256 24xx256
512Kbit (64K × 8) AT24C32 M24512 24xx512
1Mbit (128K × 8) AT24C32 N/A N/A

2

C

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LH79524/LH79525 User’s Guide Boot Controller

3.1.4 Booting from UART

Another boot option is to boot using UART0. The transfer protocol implementation is
XMODEM with 128-byte packets. All UART0 parameters are summarized in Table 3-6.

The Boot Controller automatically handles initialization and setup of UART0; the source of
the boot code must be compatible with the parameters in the table.

Table 3-6. UART0 Boot Parameters

PARAMETER VALUE

Protocol XMODEM Checksum
Bit Rate 115 kbps
Data Bits 8
Parity None
Stop Bits 1
Packet Size 128 bytes

3.2 Register Reference

This section provides the Boot Controller register memory mapping and bit fields.

3.2.1 Memory Map

The base address for the Boot Controller is 0xFFFE6000. Table 3-7 summarizes the Boot
Controller registers.

Table 3-7. Boot Controller Register Summary

ADDRESS OFFSET NAME DESCRIPTION

0x00 PBC Power-up Boot Configuration Register
0x04 CS1OV nCS1 Override Register
0x08 EPM External Peripheral Mapping Register

Version 1.0 3-7

Boot Controller LH79524/LH79525 User’s Guide

3.2.2 Register Definitions

3.2.2.1 Power-up Boot Configuration Register (PBC)

Reading from the PBC register returns the value that the PC[7:4] pins were driven during
a power-on reset. This value is used by software contained in the Boot ROM, as well as
the Boot Controller, to determine the type and configuration of the external device from
which the CPU is to boot.

Table 3-8. PBC Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD /// PBC
RESET 000000000000 PC[7:4]
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ADDR 0xFFFE6000 + 0x00

Table 3-9. PBC Fields

BITS NAME DESCRIPTION

31:4 /// Reserved Reading returns 0. Write the reset value.

3:0 PBC

Power-up Boot Configuration This field contains the value that the PC[7:4]
pins were driven during power-on reset.

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LH79524/LH79525 User’s Guide Boot Controller

3.2.3 nCS1 Override Register (CS1OV)

Bit 0 in the CS1OV register programs the function of the nCS1 signal. This bit has different
functions for read and write. Reading returns the nCS1 Override Enable current status.
Writing programs the nCS1 Override Control function.

During normal boot from the internal Boot ROM, CS1OV is programmed to 1 and PBC is
programmed to 0bX1XX, an override of nCS1 occurs and CS1O will read as 1, resulting
in the Boot ROM using nCS1 as chip select. This override can be disabled by writing a 0
to CS1O, causing CS1O to read as 0.

If on system reset the boot configuration is set to 0bX0XX, nCS1 remains mapped as
described above, CS1O has no effect on the memory map and CS1O will reads as 0.

The very last thing Boot ROM software should do bef ore returning control to the operating
system is to write a 0 to this register so that normal routing of the nCS1 signal occurs.

Table 3-10. CS1OV Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

RESET 000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW

ADDR 0xFFFE6000 + 0x04

NOTE: *Resets to the value to which PC[6] is externally driven during po wer-on reset.

Table 3-11. CS1OV Fields

BITS NAME DESCRIPTION

31:1 /// Reserved Reading returns 0. Write the reset value.

Read: nCS1 Override Enable

1 = nCS1 override is enabled. The override only occurs when PBC[3] = 1 and

CS1O is programmed to 1.

0CS1O

0 = nCS1 override is disabled; nCS1 is routed for normal operation

Write: nCS1 Override Control

1 = enable nCS1 override
0 = disable nCS1 override

CS1O

*

Version 1.0 3-9

Boot Controller LH79524/LH79525 User’s Guide

3.2.4 External Peripheral Mapping Register (EPM)

This register determines which chip selects will have burst accesses to their address
regions converted to a series of non-sequential transfers. The register provides individual
selectability for each of nCS0, nCS1, nCS2, and nCS3. At reset, accesses to all four chip
select regions have conversion enabled. This ensures that all external devices will be
accessible following reset.

Table 3-12. EPM Register

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIELD ///
RESET 0000000000000000
RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIELD ///

CS3EP

CS2EP

CS1EP

CS0EP

RESET 0000000000001111
RW RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW
ADDR 0xFFFE6000 + 0x08

Table 3-13. EPM Fields

BITS NAME DESCRIPTION

31:4 /// Reserved Reading returns 0. Write the reset value.

nCS3 Configured for External Peripherals

3 CS3EP

2 CS2EP

1 CS1EP

0 CS0EP

1 = All burst accesses to nCS3 are converted to a series of non-sequential single

transfers.

0 = Accesses to nCS3 are unaltered.

nCS2 Configured for External Peripherals

1 = All burst accesses to nCS2 are converted to a series of non-sequential single

transfers.

0 = Accesses to nCS2 are unaltered.

nCS1 Configured for External Peripherals

1 = All burst accesses to nCS1 are converted to a series of non-sequential single

transfers.

0 = Accesses to nCS1 are unaltered.

nCS0 Configured for External Peripherals

1 = All burst accesses to nCS0 ar e converted to a series of non-seque ntial single

transfers.

0 = Accesses to nCS0 are unaltered.

3-10 Version 1.0

Chapter 4

Color Liquid Crystal Display Controller

This chapter discusses the Color LCD Controller (CLCDC) and its Advanced LCD Interface
Peripheral (ALI) for AD-TFT, HR-TFT panels, and any technology of panel compatible with
this signal system. The ALI-specific description begins in Section 4.4. The only difference
between the LH79524 CLCDC and the LH79525 CLCDC is the pixel bit depth. The LH79524
supports up to 16 bits-per-pixel (bpp) depth, and the LH79525 supports up to 12 bpp.

4.1 Introduction

The CLCDC provides all necessary control and data signals to interface the SoC directly
to a variety of color and monochrome LCD panels, including STN and TFT panels. The ALI
modifies the CLCDC output to allow the chip to connect directly to the Row and Column
driver chips on superthin panels, including AD-TFT, HR-TFT, or any panel that supports
this method of connection. Figure 4-1 shows a simplified diagram of the two controllers
connected to the AHB, to the APB, and to each other.

ADVANCED
HIGH-PERFORMANCE
BUS (AHB)

COLOR LCD

CONTROLLER

ADVANCED LCD

INTERFACE

LCD PANEL

Figure 4-1. LH79524/LH79525 LCD System, Simplified Block Diagram

ADVANCED
PERIPHERAL
BUS (APB)

INTERNAL

TO THE

LH79524/LH79525

EXTERNAL

TO THE

LH79524/LH79525

LH79525-46

Version 1.0 4-1

Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide

4.1.1 LCD Panel Architecture

Modern technology panels, including AD-TFT and HR-TFT panels, are t hinner than ever .
To achieve maximum space savings, they are manufactured without the large ASICs and
DC-DC converter blocks built into STN and TFT panels. See Figure 4-2.

The ASIC in STN and TFT panels decodes input data into Row and Column information
and builds the timing signals. It supplies this information to the panel’s Row and Column
driver chips to set the proper pixels at the proper intensity and at the proper times. The
DC-DC converter runs the panel’s power supplies and illuminator. Including these devices
in STN and TFT panels, however, comes at the cost of bulk and weight.

The ALI eliminates the need for a separate Timing ASIC, since it is able to drive the panel’s
Row and Column driver chips directly. The DC-DC conversion is also handled off-panel,
by a separate device operating the panel’s high voltage supplies and illuminator. The
DC-DC conversion must be handled by a separate device, since the LH79524/LH79525
do not supply this function.

Unless the behavior is different, this User’s Guide uses the term TFT to discuss all types
of TFT panels whether the panel requires timing support from the ALI or not.

DISPLAY
SIGNALS

TIMING

ASIC

DC/DC

CONVERTER

LCD PANEL ASSEMBLY

ROW TIMING

COLUMN TIMING

Figure 4-2. Block Diagram of a Typical Advanced LCD Panel

LCD
PANEL
GLASS

79525-48

4-2 Version 1.0

LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller

4.2 CLCDC Features

• Supported LCD Panels
– Active-matrix TFT, HR-TFT and AD-TFT panels, with up to 16-bit bus interface

(LH79524) or 12-bit bus (LH79525)
– Single-panel monochrome STN panels, with 4-bit and 8-bit bus interfaces
– Dual-panel monochrome STN panels, with 4-bit and 8-bit bus interface per panel
– Single-panel color STN panels, with an 8-bit bus interface (LH79524 only)
– Dual-panel color STN panels, with 8-bit bus interface per panel (LH79524 only)

• Resolution up to 1024 × 1024 dots per inch (DPI)

• Additional Features
– Programmable timing for different display panels
– 256-entry, 16-bit palette RAM physically arranged as a 128 × 32-bit RAM
– AC bias signal for TFT panels and a data-enable signal for TFT panel

The following parameters can be programmed in the CLCDC:

• Horizontal front and back porch width

• Horizontal synchronization pulse width

• Number of pixels per line

• Vertical front and back porch width

• Vertical synchronization pulse width

• Number of horizontal lines per panel

• Number of panel data clocks per line

• Programmable signal polarities, active HIGH or active LOW

• AC panel bias

• Panel data clock frequency (LCDDCLK)

• Bits-per-pixel

• Little-endian, big-endian, and WinCE

• Interrupt generation.

4.3 Theory of Operation

The CLCDC is an AMBA master-slave module that connects to the AHB. Figure 4-3
is a detailed block diagram of the CLCDC. Packets of pixel-coded data are sent, via the
AHB interface, to two independently programmable, 32-bit-wide DMA FIFOs. Each FIFO
is 16 words deep by 32 bits wide. In Single Panel STN Mode, the LCD DMA FIFOs a ppear
as a single FIFO of twice the size. The buffered pixel-coded data is then unpacked via a
pixel serializer.

TM

data formatting

Version 1.0 4-3

Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide

CLOCK

LCD PANEL

PANEL

CLOCK

GENERATOR

CONTROL

LCD PANEL

TIMING

CONTROLLER

UPPER

STN DATA

PANEL

UPPER

PANEL

UPPER

FIFO

OUTPUT

FORMATTER

LCD

GRAY

PANEL

DATA

DATA

SELECT

STN/TFT

LOWER

SCALER

STN

DATA

LOWER

LOWER

PANEL

OUTPUT

PANEL

FORMATTER

FIFO

LH79525-37

INTERRUPTS

INTERRUPT

GENERATION

TFT DATA

AND

CONTROL

CLCDCLK

AHB

STATUS

REGISTER

SLAVE

INTERFACE

DMA

FIFO

PANEL

UPPER

ADVANCED HIGH

PERFORMANCE

BUS (AHB)

PALETTE

(128 × 32)

PIXEL

SERIALIZER

FIFO

INPUT

CONTROL

AHB

MASTER

INTERFACE

PANEL

LOWER

DMA

FIFO

Figure 4-3. Color LCD Controller Block Diagram

AHB ERROR

FIFO UNDERFLOW

4-4 Version 1.0