Sharp LH532400D Datasheet
LH5324000
CMOS 24M (3M × 8) MROM
FEATURES
•• 3,145,7 28 × 8 bi t organ izatio n
•• Access time: 150 ns (MAX.)
•• Supply curre nt :
– Operating: 65 mA (MAX.)
– Standby: 100 µA (MAX.)
•• TTL compatible I/O
•• Three-state output
•• Single +5 V Power supply
•• Static operation
•• When the address in put at both A
19
an d
A
20
is high leve l , outputs become high
impedan ce irresp ectiv e o f CE o r OE.
•• Package:
42-pi n , 600 -mil DIP
•• Others :
– Non programmab le
– Not de sign ed o r rate d as rad iatio n
hardene d
– CMOS process (P typ e sil icon
substrate)
DESCRIPTION
The LH53 24000 i s a 24M-bit CMOS mask-programmable ROM organized as 3,145,728 × 8 bits. It is
fabricated using silico n-gate CMOS process technology.
PIN CONNECTIONS
532400-1
TOP VIEW
2
3
4
5
8
9
A
2
A
5
39
38
37
36
35
34
31
28
A
7
A
6
6
7A
3
A
4
33
32
A
10
A
11
A
13
A
15
GND
NC
10
11
12
41
40 A
9
A
1
13 30 A
-1
29 D
7
OE
A
0
CE
A
12
42-PIN DIP
14
15
16
17
18
19
20
21
25
22
27
26
24
23
NC
D
5
NC
D
4
D
2
NC
NC
GND
NC
D
1
D
0
D
3
NC V
CC
A
8
A
14
A
16
D
6
421
A
17
A
18
A
19
A
20
Figure 1. Pin Connecti ons
1
532400-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(3,145,728 x 8)
SENSE AMPLIFIER
GND
A
5
A
13
ADDRESS BUFFER
A
0
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
A
15
TIMING
GENERATOR
A
16
A
-1
DATA SELECTOR/OUTPUT BUFFER
OE
BUFFER
ADDRESS
BUFFER
OE
CE
A
17
A
19
A
18
A
20
37
38
39
40
4
7
8
9
3
6
41
5
36
10
35
34
33
2
42
1
32
11
13
30
22
31
12
D
3
D
2
D
1
D
7
D
6
D
4
D
5
D
0
25
18
16
14
20
29
23
27
Figure 2. LH5324000 Block Diagram
PIN DESCRIPTION
SIGNA L PIN NAME
A-1 - A
20
Addr ess in put
D
0
- D
7
Data ou tput
CE
Chip en abl e in pu t
OE Outp ut e nab le inp ut
SIGNAL PIN NAME
V
CC
Power pi n (+ 5 V)
GND
Groun d
NC
No co nne cti on
LH5324000 CMOS 24M (3M x 8 ) MROM
2
Loading...