LH5116/H
CMOS 1 6K (2 K × 8) S tatic RA M
FEATURES
•• 2,048 × 8 bit orga niza ti on
•• Access time: 100 ns (MAX.)
•• Power consu mption :
Operating : 22 0 mW (MAX.)
Standb y: 5.5 µW (MAX.)
•• Single +5 V p owe r su ppl y
•• Fully-static operatio n
•• TTL compatible I/O
•• Three-state outputs
•• Wide temp erature ra nge a vail able
LH5 116H: -40 to +8 5°C
•• Packa ges:
24-pi n , 600 -mil DIP
24-pi n , 300 -mil SK-DIP
24-pi n , 450 -mil S OP
DESCRIPTION
The LH51 16/H are static RAM s organized as 2,048 × 8
bits. It is fabri cated using silicon-gate C MOS process
technology. It features high speed access in read m ode
using output enable (tOE).
PIN CONNECTIONS
24-PIN DIP
24-PIN SK-DIP
24-PIN SOP
A
A
A
A
A
A
A
I/O
I/O
I/O
GND
Vcc
1
7
2
6
3
5
4
4
5
3
6
2
A
7
1
8
0
9
1
10
2
11
3
12
24
23
22
20
19
18
17
16
15
14
13
21
A
A
WE
OE
A
CE
I/O
I/O
I/O
I/O
I/O
TOP VIEW
8
9
10
8
7
6
5
4
5116-1
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1
LH5116/H CMOS 16K (2K × 8) Static RAM
8
A
0
3
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
A
2
6
A
1
7
23
A
8
A
22
9
19
10
9
1
10
2
11
3
13
4
14
5
15
6
16
7
17
8
BUFFERS
ROW ADDRESS
CE
ROW DECODERS
DATA CONTROL
MEMORY CELL
ARRAY
(128 x128)
COLUMN
I/O CIRCUIT
COLUMN DECODERS
COLUMN ADDRESS
BUFFERS
CE
24
12
V
CC
GND
CE
18
21
WE
20
OE
5
4
A
4A3A2A1
6
Figure 2. LH5116/H Block Diagram
PIN DESCRIPTION
SIGNA L PIN N AME
A0 - A
10
Addre ss input
CE Ch ip Ena ble in put
OE Ou tpu t E nab le inp ut
WE Wri te E na ble inp ut
SIGNAL PIN NAME
I/O1 - I/O
V
GND Ground
TRUTH TABLE
CE OE WE MODE I/O1 - I/O
L X L Write D
L L H Read D
IN
OUT
H X X Deselect High-Z Standby (I
L H X Outputs disable High-Z Operating (I
NOTE:
1. X = H or L
SUPPLY CURRENT NOTE
8
7
Data i npu t/o utp ut
8
CC
Power sup ply
Operating (ICC) 1
Operating (ICC)
)1
SB
)1
CC
5116-2
2
CMOS 16K (2K × 8) Static RAM LH5116/H
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Suppl y v olt age
Input vol tage V
V
CC
IN
Operat ing te mpe ratu re Topr
Storage temperature Tstg -55 to +150
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. Applied to the LH5116/D/NA
3. Applied to the LH5116H/HD/HN
-0.3 to +7.0 V 1
-0.3 to VCC + 0.3 V 1
0 to +70
-40 to +85 3
°C
°C
2
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN. TYP . MAX. UNIT
Suppl y v olt age V
Input vol tage
NOTE:
1.
T
= 0 to 7 0°C (LH5116/D/NA), TA = -40 to +85 °C (LH5116H/HD/HN)
A
CC
V
IH
V
IL
4.5 5.0 5.5 V
2.2 VCC + 0.3 V
-0.3 0.8 V
1
DC CHARACTERISTICS 1 (VCC = 5 V ±10%)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Output ‘L OW’ v olta ge V
Output ‘H IGH ’ vol tage V
Input lea kag e c urr ent
Output le aka ge cur ren t I
Operat ing cu rre nt
Standb y c urr ent I
NOTES:
1.
T
= 0 to 7 0°C (LH5116/D/NA), TA = -40 to +85 °C (LH5116H/HD/HN)
A
CE = 0 V; all other input pins = 0 V to V
2.
3. CE = VIL; all other input pins = VIL to V
4.
T
= 25°C
A
OL
OH
I
LI
LO
I
CC1
I
CC2
SB
All other input pins = 0 V to V
CC
IH
IOL = 2.1 mA 0.4 V
IOH = -1.0 mA 2.4 V
VIN = 0 V to V
CE = VIH, V
= 0 V to V
I/O
CC
CC
Outputs open (OE = VCC)2530mA2
Outputs open (OE = VIH)3040mA3
CE ≥ V
CC
- 0.2 V
-1.0 1.0 µA
-1.0 1.0
CC
µA
1.0
0.2 4
µA
AC CHARACTERISTICS
1
(1) READ CYCLE (VCC = 5 V ±10%)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read c yc le t ime t
Addres s a cc ess ti me t
Chip e nab le acc es s ti me t
Chip e nab le Low to ou tpu t in Lo w-Z t
Output en abl e a cce ss tim e t
Output en abl e L ow to o utp ut in Low -Z t
Chip d isa ble to ou tpu t i n Hi gh- Z t
Output disable to outp ut in High-Z t
Output ho ld time t
NOTES:
1.
T
= 0 to 7 0°C (LH5116/NA/D). TA = -40 to 8 5°C (LH5116H/HD/HN).
A
2.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition
from steady state levels into the test load.
RC
AA
ACE
CLZ
OE
OLZ
CHZ
OHZ
OH
100 ns
100 ns
100 ns
10 ns 2
40 ns
10 ns 2
040ns2
040ns2
10 ns
3
LH5116/H CMOS 16K (2K × 8) Static RAM
(2) WRITE CYCLE 1 (VCC = 5 V ±10%)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Write c ycl e t ime
Chip e nab le to end of wri te
Addres s v al id t ime
Addres s s etu p t ime t
Write p uls e w idt h t
Write re co ver y ti me t
Output ac tiv e f rom end of wri te t
WE Low to ou tpu t in Hi gh- Z t
Data v ali d t o e nd of w rit e t
Data h old ti me t
Output en abl e t o ou tpu t i n H igh -Z t
Output ac tiv e f rom end of wri te t
NOTES:
1.
T
= 0 to + 70 °C (LH5116/D/NA), TA = -40 to +85 °C (LH5116H/HD/HN)
A
2.
Active output to high-impedance and high-impedance to output active tests specified for a ±200 mV transition
from steady state levels into the test load.
t
WC
t
CW
t
AW
AS
WP
WR
OW
WHZ
DW
DH
OHZ
OW
100 ns
80 ns
80 ns
0ns
60 ns
10 ns
10 ns 2
030ns2
30 ns
10 ns
040ns2
10 ns 2
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude 0.8 V to 2.2 V
Input rise/fall time 10 ns
Timing re fer enc e l eve l 1.5 V
Output load condition 1TTL + C
NOTE:
1. In cludes scope and jig capacitance.
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Data r ete nti on v ol tag e V
Data r ete nti on c urr ent
Chip d isa ble to da ta
retent ion
Recov ery tim e t
NOTES:
1.
T
= 0 to +7 0 °C (LH5116/D/NA), TA = -40 to +85 °C (LH5116H/HD/HN)
A
2.
TA = 25°C
3. tRC = Read cycle time
CCDR
I
CCDR
t
CDR
R
(100 pF) 1
L
CE ≥ V
CE ≥ V
V
CCDR
CCRC
CCDR
= 2.0 V
- 0.2 V
- 0.2 V,
1
2.0 5.5 V
1.0
µA
0.2 2
0ns
t
RC
ns 3
CAPACITANC E 1 (f = 1 MHz, TA = 25°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. M AX. UNIT
Input cap acitan ce C
Input/ out put ca pac ita nce C
NOTE:
1. T his parameter is sampled and not production tested.
IN
I/O
4
VIN = 0 V 7 pF
V
= 0 V 10 pF
I/O
CMOS 16K (2K × 8) Static RAM LH5116/H
4.5 V
2.2 V
V
CCDR
A0 - A
V
CC
CE
0 V
D
10
CE
OE
OUT
t
CDR
DATA RETENTION MODE
CCDR
-0.2 V
CE ≥ V
Figure 3. Low Voltage Data Retenti on
t
RC
t
AA
t
ACE
t
OE
t
OLZ
t
CLZ
DATA VALID
t
R
5116-6
t
OH
t
CHZ
t
OHZ
NOTE: WE = "HIGH"
5116-3
Figure 4. Read Cycle
5
LH5116/H CMOS 16K (2K × 8) Static RAM
t
WC
A0 - A
10
t
(NOTE 3)
WP
WR
t
DH
.
t
OW
(NOTE 5)
(NOTE 6)
5116-4
t
AW
t
CW
CE
t
AS
t
WP
(NOTE 2)
WE
t
WHZ
(NOTE 4)
D
NOTES:
OUT
D
IN
OE = 'LOW'
t
DW
1. WE must be HIGH when there is a change in A0 - A10.
2. When CE and WE are both LOW at the same time, write occurs during the period t
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
WR
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
outputs data with the same logic level as the input data of this write cycle.
5. D
OUT
6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input
signals of opposite logic level must not be applied.
Figure 5. Write Cycle 1
t
WC
A0 - A
10
WP
t
DW
.
(NOTE 3)
t
WR
t
(NOTE 5)
t
DH
(NOTE 6)
OW
t
AW
OE
t
CW
CE
t
AS
t
WP
(NOTE 2)
WE
t
OHZ
D
OUT
(NOTE 4)
D
IN
NOTES:
1. WE must be HIGH when there is a change in A0 - A10.
2. When CE and WE are both LOW at the same time, write occurs during the period t
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
WR
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
outputs data with the same logic level as the input data of this write cycle.
OUT
6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input
signals of opposite logic level must not be applied.
t
OLZ
5116-5
Figure 6. Write Cycle 2
6
CMOS 16K (2K × 8) Static RAM LH5116/H
ACCESS TIME VS. SUPPLY VOLTAGE
1.2
1.1
(RELATIVE VALUE)
1.0
ACE
, t
AA
0.9
ACCESS TIME t
0.8
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE V
CC
AVERAGE SUPPLY CURRENT VS.
25
SUPPLY VOLTAGE
(mA)
CC
20
(V)
ACCESS TIME VS. AMBIENT TEMPERATURE
1.2
1.1
(RELATIVE VALUE)INPUT VOLTAGE V
1.0
ACE
, t
AA
0.9
ACCESS TIME t
0.8
0 25 50 75 100
AMBIENT TEMPERATURE T
AVERAGE SUPPLY CURRENT VS.
25
AMBIENT TEMPERATURE
(mA)
CC
20
A
(°C)
15
10
AVERAGE SUPPLY CURRENT I
5
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE V
INPUT VOLTAGE VS. SUPPLY VOLTAGE
2.5
(V)
2.0
IL
, V
IH
CC
1.5
1.0
INPUT VOLTAGE V
0.5
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE V
CC
(V)
(V)
15
10
5
0 25 50 75 100
AMBIENT TEMPERATURE T
A
(°C)
INPUT VOLTAGE VS.
2.5
(V) AVERAGE SUPPLY CURRENT I
2.0
IL
, V
V
IH
V
IL
IH
1.5
1.0
AMBIENT TEMPERATURE
V
IH
V
IL
0.5
0 25 50 75 100
AMBIENT TEMPERATURE T
A
(°C)
5116-7
Figure 7. Electrical Characteristic Curves
(VCC = 5 V, TA = 25°C unless otherwise specifi ed)
7
LH5116/H CMOS 16K (2K × 8) Static RAM
PACKAGE DIAGRAMS
24DIP (DIP024-P-0600)
24 13
112
31.30 [1.232]
30.70 [1.209]
2.54 [0.100]
TYP.
DIMENSIONS IN MM [INCHES]
0.60 [0.024]
0.40 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
13.45 [0.530]
12.95 [0.510]
4.45 [0.175]
4.05 [0.159]
5.30 [0.209]
4.90 [0.193]
3.45 [0.136]
3.05 [0.120]
0.51 [0.020] MIN
DETAIL
0° TO 15°
0.30 [0.012]
0.20 [0.008]
15.24 [0.600]
TYP.
24DIP-2
24SDIP (SDIP024-P-0300)
112
22.25 [0.876]
21.75 [0.856]
1.778 [0.070]
TYP.
DIMENSIONS IN MM [INCHES]
0.56 [0.022]
0.36 [0.014]
1324
0.51 [0.020] MIN
MAXIMUM LIMIT
MINIMUM LIMIT
24-pin, 600-mil DIP
6.55 [0.258]
6.15 [0.242]
3.65 [0.144]
3.25 [0.128]
4.40 [0.173]
4.00 [0.157]
3.45 [0.136]
3.05 [0.120]
DETAIL
0° TO 15°
0.30 [0.012]
0.20 [0.008]
7.62 [0.300]
TYP.
24SDIP
24-pin, 300-mi l SK-DIP
8
CMOS 16K (2K × 8) Static RAM LH5116/H
24SOP (SOP024-P-0450B)
1.27 [0.050]
0.50 [0.120]
0.30 [0.012]
24 13
TYP.
1.70 [0.067]
15.60 [0.614]
15.20 [0.598]
DIMENSIONS IN MM [INCHES]
121
0.15 [0.006]
MAXIMUM LIMIT
MINIMUM LIMIT
8.80 [0.346]
8.40 [0.331]
1.70 [0.067]
1.025 [0.040]
1.025 [0.040]
12.40 [0.488]
11.60 [0.457]
2.40 [0.094]
2.00 [0.079]
0.20 [0.008]
0.00 [0.000]
24-pin, 450-mil SOP
10.60 [0.417]
0.20 [0.008]
0.10 [0.004]
24SOP
9
LH5116/H CMOS 16K (2K × 8) Static RAM
ORDERING INFORMATION (TA = 0°C to 70°C)
LH5116
Device Type
X
Package
- ##
Speed
10 100 Access Time (ns)
Blank 24-pin, 600-mil DIP (DIP024-P-0600)
D 24-pin, 300-mil SK-DIP (DIP024-P-0300)
N 24-pin, 450-mil SOP (SOP024-P-0450B)
CMOS 16K (2K x 8) Static RAM
Example: LH5116N-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP)
ORDERING INFORMATION (TA = -40°C to +85°C)
LH5116H
Device Type
X
Package
- ##
Speed
10 100 Access Time (ns)
5116-8
Blank 24-pin, 600-mil DIP (DIP024-P-0600)
D 24-pin, 300-mil SK-DIP (DIP024-P-0300)
N 24-pin, 450-mil SOP (SOP024-P-0450B)
CMOS 16K (2K x 8) Static RAM
Example: LH5116HN-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP)
5116-9
10
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