Sharp LH28F320S3TD-L10 Datasheet

32 M-bit (2 MB x 8/1 MB x 16 x 2-Bank)

LH28F320S3TD-L10

DESCRIPTION

The LH28F320S3TD-L10 Dual Work flash memory
with Smart 3 technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through highly-optimized
page buffer operations. Its symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Its enhanced suspend capabilities
provide for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F320S3TD-L10 offers three levels of
protection : absolute protection with V
selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. LH28F320S3TD-L10 is conformed to the
flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.

FEATURES

• Smart 3 Dual Work technology
– 2.7 V or 3.3 V V
– 2.7 V, 3.3 V or 5 V VPP
– Capable of performing erase, write and read

for each bank independently (Impossible to
perform read from both banks at a time).

• High-speed write performance
– Two 32-byte page buffers/bank
– 2.7 µs/byte write transfer rate

• Common Flash Interface (CFI)
– Universal & upgradable interface

CC

PP at GND,

Smart 3 Dual Work Flash Memory

• Scalable Command Set (SCS)

• High performance read access time
– 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read

• Enhanced data protection features
– Absolute protection with V
– Flexible block locking
– Erase/write lockout during power transitions

• SRAM-compatible write interface

• User-configurable x8 or x16 operation

• High-density symmetrically-blocked architecture
– Sixty-four 64 k-byte erasable blocks

• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/bank

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc

in static mode

• Automated write and erase
– Command user interface
– Status register

TM

• ETOX

• Package

∗ ETOX is a trademark of Intel Corporation.

∗

– 56-pin TSOP Type I (TSOP056-P-1420)

LH28F320S3TD-L10

PP = GND

V nonvolatile flash technology

Normal bend

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

- 1 -

PIN CONNECTIONS

56-PIN TSOP (Type I)

(TSOP056-P-1420)

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC

BE

1L#

BE

1H#

A

20

A19
A18
A17
A16

VCC

A15
A14
A13
A12

BE0#

V

PP

RP#

A

11

A10

A9
A8

GND

A

7

A6
A5
A4
A3
A2
A1

WP#
WE#
OE#
STS
DQ

15

DQ7
DQ14
DQ6
GND
DQ

13

DQ5
DQ12
DQ4
VCC
GND
DQ

11

DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC

LH28F320S3TD-L10

TOP VIEW

- 2 -

BLOCK DIAGRAM

Y GATING

Y

DECODER

INPUT

BUFFER

OUTPUT
BUFFER

DQ0-DQ15

VCC

WE#
OE#
RP#
WP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE
VOLTAGE SWITCH

STATUS

REGISTER

COMMAND

USER

INTERFACE

MULTIPLEXER

WRITE
STATE

MACHINE

DATA

REGISTER

DATA

REGISTER

OUTPUT

MULTIPLEXER

QUERY

ROM

ADDRESS
COUNTER

A0-A20

X

DECODER

32

64 k-BYTE

BLOCKS

BYTE#

VCC
GND

VPP

STS

INPUT

BUFFER

I/O

LOGIC

Bank0

Bank1

BE0#
BE

1L#

BE0#
BE

1H#

IDENTIFIER

REGISTER

LH28F320S3TD-L10

- 3 -

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.
A

A

0-A20 INPUT

DQ0-DQ15

BE0#,

BE1L#, BE1H#

INPUT/

OUTPUT

INPUT

RP# INPUT

OE# INPUT OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE# INPUT

OPEN

STS

DRAIN

OUTPUT

WP# INPUT

BYTE# INPUT

V

PP SUPPLY

VCC SUPPLY

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

0 : Byte Select Address. Not used in x16 mode (can be floated).

A

1-A4 : Column Address. Selects 1 of 16-bit lines.

A

5-A15 : Row Address. Selects 1 of 2 048-word lines.

A16-A20 : Block Address.

DATA INPUT/OUTPUTS :

DQ

0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during

memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ

8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during

memory array read cycles in x16 mode; not used for status register, query and identifier
code read mode. Data pins float to high-impedance when the chip is deselected, outputs
are disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle.
BANK ENABLE : Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When BE

0# and BE1L# "low", bank0 is in active. When BE0# and BE1H# are

"low", bank1 is in active. BE0# and BE1L#, BE1H# must not be low at the same time.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# V

IH enables normal operation. When driven VIL, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode) , it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, bank erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
ease is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).
WRITE PROTECT : Master control for block locking. When V
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE : BYTE# V
on DQ

0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode, and turns off the

IL places device in x8 mode. All data are then input or output

A0 input buffer.

BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-BIT
CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or

configuring block lock-bits. With V

PP ≤ VPPLK, memory contents cannot be altered. Block

erase, bank erase, word/byte write, and block lock-bit configuration with an invalid V
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V or 3.3 V
operation. To switch from one voltage to another, ramp V
V

CC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write attempts

CC down to GND and then ramp

to the flash memory are inhibited. Device operations at invalid V

6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted.

LH28F320S3TD-L10

IL, locked blocks can not

PP

CC voltage (see Section

- 4 -

1 INTRODUCTION

This datasheet contains LH28F320S3TD-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications. The LH28F320S3TD-L10
flash memory documentation also includes ordering
information which is referenced in Section 7.

1.1 Product Overview

The LH28F320S3TD-L10 is a high-performance
32 M-bit Smart 3 Dual Work flash memory
organized as 2 MB x8/1 MB x 16 x 2-Bank. The
4 MB of data is arranged in sixty-four 64 k-byte
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.

LH28F320S3TD-L10

A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.41 second (3.3 V

CC, 5 V VPP) independent of other blocks. Each

V
block can be independently erased 100 000 times
(3.2 million block erases per bank). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

A word/byte write is performed in byte increments
typically within 12.95 µs (3.3 V V
multi word/byte write has high speed write
performance of 2.7 µs/byte (3.3 V V
(Multi) word/byte write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.

CC, 5 V VPP). A

CC, 5 V VPP).

Smart 3 technology provides a choice of V

PP combinations, as shown in Table 1, to meet

V
system performance and power expectations. V

CC and

PP

at 2.7 V, 3.3 V and 5 V eliminates the need for a
separate 12 V converter. In addition to flexible
erase and program voltages, the dedicated V
gives complete data protection when V

Table 1 VCC and VPP Voltage Combinations

Offered by Smart 3 Technology

VCC VOLTAGE VPP VOLTAGE

2.7 V 2.7 V, 3.3 V, 5 V

3.3 V 3.3 V, 5 V

PP pin

PP ≤ VPPLK.

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration operations.

Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits per bank, to lock
and unlock blocks. Block lock-bits gate block erase,
bank erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.

The status register indicates when the WSM’s block
erase, bank erase, (multi) word/byte write or block
lock-bit configuration operation is finished.

The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are

- 5 -

LH28F320S3TD-L10

inactive, (multi) word/byte write are suspended, or
the device is in deep power-down mode. The other
3 alternate configurations are all pulse mode for
use as a system interrupt.

The access time is 100 ns (t

AVQV) at the VCC

supply voltage range of 3.0 to 3.6 V over the
temperature range, 0 to +70°C. At 2.7 to 3.6 V

CC, the access time is 120 ns.

V

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

2.7 V and 3.3 V V

CC.

CCR current is 3 mA at

When either BE
are at V

0# or BE1L#, BE1H# and RP# pins

CC, the ICC CMOS standby mode is

enabled. When the RP# pin is at GND, deep
power-down mode is enabled which minimizes
power consumption and provides write protection
during reset. A reset time (t

PHQV) is required from

RP# switching high until outputs are valid. Likewise,
the device has a wake time (t

PHEL) from RP#-high

until writes to the CUI are recognized. With RP# at
GND, the WSM is reset and the status register is
cleared.

- 6 -

LH28F320S3TD-L10

64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block

1FFFFF
1F0000

1EFFFF
1E0000

1DFFFF
1D0000

1CFFFF
1C0000

1BFFFF
1B0000

1AFFFF
1A0000

19FFFF
190000

18FFFF
180000

17FFFF
170000

16FFFF
160000

15FFFF
150000

14FFFF
140000

13FFFF
130000

12FFFF
120000

11FFFF
110000

10FFFF
100000

0FFFFF
0F0000

0EFFFF
0E0000

0DFFFF
0D0000

0CFFFF
0C0000

0BFFFF
0B0000

0AFFFF
0A0000

09FFFF
090000

08FFFF
080000

07FFFF
070000

06FFFF
060000

05FFFF
050000

04FFFF
040000

03FFFF
030000

02FFFF
020000

01FFFF
010000

00FFFF
000000

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block

1FFFFF
1F0000

1EFFFF
1E0000

1DFFFF
1D0000

1CFFFF
1C0000

1BFFFF
1B0000

1AFFFF
1A0000

19FFFF
190000

18FFFF
180000

17FFFF
170000

16FFFF
160000

15FFFF
150000

14FFFF
140000

13FFFF
130000

12FFFF
120000

11FFFF
110000

10FFFF
100000

0FFFFF
0F0000

0EFFFF
0E0000

0DFFFF
0D0000

0CFFFF
0C0000

0BFFFF
0B0000

0AFFFF
0A0000

09FFFF
090000

08FFFF
080000

07FFFF
070000

06FFFF
060000

05FFFF
050000

04FFFF
040000

03FFFF
030000

02FFFF
020000

01FFFF
010000

00FFFF
000000

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

Bank0

(BE

0# = BE1L# = "L")

Bank1

(BE0# = BE1H# = "L")

Fig. 1 Memory Map

- 7 -

2 PRINCIPLES OF OPERATION

The LH28F320S3TD-L10 Smart 3 Dual Work flash
memory includes an on-chip WSM to manage
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration functions. It allows for :
100% TTL-level control inputs, fixed power supplies
during block erase, bank erase, (multi) word/byte
write and block lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2.1 and Table 2.2
"Bus Operations"), the device defaults to read
array mode. Manipulation of external memory
control pins allow array read, standby, and output
disable operations.

Status register, query structure and identifier codes
can be accessed through the CUI independent of

PP voltage. High voltage on VPP enables

the V
successful block erase, bank erase, (multi)
word/byte write and block lock-bit configuration. All
functions associated with altering memory
contents—lock erase, bank erase, (multi) word/byte
write and block lock-bit configuration, status, query
and identifier codes—are accessed via the CUI and
verified through the status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
bank erase, (multi) word/byte write and block lock­bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification, and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes,
outputs query structure or outputs status register
data.

LH28F320S3TD-L10

Interface software that initiates and polls progress
of block erase, bank erase, (multi) word/byte write
and block lock-bit configuration can be stored in
any block. This code is copied to and executed
from system RAM during flash memory updates.
After successful completion, reads are again
possible via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read/write data from/to blocks other
than that which is suspended. Write suspend allows
system software to suspend a (multi) word/byte
write to read data from any other flash memory
array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V
switchable (available only when block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to

PPH1/2/3. The device accommodates either design

V
practice and encourages optimization of the
processor-memory interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with multi-step block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration command sequences, provides
protection from unwanted operations even when
high voltage is applied to V
are disabled when V
voltage V

LKO or when RP# is at V IL. The device’s

CC is below the write lockout

block locking capability provides additional
protection from inadvertent code or data alteration
by gating block erase, bank erase and (multi)
word/byte write operations.

PP power supply

PP. All write functions

- 8 -

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, query structure, or status register
independent of the V

IH.

V

PP voltage. RP# must be at

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes,
Query or Read Status Register) to the CUI. Upon
initial device power-up or after exit from deep
power-down mode, the device automatically resets
to read array mode. Five control pins dictate the
data flow in and out of the component : BE# (BE

1L#, BE1H#), OE#, WE#, RP# and WP#. BE0#,

BE

1L#, BE1H# and OE# must be driven active to

BE
obtain data at the outputs. BE

0#, BE1L#, BE1H# is

0#,

the device selection control, and when active
enables the selected memory device. OE# is the
data output (DQ

0-DQ15) control and when active

drives the selected memory data onto the I/O bus.
WE# and RP# must be at V

IH. Fig. 15 and Fig. 16

illustrate a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ

0-DQ15 are

placed in a high-impedance state.

3.3 Standby

Either BE0# or BE1L#, BE1H# at a logic-high level

IH) places the device in standby mode which

(V
substantially reduces device power consumption.
DQ

0-DQ15 outputs are placed in a high-impedance

state independent of OE#. If deselected during
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.

LH28F320S3TD-L10

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase, bank erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t
after RP# goes to logic-high (V
command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
bank erase, (multi) word/byte write and block lock­bit configuration. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.

PHQV is required

PHWL is required

IH) before another

- 9 -

3.5 Read Identifier Codes Operation

Block 31 Status Code

Block 0

Block 1 Status Code

Block 0 Status Code

Device Code

Manufacture Code

1FFFFF

1F0006
1F0005
1F0004
1F0003

1F0000
1EFFFF

020000
01FFFF

010006
010005
010004
010003

010000
00FFFF

000006
000005
000004
000003
000002
000001
000000

1FFFFF

1F0006
1F0005
1F0004
1F0003

1F0000
1EFFFF

020000
01FFFF

010006
010005
010004
010003

010000
00FFFF

000006
000005
000004
000003
000002
000001
000000

Bank0

(BE0# = BE1L# = "L")

Bank1

(BE

0# = BE1H# = "L")

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 31

(Blocks 2 through 30)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

Block 0

Device Code

Manufacture Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 31

(Blocks 2 through 30)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

Block 31 Status Code

Block 1 Status Code

Block 0 Status Code

The read identifier codes operation outputs the
manufacture code, device code, block status codes
for each block (see Fig. 2). Using the manufacture
and device codes, the system CPU can

LH28F320S3TD-L10

automatically match the device with its proper
algorithms. The block status codes identify locked
or unlocked block setting and erase completed or
erase uncompleted condition.

3.6 Query Operation

The query operation outputs the query structure.
Query database is stored in the 48-byte ROM per
bank. Query structure allows system software to
gain critical information for controlling the flash
component. Query structures are always presented
on the lowest-order data output (DQ

Fig. 2 Device Identifier Code Memory Map

0-DQ7) only.

3.7 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

CC = VCC1/2 and VPP = VPPH1/2/3, the CUI

additionally controls block erase, bank erase, (multi)
word/byte write and block lock-bit configuration.

- 10 -

LH28F320S3TD-L10

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word/Byte Write command requires
the command and address of the location to be

BE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 17 and
Fig. 18 illustrate WE# and BE#-controlled write

operations.
written. Set Block Lock-Bit command requires the
command and block address within the device
(Block Lock) to be locked. The Clear Block Lock­Bits command requires the command and address
within the device.

4 COMMAND DEFINITIONS

When the VPP voltage VPPLK, read operations from

the status register, identifier codes, query, or blocks

are enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase, bank erase, (multi)
The CUI does not occupy an addressable memory
location. It is written when WE# and BE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or

Table 2.1 Bus Operations (BYTE# = VIH)

MODE NOTE RP# BE0#BE1L#BE1H# OE# WE#

Bank0

Read Bank1

Disable VIL VIL VIL

1, 2, 3,

9, 10

VIH VIL VIH VIL VIL VIH XXDOUT X

Output Disable 3 VIH VIL VIL VIL VIH VIH X X High Z X

Bank0

Standby Bank1 3 V

Bank0, 1
Deep Power-Down 4 VIL X X X X X X X High Z High Z
Read
Identifier
Codes

Bank0 V

Bank1 9, 10 V

Disable V
Query 9, 10 VIH VIL VIL VIL VIL VIH

Bank0
Write Bank1

Bank0, 1 V

3, 7,

8, 9

VIH VIL VIH VIL VIH VIL XXDIN X

V

IL VIL VIH

V

IH

IH VIL VIH VIL VIL VIH

IH XX

VIL VIH VIH

IL VIL VIH

IL VIL VIL

VIL VIL VIH

IL VIL VIL

word/byte write and block lock-bit configuration
operations. Device operations are selected by
writing specific commands into the CUI. Table 3
defines these commands.

ADDRESS

X X X X High Z X

See

Fig. 2

See Table
6 through 10

VPP DQ0-15 STS

X

X

(NOTE 5)

(NOTE 6)

High Z

High Z

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

V
CHARACTERISTICS" for V

3. STS is V
WSM is executing internal block erase, bank erase,
(multi) word/byte write or block lock-configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.

IL or VIH for control pins and addresses, and

PPLK and VPPH1/2/3 voltages.

OL (if configured to RY/BY# mode) when the

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. See Section 4.5 for query data.

7. Command writes involving block erase, bank erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when V

CC1/2.

V

8. Refer to Table 3 for valid D

9. Don’t use the timing both OE# and WE# are V

10. Impossible to perform simultaneous read from both
banks at a time. Both BE
be low at the same time.

PP = VPPH1/2/3 and VCC =

IN during a write operation.

IL.

0# and BE1L#, BE1H# must not

- 11 -

LH28F320S3TD-L10

Table 2.2 Bus Operations (BYTE# = VIL)

MODE NOTE RP# BE0#BE1L#BE1H# OE# WE#

Bank0

Read Bank1

Disable VIL VIL VIL

1, 2, 3,

9, 10

VIH VIL VIH VIL VIL VIH XXDOUT X

IL VIL VIH

V

Output Disable 3 VIH VIL VIL VIL VIH VIH X X High Z X

Bank0

Standby Bank1 3 V

Bank0, 1

IH

IH XX

V
VIL VIH VIH

X X X X High Z X

Deep Power-Down 4 VIL XXXXX X XHigh Z High Z
Read
Identifier
Codes

Bank0 VIL VIL VIH
Bank1 9, 10 V
Disable V

IH VIL VIH VIL VIL VIH

IL VIL VIL

Query 9, 10 VIH VIL VIL VIL VIL VIH

Bank0

Write Bank1

Bank0, 1 VIL VIL VIL

3, 7,
8, 9

VIH VIL VIH VIL VIH VIL XXDIN X

VIL VIL VIH

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V
V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

3. STS is V
WSM is executing internal block erase, bank erase,
(multi) word/byte write or block lock-configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.

IL or VIH for control pins and addresses, and

PPLK and VPPH1/2/3 voltages.

OL (if configured to RY/BY# mode) when the

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. See Section 4.5 for query data.

7. Command writes involving block erase, bank erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when V

CC1/2.

V

8. Refer to Table 3 for valid D

9. Don’t use the timing both OE# and WE# are V

10. Impossible to perform simultaneous read from both
banks at a time. Both BE
be low at the same time.

ADDRESS

See

Fig. 2

See Table
6 through 10

VPP DQ0-7 STS

X

(NOTE 5)

X

(NOTE 6)

PP = VPPH1/2/3 and VCC =

IN during a write operation.

0# and BE1L#, BE1H# must not

High Z

High Z

IL.

- 12 -

LH28F320S3TD-L10

COMMAND

Table 3 Command Definitions

BUS CYCLES

REQ’D.

NOTE

Oper

FIRST BUS CYCLE SECOND BUS CYCLE

(NOTE 1)

Addr

(NOTE 10)

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Query ≥ 2 Write X 98H Read QA QD
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase Setup/Confirm 2 5 Write BA 20H Write BA D0H
Bank Erase Setup/Confirm 2 Write X 30H Write X D0H
Word/Byte Write Setup/Write 2 5, 6 Write WA 40H Write WA WD
Alternate Word/Byte Write
Setup/Write
Multi Word/Byte Write
Setup/Confirm
Block Erase and (Multi)
Word/Byte Write Suspend
Confirm and Block Erase and
(Multi) Word/Byte Write Resume
Block Lock-Bit Set
Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm

2 5, 6 Write WA 10H Write WA WD

≥ 4 9 Write WA E8H Write WA N–1

1 5 Write X B0H

1 5 Write X D0H

2 7 Write BA 60H Write BA 01H

2 8 Write X 60H Write X D0H

STS Configuration
Level-Mode for Erase 2 Write X B8H Write X 00H
and Write (RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration Pulse-Mode
for Erase and Write

2 Write X B8H Write X 01H

2 Write X B8H Write X 02H

2 Write X B8H Write X 03H

NOTES :

1. BUS operations are defined in Table 2.1 and Table 2.2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
QA = Query offset address.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 13.1

for a description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or BE# (whichever

goes high first).
ID = Data read from identifier codes.
QD = Data read from query database.

4. Following the Read Identifier Codes command, read
operations access manufacture, device and block status
codes. See Section 4.2 for read identifier code data.

5. If the block is locked, WP# must be at V
block erase or (multi) word/byte write operations.
Attempts to issue a block erase or (multi) word/byte write
to a locked block while RP# is V

6. Either 40H or 10H is recognized by the WSM as the
byte write setup.

7. A block lock-bit can be set while WP# is V

8. WP# must be at V
block lock-bits operation simultaneously clears all block
lock-bits.

9. Following the Third Bus Cycle, inputs the write address
and write data of "N" times. Finally, input the confirm
command "D0H".

10. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

IH to clear block lock-bits. The clear

IH.

IH to enable

IH.

(NOTE 3)

- 13 -

LH28F320S3TD-L10

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, bank erase, (multi) word/byte write or
block lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend and (Multi)
Word/Byte Write Suspend command. The Read
Array command functions independently of the V

PP

voltage and RP# must be VIH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and block erase status (see
Table 4 for identifier code values). To terminate the
operation, write another valid command. Like the
Read Array command, the Read Identifier Codes

DATA

B0

D0

DQ

DQ

PP

1 = 0

1 = 1

2-7

command functions independently of the V
voltage and RP# must be VIH. Following the Read
Identifier Codes command, the following information
can be read :

Table 4 Identifier Codes

CODE

Manufacture Code

Device Code

Block Status Code

•Block is Unlocked DQ0 = 0

•Block is Locked DQ0 = 1

•Last erase operation
completed successfully

•Last erase operation did
not completed successfully

•Reserved for Future Use DQ

ADDRESS

00000H
00001H
00002H
00003H

(NOTE 1)

X0004H

(NOTE 1)

X0005H

NOTE :

1. X selects the specific block status code to be read. See

Fig. 2 for the device identifier code memory map.

4.3 Read Status Register Command

The status register may be read to determine when
a block erase, bank erase, (multi) word/byte write
or block lock-bit configuration is complete and
whether the operation completed successfully (see
Table 13.1). It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or

0# or BE1# (Either BE1L# or BE1H#), whichever

BE
occurs. OE# or BE
BE

1H#) must toggle to VIH before further reads to

0# or BE1# (Either BE1L# or

update the status register latch. The Read Status
Register command functions independently of the

PP voltage. RP# must be VIH.

V

The extended status register may be read to
determine multi byte write availability (see Table

13.2). The extended status register may be read at
any time by writing the Multi Byte Write command.
After writing this command, all subsequent read
operations output data from the extended status
register, until another valid command is written. The
contents of the extended status register are latched
on the falling edge of OE# or BE
BE

1L# or BE1H#), whichever occurs last in the read

0# or BE1# (Either

cycle. Multi Byte Write command must be re-issued
to update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 13.1).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in

- 14 -

LH28F320S3TD-L10

sequence) may be performed. The status register
may be polled to determine if an error occurs
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
must be V

IH. This command is not functional during

PP voltage. RP#

block erase, bank erase, (multi) word/byte write,
block lock-bit configuration, block erase suspend or
(multi) word/byte write suspend modes.

4.5 Query Command

Query database of each bank can be read by
writing Query command (98H). Following the
command write, read cycle from address shown in
Table 6 through Table 10 retrieve the critical
information to write, erase and otherwise control the
flash component. A
ignored when x8 mode (BYTE# = V

Query data of each bank are always presented on
the low-byte data output (DQ
high-byte (DQ

0 of query offset address is

IL).

0-DQ7). In x16 mode,

8-DQ15) outputs 00H. The bytes not

assigned to any information or reserved for future
use are set to "0". This command functions
independently of the V

Table 5 Example of Query Structure Output

MODE OFFSET ADDRESS

A5, A4, A3, A2, A1, A0

1, 0, 0, 0, 0, 0 (20H) High Z "Q"

x8 mode 1, 0, 0, 0, 0, 1 (21H) High Z "Q"

1, 0, 0, 0, 1, 0 (22H) High Z "R"
1, 0, 0, 0, 1, 1 (23H) High Z "R"

A5, A4, A3, A2, A1

x16 mode

1, 0, 0, 0, 0 (10H) 00H "Q"
1, 0, 0, 0, 1 (11H) 00H "R"

PP voltage. RP# must be VIH.

OUTPUT

DQ15-8 DQ7-0

4.5.1 BLOCK STATUS REGISTER

This field provides lock configuration and erase
status for the specified block. These informations
are only available when device is ready (SR.7 = 1).
If block erase or bank erase operation is finished
irregularly, block erase status bit will be set to "1". If
bit 1 is "1", this block is invalid.

Table 6 Query Block Status Register

OFFSET

(Word Address)

(BA+2)H 01H Block Status Register

LENGTH DESCRIPTION

bit0 Block Lock Configuration

0 = Block is unlocked
1 = Block is locked

bit1 Block Erase Status

0 = Last erase operation completed successfully
1 = Last erase operation not completed successfully

bit2-7 Reserved for future use

NOTE :

1. BA = The beginning of a Block Address.

- 15 -

LH28F320S3TD-L10

4.5.2 CFI QUERY IDENTIFICATION STRING

The identification string provides verification that the
component supports the Common Flash Interface
specification. Additionally, it indicates which version

Table 7 CFI Query Identification String

OFFSET

(Word Address)

10H, 11H, 12H 03H Query Unique ASCII string "QRY"

13H, 14H 02H Primary Vendor Command Set and Control Interface ID Code

15H, 16H 02H Address for Primary Algorithm Extended Query Table

17H, 18H 02H Alternate Vendor Command Set and Control Interface ID Code

19H, 1AH 02H Address for Alternate Algorithm Extended Query Table

LENGTH DESCRIPTION

51H, 52H, 59H

01H, 00H (SCS ID Code)

31H, 00H (SCS Extended Query Table Offset)

0000H (0000H means that no alternate exists)

0000H (0000H means that no alternate exists)

of the spec and which vendor-specified command
set(s) is(are) supported.

4.5.3 SYSTEM INTERFACE INFORMATION

The following device information can be useful in optimizing system interface software.

Table 8 System Information String

OFFSET

(Word Address)

1BH 01H V

1CH 01H V

1DH 01H V

1EH 01H V

1FH 01H Typical Time-Out per Single Byte/Word Write

20H 01H Typical Time-Out for Maximum Size Buffer Write (32 Bytes)

21H 01H Typical Time-Out per Individual Block Erase

22H 01H Typical Time-Out for Bank Erase

23H 01H Maximum Time-Out per Single Byte/Word Write, 2

24H 01H Maximum Time-Out per Maximum Size Buffer Write, 2

25H 01H Maximum Time-Out per Individual Block Erase, 2

26H 01H Maximum Time-Out for Bank Erase, 2

LENGTH DESCRIPTION

CC Logic Supply Minimum Write/Erase voltage

27H (2.7 V)

CC Logic Supply Maximum Write/Erase voltage

55H (5.5 V)

PP Programming Supply Minimum Write/Erase voltage

27H (2.7 V)

PP Programming Supply Maximum Write/Erase voltage

55H (5.5 V)

03H (23= 8 µs)

06H (26= 64 µs)

0AH (0AH = 10, 210= 1 024 ms)

0FH (0FH = 15, 215= 32 768 ms)

04H (24= 16, 8 µs x 16 = 128 µs)

04H (24= 16, 64 µs x 16 = 1 024 µs)

04H (24= 16, 1 024 ms x 16 = 16 384 ms)

N

times of typical.

04H (2

4

= 16, 32 768 ms x 16 = 524 288 ms)

N

times of typical.

N

times of typical.

N

times of typical.

- 16 -