Sharp LH28F016SAT-70 Datasheet

LH28F016SA

16M (1M × 16, 2M × 8) Flash Memory

FEATURES

• User-Configurable x8 or x16 Operation

• User-Selectable 3.3 V or 5 V V

CC

• 70 ns Maximum Access Time

• 0.43 MB/sec Write Transf er Rate

• 100,000 Erase Cycles per Block

• 32 Independently Lockable Blocks (64K)

• Revolutionary Architecture

– Pipelined Command Execution
– Write During Erase
– Command Superset of

Sharp LH28F008SA

• 50 µA (Typ.) I

in CMOS Standby

CC

• 1 µA (Typ.) Deep Power-Down

• State-of-the-Art 0.55 µm ETOX™ Flash

Technology

• 56-Pin, 1.2 mm × 14 mm × 20 mm

TSOP (Type I) Package

3/5

CE

NC
A

A
A

A

V

CC

A
A
A
A

CE

V

PP

RP
A
A

A
A

GND

A
A
A
A
A
A
A

1

2

1

3
4

20

5

19

6

18

7A

17

8

16

9

10

15

11

14

12

13

13 44 DQ

12

14

0

15
16

17

11

18

10

19

9

20

8

21

22

7

23

6

24

5

25

4

26

3

27

2

28

1

TOP VIEW56-PIN TSOP

56

WP

55

WE

54 OE
53

RY/BY

52

DQ
DQ

51

DQ

50



49

DQ
GND

48
47

DQ
DQ

46

DQ

45

43 V

GND

42
41

DQ

40

DQ
DQ

39

DQ

38
37

V
DQ

36
35 DQ
34 DQ

33

DQ

32

A

31

BYTE

30

NC

29

NC

15
7

14
6

13
5
12
4

CC

11
3
10
2

CC

9

1
8
0

0

Figure 1. TSOP Configuration

28F016SAT-1

1

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

DQ8 - DQ

OUTPUT
BUFFER

15

OUTPUT

MULTIPLEXER

DQ0 - DQ

OUTPUT
BUFFER

REGISTER

CSR

ESRs

7

ID

DATA

COMPARATOR

INPUT

BUFFER

DATA

QUEUE

REGISTERS

PAGE

BUFFERS

INPUT

BUFFER

CUI

I/O

LOGIC

3/5
BYTE

CE
CE

OE
WE
WP
RP

0
1

A0 - A

20

INPUT

BUFFER

ADDRESS

QUEUE

LATCHES

ADDRESS
COUNTER

Y-DECODER

X-DECODER

. . .

64KB BLOCK 0

Y GATING/SENSING

. . .

64KB BLOCK 1

. . .

64KB BLOCK 30

64KB BLOCK 31

WSM

PROGRAM/

ERASE

VOLTAGE 

SWITCH

Figure 2. LH28F016SA Block Diagram (Architectural Evolution Includes Page Buffers,

Queue Registers and Extended Status Registers)

RY/BY

V

PP

3/5

V

CC

GND

28F016SAT-2

2

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8

A

0

INPUT

mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A
input buffer is turned off when BYTE is high).

0

A1 - A

- A

A

16

- DQ7INPUT/OUTPUT

DQ

0

DQ

- DQ15INPUT/OUTPUT

8

CE

, CE

»

0

RP

INPUT

15

INPUT

20

INPUT

»

1

» INPUT

WORD-SELECT ADDRESSES: Select a word within one 64K block. A

- A15 selects

6

1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are
latched during Data Writes.

BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.

HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs

array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.

CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and

sense amplifiers. With either CE

»

0

or CE

»

high, the device is de-selected and power

1

consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE

, CE

»

0

must be low to select the device. All timing

»

1

specifications are the same for both signals. Device Selection occurs with the latter
falling edge of CE

»

0

RESET/POWER-DOWN: RP

or CE

. The first rising edge of CE

»

1

low places the device in a Deep Power-Down state. All

»

or CE

»

0

disables the device.

»

1

circuits that burn static power, even those circuits enabled in standby mode, are
turned off. When returning from Deep Power-Down, a recovery time of 400 ns

= 5.0 V ± 0.25 V) is required to allow these circuits to power-up. When RP

(V

CC

»

goes low, any current or pending WSM operation(s) are terminated, and the device
is reset. All Status Registers return to ready (with all status flags cleared).

OE

INPUT

»

WE INPUT

RY

»/BY

OPEN DRAIN

»

OUTPUT

OUTPUT ENABLE: Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

NOTE: CE

»

overrides OE

X

», and OE » overrides WE.

» is high.

WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers

and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.

READY/BUSY: Indicates status of the internal WSM. When low, it in dicates that th e

WSM is busy performing an operation. RB

»/BY » high indicates that the WSM is ready

for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE

» or CE

»

, CE

»

are high), except if a RY

0

1

»/BY

Pin Disable command is issued.

»

3

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

PIN DESCRIPTION (Continued)

SYMBOL TYPE NAME AND FUNCTION

WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for

each block. When WP is low, those locke d blocks as reflected by the B lock-Lock Status

WP INPUT

BYTE INPUT

» INPUT

3/5

bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP

BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output

on DQ
byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer.
Address A1, then becomes the lowest order address.

3.3/5.0 V OLT SELECT: 3/5» high configures internal circuits for 3.3 V operation.

3/5» low configures internal circuits f or 5.0 V operation.

NOTES:

device. There is a significant delay from 3/5» » Switching to valid data.

- DQ7, and DQ

0

Reading the array with 3/5» high in a 5.0 V system could damage the

- DQ15 float. Address A0 selects between the high and low

8

» transitions low (deep power-down mode).

V

PP

V

CC

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.

NC

SUPPLY

SUPPLY

INTRODUCTION

Sharp’s LH28F016SA 16M Flash Memory is a revolu­tionary architecture which enables the design of truly mo­bile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single v oltage operation and very high read/write per­formance, the LH28F016SA is also the ideal choice for
designing embedded mass storage flash memory systems.

The LH28F016SA is a v ery high density , highest per­formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi­tecture (100% compatible with the LH28F008SA 8M
Flash memory), extended cycling, low power 3.3 V
operation, very fast write and read performance and
selective bloc k locking provide a highly fle xible memory
component suitable for high density memory cards.
Resident Flash Arrays and PCMCIA-ATA Flash Drives.
The LH28F016SA’s dual read voltage enables the
design of memory cards which can interchangeably be
read/written in 3.3 V and 5.0 V systems. Its x8/x16
architecture allows the optimization of memory to pro­cessor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manuf actured
on Sharp’s 0.55 µm ETOX™ process technology, the

ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing

words/bytes/pages into the flash array.

DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V): Do not leave any

power pins floating.

NO CONNECT: No internal connection to die, lead may be driven or left floating.

DESCRIPTION

The LH28F016SA is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M × 8.
The LH28F016SA includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 3.

The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.

Among the significant enhancements of the
LH28F016SA:

• 3.3 V Low Power Capability

• Improved Write Performance

• Dedicated Block Write/Erase Protection

A 3/5» input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.

The LH28F016SA will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack­age. This f orm factor and pinout allow f or very high board
layout densities.

LH28F016SA is the most cost-effective, high-density

3.3 V flash memory.

4

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

A Command User Interface (CUI) serves as the sys­tem interface between the microprocessor or
microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• T w o-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or
word increments typically within 6 µs, a 33% improve­ment over the LH28F008SA. A Block Erase operation
erases one of the 32 blocks in typically 0.6 seconds,
independent of the other blocks, which is about 65%
improvement ov er the LH28F008SA.

The LH28F016SA incorporates two Page Buffers of
256 Bytes (128 W ords) each to allow page data writes.
This feature can improve a system write performance
over pre vious flash memory de vices.

All operations are started by a sequence of Write
commands to the device. Three Status Registers (de­scribed in detail later) and a RY»/BY» output pin provide
information on the progress of the requested operation.

While the LH28F008SA requires an operation to com­plete before the next operation can be requested, the
LH28F016SA allows queuing of the next oper ation while
the memory executes the current operation. This elimi­nates system overhead when writing sev eral b ytes in a
row to the array or erasing several blocks at the same
time. The LH28F016SA can also perform write opera­tions to one block of memory while performing erase of
another block.

The LH28F016SA contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s
Status Register. This register , when used alone, pro­vides a straightforward upgrade capability to the
LH28F016SA from a LH28F008SA-based design.

• A Global Status Register (GSR) which informs the

system of command Queue status, Page Buff er sta­tus, and over all Write State Machine (WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status inf ormation such as the block
lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 4 and 5.

The LH28F016SA incorporates an open drain
RY»/BY» outpin. This feature allows the user to OR-tie
many RY»/BY» pins together in a multiple memory con­figuration such as a Resident Flash Array.

The LH28F016SA also incorporates a dual chip­enable function with two input pins, CE »0 and CE»1. These
pins have exactly the same functionality as the regular
chip-enable pin CE» on the LH28F008SA. F or minimum
chip designs, CE»1 may be tied to ground and use CE»
as the chip enable input. The LH28F016SA uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE»0 and CE»1 must be ac­tive low to enable the de vice and if either one becomes
inactive, the chip will be disabled. This feature, along
with the open drain RY»/BY» pin, allows the system de-
signer to reduce the number of control pins used in a
large array of 16M de vices .

The BY»TE» pin allows either x8 or x16 read/writes to
the LH28F016SA. BY»TE» at logic low selects 8-bit mode
with address A0 selecting between low byte and high
byte. On the other hand, BY»TE» at logic high enables
16-bit operation with address A1 becoming the lowest
order address and address A0 is not used (don’t care).
A block diagram is shown in Figure 2.

The LH28F016SA is specified for a maximum access
time of each version, as follo ws:

0

The LH28F016SA provides user-selectable block
locking to protect code or data such as Device Driv ers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated non­volatile lock-bit which determines the lock status of the
block. In addition, the LH28F016SA has a master Write
Protect pin (WP
memory blocks whose lock-bits are set.

»

) which prevents any modifications to

OPERATING

TEMPERATURE

0 - 70°C 4.75 - 5.25 V 70 ns
0 - 70°C 4.5 - 5.5 V 80 ns
0 - 70°C 3.0 - 3.6 V 120 ns

V

CC

SUPPLY

MAX. ACCESS

(T

ACC

)

5

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

MEMORY MAPThe LH28F016SA incorporates an Automatic P ow er

Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).

In APS mode, the typical ICC current is 2 mA at

5.0 V (1 mA at 3.3 V).

A Deep Power-Down mode of operation is invoked
when the RP» (called PWD on the LH28F008SA) pin
transitions low . This mode brings the device pow er con­sumption to less than 5 µA, typically , and provides addi­tional write protection by acting as a device reset pin
during power transitions. A reset time of 400 ns
(VCC = 5.0 V ± 0.25 V system) is required from RP»
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR regis­ters are cleared.

A CMOS Standby mode of operation is enabled when
either CE»0 or CE»1 transitions high and RP» sta ys high with
all input control pins at CMOS levels. In this mode, the
device typically dra ws an ICC standby current of 10 µA.

1FFFFFH

1F0000H
1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H
1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH
160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H
0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

64KB BLOCK

64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK

31 64KB BLOCK

30

29 64KB BLOCK

28 64KB BLOCK
27 64KB BLOCK
26 64KB BLOCK
25 64KB BLOCK
24 64KB BLOCK
23 64KB BLOCK
22 64KB BLOCK

21 64KB BLOCK

20 64KB BLOCK
19 64KB BLOCK
18 64KB BLOCK
17 64KB BLOCK
16 64KB BLOCK
15
14
13
12
11
10

9
8
7
6
5
4
3
2

1

0

28F016SAT-3

Figure 3. LH28F016SA Memory Map

(Byte-Wide Mode)

6

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

Extended Status Registers Memory Map

x8 MODE

RESERVED

GSR

RESERVED

BSR31
RESERVED
RESERVED

.
.
.

RESERVED

RESERVED

GSR

RESERVED

BSR0
RESERVED
RESERVED

Figure 4. Extended Status Register

Memory Map (Byte-Wide Mode)

A[20:0]

1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H

010002H

000006H
000005H
000004H
000003H
000002H
000001H
000000H

28F016SAT-4

x16 MODE

A[20:1] (NOTE)

RESERVED

GSR

RESERVED

BSR31
RESERVED
RESERVED

.

F8003H

F8002H

F8001H

F8000H

.
.

08001H

RESERVED

RESERVED

GSR

RESERVED

BSR0
RESERVED
RESERVED

NOTE: In word-wide mode A0 don't care, address values 
are ignored A0.

Figure 5. Extended Status Register

Memory Map (Word-Wide Mode)

00003H

00002H

00001H

00000H

28F016SAT-5

7

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BY»TE» = VIH)

MODE RP

Read V
Output Disable V

Standby V

Deep Powe r-Do wn V
Manufacturer ID V
Devi ce ID V
Wri te V

» CE »

IH

IH

IH

IL

IH

IH

IH

1

V

IL

V

IL

V

IL

V

IH

V

IH

XXXXX High-Z VOH1, 3

V

IL

V

IL

V

IL

CE

V
V
V

V
V

V
V
V

»

0

IL

IL

IH

IL

IH

IL

IL

IL

OE

» WE A

V

V

V

IL

IH

IH

V

IH

DQ0 - DQ

1

XD

15

OUT

X High-Z X 1, 6, 7

RY

»/BY » NOTE

X1, 2, 7

X X X High-Z X 1, 6, 7

V
V

V

V

IL

V

IL

V

IH

V

IH

IH

IL

IL

V

IH

XDINX1, 5, 6

0089H V
66A0H V

OH

OH

4
4

Bus Operations For Byte-Wide Mode (BY»TE» = VIL)

PPH

» CE »

IH

IH

IH

IL

IH

IH

IH

.

1

V

IL

V

IL

V

IL

V

IH

V

IH

XXXXX High-Z VOH1, 3

V

IL

V

IL

V

IL

MODE RP

Read V
Output Disable V

Standby V

Deep Powe r-Do wn V
Manufacturer ID V
Devi ce ID V
Wri te V

NOTES:

1. X can be VIH or VIL for address or control pins except for RY»/BY», which is either VOL or VOH.

2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY»/BY» will be at VOH if it is tied to VCC through a resistor. When the RY»/BY» at VOH is independent of OE
operation is in progress.

3. RP» at GND ± 0.2 V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A0 and A1, at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully com­pleted when VPP = V

6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at VOL until all operations are complete. RY»/BY» goes to
VOH when the WSM is not busy or in erase suspend mode.

7. RY»/BY» may be at VOL while the WSM is busy performing various operations. For example, a status register read during a
write operation.

CE

V
V
V

V
V

V
V
V

»

0

IL

IL

IH

IL

IH

IL

IL

IL

OE

» WE A

V

V

V

IL

IH

IH

V

IH

DQ0 - DQ

0

XD

7

OUT

X High-Z X 1, 6, 7

RY

»/BY » NOTE

X1, 2, 7

X X X High-Z X 1, 6, 7

V
V

V

V

IL

V

IL

V

IH

V

IH

IH

IL

IL

V

IH

XDINX1, 5, 6

89H V
A0H V

OH

OH

»

while a WSM

4
4

8

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

LH28F008SA-Compatible Mode Command Bus Definitions

COMMAND

NOTE

OPER. ADDRESS DATA OPER. ADDRESS DATA

Read Array Write X FFH Read AA AD
Intelligent Identifier Write X 90H Read IA ID 1
Read Compatible Status Register Write X 70H Read X CSRD 2
Clear Status Register Write X 50H 3
Word/Byte Write Write X 40H Write WA WD
Alternate Word/Byte Write Write X 10H Write WA WD
Block Erase/Confirm Write X 20H Write BA D0H 4
Erase Suspend/Resume Write X B0H Write X D0H 4

ADDRESS DATA

AA = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
WA = Write Address WD = Write Data
X = Don’t Care

NOTES:

1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.

3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.

4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued,while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/
Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to Perfor­mance Enhancement Command Bus Definitions.)

FIRST BUS CYCLE SECOND BUS CYCLE

9

LH28F016SA 16M (1M × 16, 2M × 8) Flash Memory

LH28F016SA Performance Enhancement Command Bus Definitions

COMMAND MODE

NOTE

OPER. ADDR. DAT A OPE R. ADDR. DAT A OPE R. ADDR. DAT A

FIRST BUS CYCLE SECOND BUS CYCLE THIRD BUS CYCLE

Read Extended
Status Register

Write X 71H Read RA

GSRD

BSRD
Page Buffer Swap Write X 72H 7
Read Page Buffer Write X 75H Read PA PD
Single Load to

Page Buffer

Writ e X 74H Wr i t e PA PD

x8 Wr it e X E0H Wr it e X BCL Wri te X BCH 4, 6, 1 0

Sequential Load to
Page Buffer

Page Buffer Write

x16 Write X E0H Writ e X WC L Writ e X WCH

x8 Write X 0 CH Write A0

BC

(L, H)

Write WA BC (H, L)

4, 5,

6, 10

3, 4,

9, 10

to Flash

x16 Write X 0CH Wr it e X WC L Writ e WA WCH 4, 5, 10

Two-Byte Wri te x8 Write X FBH Write A0

Block
Erase/Confirm

Write X 20H Write BA D0H Write X D0H 11

WD

(L, H)

Write WA W D (H, L ) 3

1

Lock Block/Confirm Write X 77H Write BA D0H
Upload Status

Bits/Confirm
Uploa d Devic e

Information
Erase All Unlocked

Blocks/Confirm
RY

»/BY » Enable to

Level-Mode

»/BY » Pulse-On-

RY
Writ e

»

»

/BY

RY

Pulse-On-

Erase

»/BY » Disable Write X 96H Write X 04H 8

RY

Writ e X 97H Wri t e X D0H 2

Writ e X 9 9H Wri te X D0H

Writ e X A7H Wri te X D0H Wri te X D0H 1 1

Write X 96H Write X 01H 8

Write X 96H Write X 02H 8

Write X 96H Write X 03H 8

Sleep Write X F0H
Abort Write X 80H

ADDRESS DATA

BA = Block Address AD = Array Data
PA = Page Buffer Address PD = Page Buffer Data
RA = Extended Register Address BSRD = BSR Data
WA = Write Address GSRD = GSR Data
X = Don’t Care WC (L, H) = Word Count (Low, High)

BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)

10

16M (1M × 16, 2M × 8) Flash Memory LH28F016SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figure 4 and 5 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual
lock-bit status.

3. A0 is automatically complemented to load second byte of data. BY»TE
first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.

5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.

6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure RY»/BY» output to one of two pulse-modes or enable and disable the RY»/BY» function.

9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F016SU User’s Manual.

10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.

11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.

»

must be at VIL. A0 value determines which WD/BC is supplied

Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

CSR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready
0 = Busy

CSR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended
0 = Erase in Progress/Completed

CSR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure
0 = Successful Block Erase

CSR.4 = DATA-WRITE STATUS (DWS)

1 = Error in Data Write
0 = Data Write Successful

CSR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort
0 = VPP OK

NOTES:

1. RY»/BY» output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.

2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.

3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between V

4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.

PPL

and V

PPH

.

11