Sharp LH28F016LLT-15, LH28F016LLT-12 Datasheet

LH28F016LL

1

16M (1M × 16, 2M × 8) Flash Memory

Figure 1. TSOP Configuration

FEATURES

• User-Configurable x8 or x16 Operation

• 3 V Write/Erase Operation (3 V V

PP

)

– 2.7 - 3.6 V Write-Erase Operation

• 120 ns Maximum Access Time

(V

CC

= 3.0 V)

• 150 ns Maximum Access Time

(V

CC

= 2.7 V)

• 32 Independently Lockable Blocks (64K)

• 0.48 MB/sec Write Transf er Rate

• 100,000 Erase Cycles per Block

• Revolutionary Architecture

– Pipelined Command Execution
– Write During Erase
– Command Superset of

Sharp LH28F016SU

• 10 µA (MAX.) I

CC

in CMOS Standby

• 5 µA (MAX.) Deep Power-Down

• State-of-the Art 0.6 µm ETOX™

Flash Technology

• 56-Pin, 1.2 mm × 14 mm × 20 mm TSOP

(Type I) Package

28F016LLT-1

TOP VIEW56-PIN TSOP

2
3

4
5

8
9

A

16

A

19

A

20

53
52
51
50



49
48

45

42

LX

6
7A

17

A

18

47
46

RY/BY
DQ

15

DQ

14

GND

GND

10

11

12

55
54 OE

V

CC

13 44 DQ

4

43 V

CC

A

15

DQ

7

14
15
16
17
18
19
20

39

36

41
40

38
37

DQ

3

DQ

10

DQ

2

V

CC

A

10

A

9

A

11

CX
RP

CE

0

A

8

DQ

9

WE

DQ

6

DQ

13

DQ

11

56

1

CE

1

VSSL

WP

21
22
23

24
25
26
27
28

A

4

A

3

A

5

A

7

A

6

GND

A

2

A

1

34 DQ

8

35 DQ

1

31

33
32

30
29

A

0

BYTE
NC
NC

DQ

0

A

14

A

13

A

12

DQ

5

DQ

12

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

2

Figure 2. LH28F016LL Block Diagram (Architectural Evolution Includes Page Buffers,

Queue Registers and Extended Status Registers)

OUTPUT
BUFFER

OUTPUT
BUFFER

INPUT

BUFFER

INPUT

BUFFER

DQ8 - DQ

15

DQ0 - DQ

7

ID

REGISTER

OUTPUT

MULTIPLEXER

CSR

ESRs

DATA

COMPARATOR

DATA

QUEUE

REGISTERS

PAGE

BUFFERS

I/O

LOGIC

CUI

WSM

64KB BLOCK 0

64KB BLOCK 1

64KB BLOCK 30

64KB BLOCK 31

. . .

. . .

Y GATING/SENSING

Y-DECODER

X-DECODER

CE

0

CE

1

OE
WE
WP
RP

PROGRAM/

ERASE

VOLTAGE 

SWITCH

DC/DC

CONVERTER

BYTE

LX
CX

V

CC

GND

RY/BY

ADDRESS
COUNTER

ADDRESS

QUEUE

LATCHES

INPUT

BUFFER

A0 - A

20

. . .

28F016LLT-2

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

3

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A

0

INPUT

BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8

mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A

0

input buffer is turned off when BYTE is high).

A

1

- A

15

INPUT

WORD-SELECT ADDRESSES: Select a word within one 64K block. A

6

- A

15

selects
1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are
latched during Data Writes.

A

16

- A

20

INPUT

BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

DQ

0

- DQ7INPUT/OUTPUT

LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.

Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.

DQ

8

- DQ15INPUT/OUTPUT

HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs

array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.

CE

»

0

, CE

»

1

INPUT

CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and

sense amplifiers. With either CE

»

0

or CE

»

1

high, the device is de-selected and power
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE

»

0

, CE

»

1

must be low to select the device. All timing

specifications are the same for both signals. Device Selection

occ

urs with the latter

falling edge of CE

»

0

or CE

»

1

. The first rising edge of CE

»

0

or CE

»

1

disables the device.

RP

» INPUT

RESET/POWER-DOWN: RP

»

low places the device in a Deep Power-Down state. All
circuits that burn static power, even those circuits enabled in standby mode, are turned
off. When returning from Deep Power-Down, a recovery time of 5 ns is required to
allow these circuits to power-up for Read mode, and another 395 ns is required to enter
Program or Erase mode. W hen RP

» goes low, any current or pending WSM operation(s)

are terminated, and the device is reset. All Status registers return to ready (with all
status flags cleared).

OE

»

INPUT

OUTPUT ENABLE: Gates device data through the output buffers when low. The

outputs float to tri-state off when OE

» is high.

NOTE: CE

»

X

overrides OE

», and OE » overrides WE.

WE INPUT

WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers

and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.

RY

»/BY

»

OPEN DRAIN
OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it ind icates that the

WSM is busy performing an operation. RY

»/BY » high indicates that the WSM is ready

for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE

» or CE

»

0

, CE

»

1

are high), except if a RY

»/BY

»

Pin Disable command is issued.

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

4

PIN DESCRIPTION (Continued)

SYMBOL TYPE NAME AND FUNCTION

WP INPUT

WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for

each block. When WP is low, those locke d blocks as reflected by the B lock-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP

» transitions low (deep power-down mode).

BYTE INPUT

BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output

on DQ0 - DQ7, and DQ8 - DQ15 float. Address A0 selects between the high and low
byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer.
Address A1, then becomes the lowest order address.

LX INPUT

INPUT FROM OUTSIDE INDUCTOR: Input pin for outside inductor in DC/DC

converter circuit. Connect 1.8 (µH) inductor from VCC.

LC INPUT

INPUT FROM OUTSIDE CAPACITOR: Input pin for outside capacitor in DC/DC

converter circuit. Ground at 22000 (pF) capacitor.

V

CC

SUPPLY DEVICE POWER SUPPLY 3.0 V (2.7 V to 3.6 V): Do not leave any power pins floating.

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.

NC NO CONNECT: No internal connection to die, lead may be driven or left floating.

VSSL GROUND

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

5

INTRODUCTION

Sharp’s LH28F016LL 16M Flash Memory is a revo­lutionary architecture which enables the design of truly
mobile, high performance, personal computing and com­munication products. With innovative capabilities,
3 V single voltage operation and very high read/write
performance, the LH28F0166LL is also the ideal choice
for designing embedded mass storage flash memory
systems.

The LH28F016LL is very high density, highest per­formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi­tecture (100% compatible with the LH28F016SU 16M
Flash memory), extended cycling, minimum power

2.7 V operation, very fast write and read performance
and selective block locking provide a highly flexible
memory component suitable for battery operation por­table equipment such as digital still camera, PDA, cel­lular phone, and memory card. Its x8/x16 architecture
allows the optimization of memory to processor inter­face. The flexible b lock loc king option enab les bundling
of executable of executable application software in a
Resident Flash Array or memory card. Manufactured
on Sharp’s 0.6 µm ETOX™ process technology, the
LH28F016LL is the most cost-effective, high-density
3 V single po wer oper ation flash memory.

DESCRIPTION

The LH28F016LL is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M x 8.
The LH28F016LL includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 3.

The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.

Among the significant enhancements of the
LH28F016LL:

• 3 V Write/Erase Operation (3 V V

PP

)

• 3 V Low Power Capability

• Improved Write P erformance

• Dedicated Block Write/Erase Protection

The LH28F016LL will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack­age. This f orm factor and pinout allow for v ery high board
layout densities.

A Command User Interface (CUI) serves as the sys­tem interface between the microprocessor or
microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed us­ing a Two-Write command sequence to the CUI in the
same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• T w o-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or
word increments typically within 9 µs, a 15% improve­ment over the LH28F008SA.

Each block can be written and erased a minimum of
100,000 cycles. Systems can achie ve 1,000,000 Block
Erase Cycles by providing wear-le veling algorithms and
graceful block retirement. These techniques have
already been employed in man y flash file systems and
Hard Disk Drive designs.

The LH28F016LL incorporates two Page Buffers of
256 Bytes (128 W ords) each to allow page data writes.
This feature can improve a system write performance
by up to 4.8 times over pre vious flash memory devices.

All operations are started by a sequence of Wr ite
commands to the device. Three Status Registers (de­scribed in detail later) and a RY»/BY» output pin provide
information on the progress of the requested operation.

While the LH28F008SA requires an operation to com­plete before the next operation can be requested, the
LH28F016LL allows queuing of the next operation while
the memory executes the current operation. This elimi­nates system overhead when writing sev eral b ytes in a
row to the array or erasing several blocks at the same
time. The LH28F016LL can also perform write opera­tions to one block of memory while performing erase of
another block.

The LH28F016LL provides user-selectable block
locking to protect code or data such as Device Driv ers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated non­volatile lock-bit which determines the lock status of the
block. In addition, the LH28F016LL has a master Write
Protect pin (WP

»

) which prevents any modifications to

memory blocks whose lock-bits are set.

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

6

Figure 3. LH28F016LL Memory Map

MEMORY MAPThe LH28F016LL contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s
Status Register. This register , when used alone, pro­vides a straightforward upgrade capability to the
LH28F016LL from a LH28F008SA-based design.

• A Global Status Register (GSR) which informs

the system of command Queue status. Page
Buffer status, and overall Write Status Machine
(WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status inf ormation such as the bloc k
lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 4 and 5.

The LH28F016LL incorporates an open drain
RY»/BY» output pin. This feature allows the user to OR­tie many RY »/BY» pins together in a multiple memory con­figuration such as a Resident Flash Array.

The LH28F016LL also incorporates a dual chip­enable function with two input pins, CE »0 and CE»1. These
pins have e xactly the same functionality as the regulary
chip-enable pin CE» on the LH28F008SA. F or minimum
chip designs, CE»1 may be tied to ground and use CE»

0

as the chip enable input. The LH28F016LL uses the logi­cal combination of these two signals to enable or dis­able the entire chip. Both CE»0 and CE»1 must be active
low to enable the device and if either one becomes in­active, the chip will be disabled. This f eature, along with
the open drain RY»/BY » pin, allo ws the system designer
to reduce the number of control pins used in a large
array of 16M de vices.

The BY»TE» pin allows either x8 or x16 read/writes to
the LH28F016LL. BY »TE» at logic low selects 8-bit mode
with address A0 selecting between low byte and high
byte. On the other hand, BY »TE» at logic high enables
16-bit operation with address A1 becoming the lowest
order address and address A0 is not used (don’t care).
A device diagram is sho wn in Figure 1.

The LH28F016LL is specified for a maximum access
time (t

ACC

)150 ns, in operating voltage 2.7 V to 3.6 V

and in operating temperature 0°C to +70°C.

The LH28F016LL incorporates an Automatic P ower
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (address not switching).

In APS mode, the typical I

CC

current is 1 mA at 3.0 V.

A Deep Power-Down mode of operation is invoked
when the RP» (called PWD on the LH28F008SA) pin
transitions low . This mode brings the device power con­sumption to less than 5 µA typically , and pro vides addi­tional write protection by acting as a device reset pin
during power transitions. A reset time of 480 ns is re­quired from RP» switching high until outputs are again
valid. In the Deep Power-Down state , the WSM is reset

(any current operation will abort) and the CSR, GSR
and BSR registers are cleared.

A CMOS Standby mode of operation is enabled when
either CE»0 or CE»1 transitions high and RP» stays high
with all input control pins at CMOS levels . In this mode ,
the device typically draws an I

CC

standby current of

10 µA.

15

1F0000H

1FFFFFH

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

18FFFFH

180000H

17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

000000H

14
13
12
11
10

9
8
7
6
5
4
3
2

0

64KB BLOCK

16 64KB BLOCK

17 64KB BLOCK

18 64KB BLOCK

19 64KB BLOCK

20 64KB BLOCK

21 64KB BLOCK

22 64KB BLOCK

23 64KB BLOCK

24 64KB BLOCK

25 64KB BLOCK

26 64KB BLOCK

27 64KB BLOCK

28 64KB BLOCK

29 64KB BLOCK

30 64KB BLOCK

31 64KB BLOCK

64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK

1

64KB BLOCK

64KB BLOCK

28F016LLT-3

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

7

Figure 4. Extended Status Register

Memory Map (Byte-Wide Mode)

Figure 5. Extended Status Register

Memory Map (Word-Wide Mode)

Extended Status Registers Memory Map

RESERVED

GSR

RESERVED

BSR31
RESERVED
RESERVED

1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H

A[20:0]

x8 MODE

.
.
.

RESERVED

GSR

RESERVED

BSR0
RESERVED
RESERVED

000006H
000005H
000004H
000003H
000002H
000001H
000000H

RESERVED

010002H

28F016LLT-4

RESERVED

GSR

RESERVED

BSR31
RESERVED
RESERVED

F8003H

F8002H

F8001H

F8000H

A[20:1] (NOTE)

x16 MODE

.
.
.

RESERVED

GSR

RESERVED

BSR0
RESERVED
RESERVED

00003H

00002H

00001H

00000H

RESERVED

08001H

28F016LLT-5

NOTE: In word-wide mode A0 don't care, address values 
are ignored A0.

LH28F016LL 16M (1M × 16, 2M × 8) Flash Memory

8

BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BY»TE» = VIH)

MODE RP

» CE »

1

CE

»

0

OE

» WE A

1

DQ0 - DQ

15

RY

»/BY » NOTE

Read V

IH

V

IL

V

IL

V

IL

V

IH

XD

OUT

X1, 2

Output Disable V

IH

V

IL

V

IL

V

IH

V

IH

X High-Z X 1, 6

Standby V

IH

V

IL

V

IH

V

IH

V

IH

V

IL

V

IH

X X X High-Z X 1, 6

Deep Powe r-Down V

IL

XXXXX High-Z VOH1, 3

Manufacturer ID V

IH

V

IL

V

IL

V

IL

V

IH

V

IL

00B0H V

OH

4

Device ID V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

6688H V

OH

4

Writ e V

IH

V

IL

V

IL

V

IH

V

IL

XDINX1, 5, 6

NOTES:

1. X can be VIH or VIL for address or control pins except for RY»/BY», which is either VOL or VOH.

2. RY»/BY» output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY»/BY» will be at VOH if it is tied to VCC through a resistor. When the RY»/BY» at VOH is independent of OE

»

while a WSM

operation is in progress.

3. RP» at GND ± 0.2 V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
A0 and A1, at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully
completed when VPP = V

PPH

.

6. While the WSM is running, RY»/BY» in Level-Mode (default) stays at VOL until all operations are complete. RY»/BY» goes to
VOH when the WSM is not busy or in erase suspend mode.

Bus Operations For Byte-Wide Mode (BY»TE» = VIL)

MODE RP

» CE »

1

CE

»

0

OE

» WE A

0

DQ0 - DQ

7

RY

»/BY » NOTE

Read V

IH

V

IL

V

IL

V

IL

V

IH

XD

OUT

X1, 2

Output Disable V

IH

V

IL

V

IL

V

IH

V

IH

X High-Z X 1, 6

Standby V

IH

V

IL

V

IH

V

IH

V

IH

V

IL

V

IH

X X X High-Z X 1, 6

Deep Powe r-Down V

IL

XXXXX High-Z VOH1, 3

Manufacturer ID V

IH

V

IL

V

IL

V

IL

V

IH

V

IL

B0H V

OH

4

Device ID V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

88H V

OH

4

Writ e V

IH

V

IL

V

IL

V

IH

V

IL

XDINX1, 5, 6

16M (1M × 16, 2M × 8) Flash Memory LH28F016LL

9

COMMAND

FIRST BUS CYCLE SECOND BUS CYCLE

NOTE

OPER. ADDRESS DATA OPER. ADDRESS DATA

Read Array Write X FFH Read AA AD
Intelligent Identifier Write X 90H Read IA ID 1
Read Compatible Status Register Write X 70H Read X CSRD 2
Clear Status Register Write X 50H 3
Word/Byte Write Write X 40H Write WA WD
Alternate Word/Byte Write Write X 10H Write WA WD
Block Erase/Confirm Write X 20H Write BA D0H
Erase Suspend/Resume Write X B0H Write X D0H

ADDRESS DATA

AA = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
WA = Write Address WD = Write Data
X = Don’t Care

NOTES:

1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.

3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.

4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/
Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to
Performance Enhancement Command Bus Definitions.)

LH28F008SA-Compatible Mode Command Bus Definitions