SHARP LH28F008SC-V, LH28F008SCH-V User Manual

LH28F008SC-V/SCH-V

DESCRIPTION

The LH28F008SC-V/SCH-V flash memories with
Smart 5 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and memory
cards. Their enhanced suspend capabilities provide
for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F008SC-V/SCH-V offer three levels of
protection : absolute protection with V

PP at GND,

selective hardware block locking, or flexible software
block locking. These alternatives give designers
ultimate control of their code security needs.

FEATURES

• Smart 5 technology
–5 V V

CC

– 5 V or 12 V VPP

• High performance read access time

LH28F008SC-V85/SCH-V85

– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)

LH28F008SC-V12/SCH-V12

– 120 ns (5.0±0.5 V)

• Enhanced automated suspend options
– Byte write suspend to read
– Block erase suspend to byte write
– Block erase suspend to read

• Enhanced data protection features
– Absolute protection with V

PP = GND

– Flexible block locking
– Block erase/byte write lockout during power

transitions

• SRAM-compatible write interface

• High-density symmetrically-blocked architecture
– Sixteen 64 k-byte erasable blocks

• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

CC

in static mode

• Automated byte write and block erase
– Command user interface
– Status register

• ETOX

TM

∗

V nonvolatile flash technology

• Packages
– 40-pin TSOP Type I (TSOP040-P-1020)

Normal bend/Reverse bend
– 44-pin SOP (SOP044-P-0600)
– 48-ball CSP (FBGA048-P-0608)

∗

ETOX is a trademark of Intel Corporation.

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F008SC-V/SCH-V

8 M-bit (1 MB x 8) Smart 5

Flash Memories

DC CHARACTERISTICS

VERSIONS

OPERATING TEMPERATURE

VCCdeep power-down current (MAX.)

LH28F008SC-V 0 to +70˚C 10 µA
LH28F008SCH-V –25 to +85

˚

C 20 µA

COMPARISON TABLE

查询LH28F008SC-V供应商

LH28F008SC-V/SCH-V

- 2 -

44-PIN SOP

(SOP044-P-0600)

VPP

RP#

A

11

A10

A9
A8
A7
A6
A5

A4
NC
NC

A

3

A2

A1

A0

DQ0
DQ1
DQ2

DQ3
GND
GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

VCC
CE#
A

12

A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ

7

DQ6
DQ5
DQ4
VCC

40-PIN TSOP (Type I)

(TSOP040-P-1020)

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

VPP

RP#

A

11

A10

A9
A8
A7
A6
A5
A4

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

NC
NC
WE#
OE#
RY/BY#
DQ

7

DQ6
DQ5
DQ4
VCC
GND
GND
DQ

3

DQ2
DQ1
DQ0
A0
A1
A2
A3

A5

1

A

A6B

A

4C

A

3D

A

1E

A

2

A8

2

A9

A7

A0

DQ1

DQ0

A11 VPP VCC

3

A10

DQ2

GND

DQ3

4

NC

NC

NC

GND

5

NC

NC

NC

NC

VCC

A12

6

CE#

A13

DQ6

DQ4

DQ5

A15

7

A14

A16

RY/BY#

DQ7

NC

A

18

8

A17

A19

NC

OE#

WE#

F

NC

RP#

(FBGA048-P-0608)

48-BALL CSP

NOTE :

Reverse bend available on request.

TOP VIEW

PIN CONNECTIONS

LH28F008SC-V/SCH-V

- 3 -

BLOCK DIAGRAM

Y GATING

Y DECODER

INPUT

BUFFER

OUTPUT
BUFFER

DQ0-DQ7

VCC

CE#
WE#
OE#
RP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE
VOLTAGE SWITCH

STATUS

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

DATA

REGISTER

OUTPUT

MULTIPLEXER

IDENTIFIER

REGISTER

ADDRESS
COUNTER

A0-A19

X DECODER

16

64 k-BYTE

BLOCKS

RY/BY#

VCC
GND

V

PP

INPUT

BUFFER

I/O

LOGIC

LH28F008SC-V/SCH-V

- 4 -

SYMBOL TYPE NAME AND FUNCTION

A

0-A19 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.

INPUT/

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V

HH enables setting of the

master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP# = V

HH overrides block lock-bits thereby enabling block erase and byte write

operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIH ≤ RP# ≤ VHH produce spurious results and should not be attempted.

OE# INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle.

WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For
erasing array blocks, writing bytes, or configuring lock-bits. With V

PP ≤ VPPLK, memory

contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results

and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation.
Do not float any power pins. With V

CC ≤ VLKO, all write attempts to the flash memory

are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC
CHARACTERISTICS") produce spurious results and should not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

OUTPUT

DQ

0-DQ7

PIN DESCRIPTION

RP#

INPUT

RY/BY# OUTPUT

V

PP SUPPLY

V

CC SUPPLY

VCC VOLTAGE VPP VOLTAGE

5 V 5 V, 12 V

LH28F008SC-V/SCH-V

1 INTRODUCTION

This datasheet contains LH28F008SC-V/SCH-V
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SC-V/
SCH-V flash memories documentation also
includes ordering information which is referenced in
Section 7.

1.1 New Features

LH28F008SC-V/SCH-V Smart 5 flash memories
maintain backwards-compatibility with the
LH28F008SA. Key enhancements over the
LH28F008SA include :

• Smart 5 Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
LH28F008SA to LH28F008SC-V/SCH-V. When
upgrading, it is important to note the following
differences :

• Because of new feature support, the two
devices have different device codes. This
allows for software optimization.

•V

PPLK has been lowered from 6.5 V to 1.5 V to

support 5 V block erase, byte write, and lock-bit
configuration operations. Designs that switch
V

PP off during read operations should make

sure that the V

PP voltage transitions to GND.

• To take advantage of Smart 5 technology, allow
V

PP connection to 5 V.

1.2 Product Overview

The LH28F008SC-V/SCH-V are high-performance
8 M-bit Smart 5 flash memories organized as 1 M­byte of 8 bits. The 1 M-byte of data is arranged in
sixteen 64 k-byte blocks which are individually

erasable, lockable, and unlockable in-system. The
memory map is shown in Fig.1.

Smart 5 technology provides a choice of V

CC and

V

PP combinations, as shown in Table 1, to meet

system performance and power expectations. V

PP

at 5 V eliminates the need for a separate 12 V
converter, while V

PP = 12 V maximizes block erase

and byte write performance. In addition to flexible
erase and program voltages, the dedicated V

PP pin

gives complete data protection when V

PP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by Smart 5 Technology

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, byte write, and lock-bit
configuration operations.

A block erase operation erases one of the device’s
64 k-byte blocks typically within 1 second (5 V V

CC,

12 V V

PP) independent of other blocks. Each block

can be independently erased 100 000 times (1.6
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

Writing memory data is performed in byte
increments typically within 6 µs (5 V V

CC, 12 V

V

PP). Byte write suspend mode enables the system

- 5 -

LH28F008SC-V/SCH-V

to read data from, or write data to any other flash
memory array location.

Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
gates block lock-bit modification. Lock-bit
configuration operations (Set Block Lock-Bit, Set
Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.

The status register indicates when the WSM

’s block

erase, byte write, or lock-bit configuration operation
is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, byte write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and byte write is inactive), byte write
is suspended, or the device is in deep power-down
mode.

The access time is 85 ns (t

AVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70˚C (LH28F008SC-V)/
–25 to +85˚C (LH28F008SCH-V). At 4.5 to 5.5 V
V

CC, the access time is 90 ns or 120 ns.

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR current is 1 mA at

5 V V

CC.

When CE# and RP# pins are at V

CC, the ICC

CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

Fig. 1 Memory Map

64 k-Byte Block

64 k-Byte Block

64 k-Byte Block
64 k-Byte Block

64 k-Byte Block

64 k-Byte Block
64 k-Byte Block

64 k-Byte Block

64 k-Byte Block

64 k-Byte Block

64 k-Byte Block
64 k-Byte Block

64 k-Byte Block

64 k-Byte Block
64 k-Byte Block

64 k-Byte Block

FFFFF
F0000

EFFFF
E0000

DFFFF

CFFFF

D0000

C0000
BFFFF

B0000
AFFFF

A0000
9FFFF

90000
8FFFF

80000
7FFFF

70000
6FFFF

60000
5FFFF

50000
4FFFF

40000
3FFFF

30000
2FFFF

20000
1FFFF

10000
0FFFF

00000

15
14

13

12

11
10

9

8
7

6
5

4

3
2

1

0

- 6 -

LH28F008SC-V/SCH-V

2 PRINCIPLES OF OPERATION

The LH28F008SC-V/SCH-V Smart 5 flash
memories include an on-chip WSM to manage
block erase, byte write, and lock-bit configuration
functions. It allows for : 100% TTL-level control
inputs, fixed power supplies during block erasure,
byte write, and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

PP

voltage. High voltage on VPP enables successful
block erasure, byte writing, and lock-bit
configuration. All functions associated with altering
memory contents—block erase, byte write, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.

Interface software that initiates and polls progress
of block erase, byte write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system

software to suspend a block erase to read/write
data from/to blocks other than that which is
suspended. Byte write suspend allows system
software to suspend a byte write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to V

PPH1/2. The device

accommodates either design practice and
encourages optimization of the processor-memory
interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V

PP. All write

functions are disabled when V

CC is below the write

lockout voltage V

LKO or when RP# is at VIL. The

device

’s block locking capability provides additional

protection from inadvertent code or data alteration
by gating erase and byte write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, or status register independent of the V

PP

voltage. RP# can be at either VIH or VHH .

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read

- 7 -

LH28F008SC-V/SCH-V

array mode. Four control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
and RP#. CE# and OE# must be driven active to
obtain data at the outputs. CE# is the device
selection control, and when active enables the
selected memory device. OE# is the data output
(DQ

0-DQ7) control and when active drives the

selected memory data onto the I/O bus. WE# must
be at V

IH and RP# must be at VIH or VHH . Fig. 12

illustrates a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ

0-DQ7 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ

0-DQ7 outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation
completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t

PHWL is required

after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. SHARP

’s flash memories

allow proper CPU initialization following a system
reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET#
signal that resets the system CPU.

- 8 -

LH28F008SC-V/SCH-V

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Fig. 2). Using the
manufacture and device codes, the system CPU
can automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

PP = VPPH1/2, the CUI additionally controls block

erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require
the command and address within the device
(Master Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 13 and
Fig. 14 illustrate WE# and CE#-controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing V

PPH1/2 on VPP enables

successful block erase, byte write and lock-bit
configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

FFFFF

F0004
F0003
F0002
F0001
F0000

1FFFF

10004
10003
10002
10001
10000
0FFFF

00004
00003
00002
00001
00000

Reserved for

Future Implementation

Block 15 Lock Configuration Code

Block 15

Block 1

Block 0

(Blocks 2 through 14)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Master Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code

- 9 -

LH28F008SC-V/SCH-V

- 10 -

MODE NOTE RP# CE# OE# WE#

ADDRESS

VPP DQ0-7 RY/BY#

Read 1, 2, 3, 8

VIHor VHHV

IL

V

IL

V

IH

XXD

OUT

X

Output Disable 3

VIHor VHHV

IL

V

IH

V

IH

X X High Z X

Standby 3

VIHor VHHV

IH

XXXXHigh Z X

Deep Power-Down 4 V

IL

XXXXXHigh Z V

OH

Read Identifier Codes 8

VIHor VHHV

IL

V

IL

V

IH

See Fig. 2

X(

NOTE 5)

V

OH

Write 3, 6, 7, 8

VIHor VHHV

IL

V

IH

V

IL

XXDINX

Table 2 Bus Operations

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

V

PPLK or VPPH1/2 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase, byte write, or lock-bit configuration
algorithms. It is V

OH during when the WSM is not busy,

in block erase suspend mode (with byte write inactive),
byte write suspend mode, or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. Command writes involving block erase, byte write, or
lock-bit configuration are reliably executed when V

PP =

V

PPH1/2 and VCC = VCC1/2. Block erase, byte write, or

lock-bit configuration with V

IH < RP# < VHH produce

spurious results and should not be attempted.

7. Refer to Table 3 for valid D

IN during a write operation.

8. Don

’t use the timing both OE# and WE# are VIL.

LH28F008SC-V/SCH-V

- 11 -

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
master lock codes. See Section 4.2 for read identifier
code data.

5. If the block is locked, RP# must be at V

HH to enable

block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is
V

IH.

6. Either 40H or 10H is recognized by the WSM as the
byte write setup.

7. If the master lock-bit is set, RP# must be at V

HH to set a

block lock-bit. RP# must be at V

HH to set the master

lock-bit. If the master lock-bit is not set, a block lock-bit
can be set while RP# is V

IH.

8. If the master lock-bit is set, RP# must be at V

HH to clear

block lock-bits. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the master
lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V

IH.

9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Byte Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Byte Write Suspend
Block Erase and

1 5 Write X D0H

Byte Write Resume
Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H
Set Master Lock-Bit 2 7 Write X 60H Write X F1H
Clear Block Lock-Bits 2 8 Write X 60H Write X D0H

Table 3 Command Definitions

(NOTE 9)

LH28F008SC-V/SCH-V

- 12 -

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, byte write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Byte
Write Suspend command. The Read Array
command functions independently of the V

PP

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

PP voltage and RP# can be

V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

NOTE :

1. X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory
map.

4.3 Read Status Register Command

The status register may be read to determine when
a block erase, byte write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
V

IH before further reads to update the status

register latch. The Read Status Register command
functions independently of the V

PP voltage. RP#

can be V

IH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or byte write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,

CODE ADDRESS DATA

Manufacture Code 00000H 89
Device Code 00001H A6
Block Lock Configuration

X0002H

(NOTE 1)

•Block is Unlocked DQ0 = 0

•Block is Locked DQ0 = 1

•Reserved for Future Use DQ1-7
Master Lock Configuration 00003H

•Device is Unlocked DQ0 = 0

•Device is Locked DQ0 = 1

•Reserved for Future Use DQ

1-7