®
PRODUCT SPECIFICATIONS
Integrated Circuits Group
LH28F008SCT-L12
Flash Memory
8M (1M ×8)
(Model No.: LHF08CH3)
Spec No.: EL104164B
Issue Date: May 7, 1999
SHARP
l
Handle this document carefully for it contains material protected by international
copyright law. Any reproduction, full or in part, of this material is prohibited without the
express written permission of the company.
l
When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
*Office electronics
*Instrumentation and measuring equipment
*Machine tools
@Audiovisual equipment
*Home appliance
*Communication equipment other than for trunk lines
LHF08CH3
(2) Those contemplating using the products covered herein for the following equipment
which demands hiqh reliabilitv, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
&ontrol and safety devices for airplanes, trains, automobiles,
transportation equipment
l
Mainframe computers
l
Traffic control systems
*Gas leak detectors and automatic cutoff devices
*Rescue and security equipment
mother safety devices and safety equipment,etc.
(3) Do not use the products covered herein for the following equipment which demands
extremelv hiqh performance in terms of functionality, reliability, or accuracy.
l
Aerospace equipment
*Communications equipment for trunk lines
*Control equipment for the nuclear power industry
@Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
and
other
l
Please direct all queries regarding the products covered herein to a sales representative
of the company.
Paw i 1
SHARI=
LHF08CH3
CONTENTS
PAGE
1.0 INTRODUCTION ...................................................
1.1 New Features..
1.2 Product Overview
2.0 PRINCIPLES OF OPERATION..
2.1 Data Protection ...................................................
3.0 BUS OPERATION .................................................
3.1 Read
3.2 Output Disable .................................................... 6
3.3 Standby ...............................................................
3.4 Deep Power-Down .............................................. 8
3.5 Read Identifier Codes
3.6 Write
4.0 COMMAND DEFINITIONS
4.1 Read Array Command.. ..................................... 12
4.2 Read Identifier Codes Command ...................... 12
4.3 Read Status Register Command.. ..................... 12
4.4 Clear Status Register Command..
4.5 Block Erase Command.. .................................... 12
4.6 Byte Write Command
4.7 Block Erase Suspend Command..
4.6 Byte Write Suspend Command.. .......................
4.9 Set Block and Master Lock-Bit Commands..
4.10 Clear Block Lock-Bits Command.. ................... 15
...................................................................
....................................................................
.................................................... 3
................................................
...........................
Operation.. ....................... 9
.................................... 9
.....................
........................................ 13
.....................
.....
3
5.0 DESIGN CONSIDERATIONS ............................. .23
5.1 Three-Line Output Control
3
7
7
a
a
a
9
12
13
14
14
5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit
Configuration Polling.. .........................................
5.3 Power Supply Decoupling.. ................................ 23
5.4 V,, Trace on Printed Circuit Boards..
5.5 v,,, v,,,
5.6 Power-Up/Down
5.7 Power Dissipation
6.0 ELECTRICAL SPECIFICATIONS..
6.1 Absolute Maximum Ratings ............................... 25
6.2 Operating Conditions
6.2.1 Capacitance ................................................. 25
6.2.2 AC Input/Output Test Conditions..
6.2.3 DC Characteristics
6.2.4 AC Characteristics - Read-Only Operations .29
6.2.5 AC Characteristics - Write Operations..
6.2.6 Alternative CE#-Controlled Writes.. .............
6.2.7 Reset Operations ......................................... 36
6.2.6 Block Erase, Byte Write and Lock-Bit
Configuration Performance ........................... 39
7.0 ADDITIONAL INFORMATION
7.1 Ordering Information
8.0 PACKAGE AND PACKING SPECIFICATIONS ..4 1
RP# Transitions.. .............................. .24
Protection..
.............................................. 24
................................
.............................
.....................
......................................... 25
........................................ 27
............................
.........................................
...............
...............
.......
1
PAGE
.23
23
.23
.24
.25
.26
.32
.35
.40
.40
Rev. 1.0
SHAi?P
LH28FOOSSCT-L12
8M-BIT (1 MB x 8)
SmartVoltage Flash MEMORY
n SmartVoltage Technology
-
2.7V(Read-Only), 3.3V or 5V Vcc
-
3.3V, 5V or 12V Vpp
n High-Performance Read Access Time
- 120ns(5V*0.5V), 150ns(3.3V*O.3V),
170ns(2.7V-3.6V)
n Operating Temperature
- 0°C to +7O”C
I High-Density Symmetrically-Blocked
Architecture
-
Sixteen 64K-byte Erasable Blocks
LHF08CH3
n Automated Byte Write and Block Erase
n Enhanced Automated Suspend Options
n Extended Cycling Capability
n SRAM-Compatible Write Interface
- Command User Interface
- Status Register
- Byte Write Suspend to Read
- Block Erase Suspend to Byte Write
-
Block Erase Suspend to Read
-
100,000 Block Erase Cycles
-
1.6 Million Block Erase Cycles/Chip
2
I Low Power Management
- Deep Power-Down Mode
-
Automatic Power Savings Mode
Decreases Ice in Static Mode
I Enhanced Data Protection Features
-
Absolute Protection with Vpp=GND
-
Flexible Block Locking
-
Block Erase/Byte Write Lockout
during Power Transitions
SHARP’s LH28F008SCT-L12 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile,
?ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCT-L12 offers three levels of protection: absolute protection with V,, at
ZND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.
The LH28F008SCT-L12 is manufactured on SHARP’s 0.38um ETOXTM process technology. It come in
ndustry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCT-L12 enables quick and easy upgrades for designs demanding the state-of-the-art.
n Industry-Standard Packaging
- 40-Lead TSOP
n ETOXTM* Nonvolatile Flash Techno
W CMOS Process
(P-type silicon substrate)
n Not designed or rated as radiation
hardened
WY
‘ETOX is a trademark of Intel Corporation.
Rev. 1.3
LHF08CH3
3
1 INTRODUCTION
This
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCT-L12
Flash
application notes and design tools which are
referenced in Section 7.
datasheet
memory documentation
contains LH28F008SCT-L12
also includes
1.1 New Features
The LH28F008SCT-L12 SmartVoltage Flash memory
maintains backwards-compatibility with SHARP’s
28F008SA. Key enhancements over the 28F008SA
include:
*SmartVoltage Technology
*Enhanced Suspend Capabilities
&r-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
28F008SA to LH28F008SCT-L12. When upgrading, it
is important to note the following differences:
*Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
l
VPPLK has been lowered from 6.5V to l.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V,, voltage
transitions to GND is recommended for designs
that switch V,, off during read operation.
*To take advantage of SmartVoltage technology,
allow V,, connection to 3.3V or 5V.
1.2 Product Overview
SmartVoltage technology provides a choice of Voc
and V,, combinations, as shown in Table 1, to mee
system performance and power expectations. 2.7\
V,, consumes approximately one-fifth the power o
5V Vo,. But, 5V Vco provides the highest reac
performance. V,,
for a separate 12V converter, while V,,=12\
maximizes block erase and byte write performance
In addition to flexible erase and program voltages
the dedicated V,, pin gives complete data protectior
when V,+V,,,,.
Table 1. Vc, and V,, Voltage Combinations
Offered by SmartVoltage Technology
Vr.r: Voltage
2.7V(‘)
-..
3.3v
I
NOTE:
1. Block erase, byte write and lock-bit configuratior
operations with V,o<3.OV are not supported.
Internal
automatically configures the device for optimizec
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and interna
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V V,,, 12V
VP,) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
VCC
at 3.3V and 5V eliminates the neec
Vpp Voltage
-
3.3v, 54, l2V
5V 5v. 12v
and
VP,
detection Circuitb
The LH28F008SCT-L12 is a high-performance 8M-bit
SmartVoltage Flash memory organized as 1 M-byte of
3 bits. The IM-byte of data is arranged in sixteen
SK-byte blocks which are individually erasable,
ockable, and unlockable in-system. The memory
nap is shown in Figure 3.
Writing memory data is performed in byte increments
typically within 6u.s (5V Vcc, 12V Vpp). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
Rev. 1.3
LHF08CH3
4
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
Jates block lock-bit modification.
zonfiguration operations (Set Block Lock-Bit, Set
Master Lock-Bit,
zommands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
iinished.
The RY/BY# output gives an additional indicator of
JVSM activity by providing both a hardware signal of
status (versus software polling) and status masking
iinterrupt masking for background block erase, for
mample). Status polling using RY/BY# minimizes
30th CPU overhead and system power consumption.
JVhen low, RY/BY# indicates that the WSM is
3erforming a block erase, byte write, or lock-bit
zonfiguration. RY/BY#-high indicates that the WSM is
,eady for a new command, block erase is suspended
:and byte write is inactive), byte write is suspended,
3r the device is in deep power-down mode.
and Clear Block Lock-Bits
Lock-bit
The access time is 120 ns (tAvav) over the
commercial temperature range (0% to +70”(Z) ant
Vc, supply voltage range of 4.5V-5.5V. At lower Vcc
voltages, the access times are 150 ns (3.OV-3.6V:
and 170 ns (2.7V-3.6V).
The Automatic Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I,,,
When CE# and RP# pins are at V,,, the I,, CMOS
standby mode is enabled. When the RP# pin is a
GND, deep power-down mode is enabled which
minimizes power consumption and provides write
protection during reset. A reset time (tpHQv) is
required from RP# switching high until outputs arc
valid. Likewise, the device has a wake time (t,,,,:
from RP#-high until writes to the CUI are recognized
With RP# at GND, the WSM is reset and the status
register is cleared.
The device is available in 40-lead TSOP (Thin Smal
Outline Package, 1.2 mm thick). Pinout is shown ir
Figure 2.
current is 1 mA at 5V V,,.
Rev.1.0
SHARP
LHF08CH3
5
49
Ale
A17
A16
AIS
A14
An
A12
CE#
vcc
VPP
RP#
41
Alo
As
43
A7
A6
A5
A4
Figure 1. Block Diagram
40-LEAD TSOP
STANDARD PINOUT
1 Omm x 20mm
TOP VIEW
Figure 2. TSOP 40-Lead Pinout
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
GND
GND
DQ3
DQ2
DQI
DQo
z
A2
A3
Rev. 1.0
SHARP
Rev.
1.0
r
r
Symbol
A,-Al
9
DQo-DQ7
CE#
RP#
OE#
WE#
RY/BY# OUTPUT
Vcc
GND
NC
OUTPUT
SUPPLY
SUPPLY
SUPPLY
Type
INPUT
INPUT/
INPUT
INPUT
INPUT
INPUT
LHF08CH3
Table 2. Pin Descriptions
T
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V,, enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP#=V,, overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with VIHcRP#<VHH produce spurious results and should not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With V,,<V,,Lk, memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V,, (see DC Characteristics) produce spurious results and should not be
attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V
operation. To switch from one voltage to another, ramp V,, down to GND and then ramp
Vco to the new voltage. Do not float any power pins. With Vcc<VLKO, all write attempts
to the flash memory are inhibited. Device operations at invalid Vco voltage (see DC
Characteristics) produce spurious results and should not be attempted. Block erase, byte
write and lock-bit configuration operations with Vrr<3.0V are not supported.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Name and Function
6
I
SHARP
LHF08CH3
2 PRINCIPLES OF OPERATION
The LH28F008SCT-L12 SmartVoltage Flash memory
includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with
RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V,, voltage. High
voltage on V,,
byte writing, and lock-bit configuration. All functions
associated with altering memory contents-block
erase, byte write, Lock-bit configuration, status, and
identifier codes-are accessed via the CUI and
verified through the status register.
Commands are
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, or outputs
status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates. After successful completion, reads are
again possible via the Read Array command. Block
erase suspend allows system software to suspend a
block erase to read or write data from any other
block. Byte write suspend allows system software to
suspend a byte write to read data from any other
flash memory array location.
enables successful block erasure,
written using
standard
7
FFFFF
FOOOO
EFFFF
EOOW
DFFFF
DO000
CFFFF
coooo
BFFFF
BOO00
AFFFF
AOOW
SFFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
SFFFF
50000
4FFFF
40000
JFFFF
30000
PFFFF
20000
1 FFFF
10000
OFFFF
FigUre 3. Memory Map
1 Data Protection
2:
Depending on the application, the system designer
may choose to make the V,, power supply
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to V,,,,,z13. The device
accommodates
either design practice
encourages optimization of the processor-memory
interface.
When Vpp~VppLK,
memory contents cannot be
altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V,,. All write
functions are disabled when Vcc is below the write
lockout voltage VLKO
or when RP# is at V,,. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.
and
Rev.1.3
SHARP
LHF08CH3 8
3 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, or status register independent of the V,,
voltage. RP# can be at either V,, or V,,.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ,-DQ,) control and when
active drives the selected memory data onto the I/O
bus. WE# must be at V,, and RP# must be at V,, or
V,,. Figure 15 illustrates a read cycle.
3.2 Output Disable
JVith OE# at a logic-high level (V,,), the device
outputs are disabled. Output pins DC+,-DQ, are
olaced in a high-impedance state.
3.3 Standby
ZE# at a logic-high level (VI,) places the device in
standby mode #which substantially reduces device
lower consumption. DQc-DQ, outputs are placed in
I high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
:onfiguration, the device continues functioning, and
consuming active power until the operatior
completes.
3.4 Deep Power-Down
RP# at V,, initiates the deep power-down mode.
In read modes, RP#-low deselects the memory
places output drivers in a high-impedance state ant
turns off all internal circuits. RP# must be held low fo
a minimum of 100 ns. Time tPHQv is required afte
return from power-down until initial memory acces:
outputs are valid. After this wake-up interval, norma
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase,
configuration modes,
operation. RY/BY# remains low until the rese
operation is complete. Memory contents beins
altered are no longer valid; the data may be partially
erased or written. Time tPHwL is requirod after RPB
goes to logic-high (V,,) before another command car
be written.
As with any automated device, it is important tc
assert RP# during system reset. When the systencomes out of reset, it expects to read from the flask
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU resei
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
,“;~low~ritell o;bo~ck;+;
Rev. 1.0
LHF08CH3 9
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code,
configuration codes for each block, and the master
lock configuration code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically match the device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
FFFFF
FOO04
FOO03
FOO02
Block 15 Lock Configuration Code
device code, block lock
Reserved for
Future Implementation
3.6 Write
Writing commands to the CUI enable reading 01
device data and identifier codes. They also control
inspection and clearing of the status register. When
VPP=VPPHli2/3~
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to 5s
erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require ths
command and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a commanc
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
the CUI additionally controls block
100021
Block 1 Lock Configuration Code
10001
10000
OFFFF
Master Lock Configuration Code
00002
00001~
Block 0 Lock Configuration Code
t
-----------------
L------------------------------------
Device Code
Manufacturer Code
Block (I
Figure 4. Device Identifier Code Memory Map
4 COMMAND DEFINITIONS
When the V,, voltage 5 V,,,,, Read operations
from the status register, identifier codes, or blocks
are enabled. Placing V,,,,,,, on V,, enables
successful block erase, byte write and lock-bii
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
L
RPV I n
SHARI=
LHF08CH3
10
Table 3. Bus Operations
Mode
Read
Output Disable
Standby 3
Notes RP# CE# OE# WE# Address VPP
1,2,3,8 VT Or
HH
3
“I, Or
Vr#
“I, Or
VHH
“IL “IL “I,
“IL “I, ‘1,
“I,
X X X X
Deep Power-Down 4 V,, X X X X
Read Identifier Codes 8
Write 3,6,7,8 “. Or
“I, Or
VHH
HH
“IL “IL vlH
“IL “I, “IL
See
Figure 4 ’
D&.-r
X X
DOUT
X X High Z
High Z X
X High Z Vn,,
Note 5
X X
DlN
RY/BY#
X
X
“OH
X
‘4OTES:
I. Refer to DC Characteristics. When Vpp<VppLK,
memory contents can be read, but not altered.
!. X can be VI, or VrH for control pins and addresses, and V,,,, or VPpHf/2/s for VP,. See DC Characteristics for
vPPLK and “PPHl12i3 voltaw
3. RY/BY# is V,, when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms.
It is VOH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write
suspend mode, or deep power-down mode.
C. RP# at GNDk0.2” ensures the lowest deep power-down current.
i. See Section 4.2 for read identifier code data.
i. Command writes involving block erase, write, or lock-bit configuration are reliably executed when Vpp=VppH1/2/3
and vCC=vCC2/3.
Block erase, byte write, or lock-bit configuration with V,c<3.OV or VrH<RP#<VHH produce
spurious results and should not be attempted.
‘. Refer to Table 4 for valid DIN during a write operation.
1. Don’t use the timing both OE# and WE# are VI,.
Rev. 1 .O
LHF08CH3
Table 4. Command Definit
Bus Cycles
Command
Read Array/Reset
11 Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Byte Write
II
id Byte Write
id Byte Write
Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
NOTES:
1. BUS operations are defined in Table 3.
2. X=Any valid address within the device.
IA=ldentifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and
master lock codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at V,,
block erase or byte write to a locked block while RP# is V,,.
Either 40H or 10H are recognized by the WSM as the byte write setup.
6.
If the master lock-bit is set, RP# must be at V,, to set a block lock-bit. RP# must be at V,, to set the master
7.
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is V,,.
8. If the master lock-bit is set, RP# must be at V,,
simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can
be done while RP# is VI,.
9. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rea’d. Notes Ooer(l) 1 Ad
1 1 Write 1 X 1
1 22 I 4 I Write I X
2
1
2
2
1
1 5 Write X DOH
2
2 7 Write X 60H Write X FlH
2 8 Write X 60H
5 Write BA 20H Write BA DOH
5,6
5
7
to enable block erase or byte write operations. Attempts to issue a
to clear block lock-bits. The clear block lock-bits operation
First B
, Jdr(2) 1 Data(“) Oper(‘)
Write X 70H Read
Write X 50H
Write WA
Write
I
Write BA
ions(g)
us Cycle
I
X
Second Bus Cycle
1 Addr12) 1 Datat3)
FFH
90H
40H
BOH
60H Write BA OlH
l&
I
Read
Write WA WD
Write X DOH
I
IA I ID /I
X SRD
1
Rev. 1.0
LHFOSCH3 12
4.1 Read Array Command 4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
Dower-down mode, the device defaults to read array
node. This operation is also initiated by writing the
Read Array command. The device remains enabled
‘or reads until another command is written. Once the
nternal WSM has started a block erase, byte write or
ock-bit configuration, the device will not recognize
:he Read Array command until the WSM completes
ts operation unless the WSM is suspended via an
Erase Suspend or Byte Write Suspend command.
The Read Array command functions independently of
:he V,, voltage and RP# can be VI, or V,,.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
qead Identifier Codes command. Following the
:ommand write, read cycles from addresses shown in
=igure 4 retrieve the manufacturer, device, block lock
:onfiguration and master lock configuration codes
see Table 5 for identifier code values). To terminate
:he operation, write another valid command. Like the
?ead Array command, the Read Identifier Codes
:ommand functions independently of the V,, voltage
lnd RP# can be V,,
dentifier Codes command, the following information
:an be read:
Table 5. Identifier Codes
or V,,. Following the Read
The status register may be read to determine when E
block erase, byte write, or lock-bit configuration i:
complete and whether the operation completec
successfully. It may be read at any time by writing the
Read Status Register command. After writing this
command, all subsequent read operations outpu
data from the status register until another valic
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to VI, before further
reads to update the status register latch. The Reac
Status Register command functions independently o’
the V,, voltage. RP# can be V,, or V,,.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.l are
set to “1”s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 7). By allowing
system software to reset these bits, severa
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence:
may be performed. The status register may be pollee
to determine if an error occurre during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied V,, Voltage. RP# can be VI, or V,,.
This command is not functional during block erase or
byte write suspend modes.
*Block is Unlocked
@Block is Locked
*Reserved for Future Use
Master Lock Configuration
*Device is Unlocked
ODevice is Locked
*Reserved for Future Use
4OTE:
. X selects the specific block lock configuration
code to be read. See Figure 4 for the device
identifier code memory map.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by
a two-cycle command. A block erase setup is first
written, followed by an block erase confirm. This
command sequence requires appropriate sequencing
and an address within the block to be erased (erase
changes all block data to FFH). Block
preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle block erase sequence is written, the
device automatically outputs status register data
when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
Rev. 1.0
LHF08CH3 13
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to “1 ‘I. Also, reliable block erasure
can only occur when Vcc=Vcc2,s and Vpp=VppH1,2,3.
In the absence of this high voltage, block contents
are protected against erasure. If block erase is
attempted while V,,IV,,,k, SR.3 and SR.5 will be
set to “1 ‘I. Successful block erase requires that the
corresponding block lock-bit be cleared or, if set, that
RP#=V,,. If block erase is attempted when the
corresponding block lock-bit is set and RP#=V,,,
SR.l and SR.5 will be set to “1”. Block erase
operations with V,,<RP#CV,~ produce spurious
,esults and should not be attempted.
4.6 Byte Write Command
3yte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write
:hat specifies the address and data (latched on the
ising edge of WE#). The WSM then takes over,
:ontrolling the byte write and write verify algorithms
nternally. After the byte write sequence is written, the
device automatically outputs status register data
Nhen read (see Figure 6). The CPU can detect the
:ompletion of the byte write event by analyzing the
qY/BY# pin or status register bit SR.7.
Nhen byte write is complete, status register bit SR.4
;hould be checked. If byte write error is detected, the
;tatus register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
;uccessfully write to “0%. The CUI remains in read
;tatus register mode until it receives another
:ommand.
qeliable byte writes can only occur when Vcc=Vcc2/s
Ind VPP=VPPH1/2/3-
loltage, memory contents are protected against byte
vrites. If byte write is attempted while Vpp~Vpp,,,
status register bits SR.3 and SR.4 will be set to “1”.
juccessful byte write requires that the corresponding
In the absence of this high
block lock-bit be cleared or, if set, that RP#=VHH. I
byte write is attempted when the corresponding bloc1
lock-bit is set and RP#=VrH, SR.l and SR.4 will bc
set to “1 ‘I. Byte write operations with VrH<RP#<Vr+
produce spurious results and should not bt
attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allow:
block-erase interruption to read or byte-write data ir
another block of memory. Once the block-erase
process starts, writing the Block Erase Suspenc
command requests that the WSM suspend the bloc+
erase sequence at a predetermined point in the
algorithm. The device outputs status register dat:
when read after the Block Erase Suspend commanc
is written. Polling status register bits SR.7 and SR.E
can determine when the block erase operation ha:
been suspended (both will be set to “1”). RY/BY# wil
also transition to VOH. Specification twHr$+ defines
the block erase suspend latency.
At this point, a Read Array command can be writter
to read data from blocks other than that which is
suspended. A Byte Write command sequence caralso be issued during erase suspend to program data
in other blocks. Using the Byte Write Suspenc
command (see Section 4.8), a byte write operation
can also be suspended. During a byte write operation
with block erase suspended, status register bit SR.7
will return to “0” and the RY/BY# output will transition
to V,,. However, SR.6 will remain “1” to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and
RY/BY# will return to V,,. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 7). VP,
must remain at VppHr,2/3 (the same Vpp level used
for block erase) while block erase is suspended. RP#
must also remain at VrH or VHH (the same RP# level
used for block erase). Block erase cannot resume
until byte write operations initiated during block erase
suspend have completed.
Rev. 1.0
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