SGS Thomson Microelectronics WS27C256L Datasheet
PRODUCT SELECTION GUIDE
PARAMETER WS27C256L-12 WS27C256L-15 WS27C256L-20
Address Access Time (Max) 120 ns 150 ns 200 ns
Chip Select Time (Max) 120 ns 150 ns 200 ns
Output Enable Time (Max) 35 ns 40 ns 40 ns
WS27C256L
TOP VIEW
Chip Carrier CERDIP
PIN CONFIGURATION
4-19
Military 32K x 8 CMOS EPROM
KEY FEATURES
• High Performance CMOS • Ceramic Leadless Chip Carrier (CLLCC)
— 120 ns Access Time
• EPI Processing
• Fast Programming
— Latch-Up Immunity to 200 mA
• DESC SMD No. 5962-86063
— ESD Protection Exceeds 2000 Volts
• 300 Mil DIP or Standard 600 Mil DIP • JEDEC Standard Pin Configuration
GENERAL DESCRIPTION
The WS27C256L is a performance oriented 256K UV Erasable Electrically Programmable Read Only Memory
organized as 32K words x 8 bits/word. It is manufactured using an advanced CMOS technology which enables it to
operate at speeds up to 120 nsecs. The memory was designed utilizing WSI's patented self-aligned split gate
EPROM cell, resulting in a low power device with a very cost effective die size.
The WS27C256L 256K EPROM provides 32K of 8 bit wide code store capacity for DSP, microprocessor, and
microcontroller-based systems. Its 120 nsec access time over the full Military temperature range provides the
potential of no-wait state operation. And where this parameter is important, the WS27C256L provides the user with
a very fast 35 nsec TOEoutput enable time.
The WS27C256L is offered in a 28 pin 300 mil skinny CERDIP or the standard 600 mil CERDIP, and also in a
32 pad Ceramic Leadless Chip Carrier (CLLCC) for surface mount applications. All packages incorporate the
standard JEDEC EPROM pinout.
A
8
A
9
A
11
NC
OE
A
10
CE/PGM
O
7
O
6
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
A7A12VPPNC
VCCA14A
13
O1 O2 NC O3 O4 O
5
1
432
32 31
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
14 15 1617181920
GND
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE/PGM
O
7
O
6
O
5
O
4
O
3
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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AC READ CHARACTERISTICS
Over Operating Range (See Above)
SYMBOL PARAMETER
WS27C256L-12 WS27C256L-15 WS27C256L-20
UNITS
MIN MAX MIN MAX MIN MAX
t
ACC
Address to Output Delay 120 150 200
t
CE
CE to Output Delay 120 150 200
t
OE
OE to Output Delay 35 40 40
t
DF
Output Disable to Output Float
35 40 40
ns
(Note 3)
Output Hold From Addresses,
t
OH
CE or OE, Whichever Occurred 0 0 0
First (Note 3)
DC READ CHARACTERISTICS
Over Operating Range. (See Above)
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS
V
IL
Input Low Voltage –0.5 0.8 V
V
IH
Input High Voltage 2.0 V
CC
+ 1 V
V
OL
Output Low Voltage IOL= 2.1 mA 0.4 V
V
OH
Output High Voltage IOH= –400 µA 3.5 V
I
SB1
VCCStandby Current (CMOS) CE = V
CC
± 0.3 V (Note 2) 100 µA
I
SB2
VCCStandby Current CE = V
IH
1mA
ICCVCCActive Current
CE = OE = V
IL
F = 5 MHz 40 mA
(Note 1)
F = 8 MHz 50 mA
I
PP
VPPSupply Current VPP= V
CC
100 µA
V
PP
V
PP
Read Voltage V
CC
–0.4 V
CC
V
I
LI
Input Leakage Current VIN= 5.5 V or Gnd –10 10 µA
I
LO
Output Leakage Current V
OUT
= 5.5 V or Gnd –10 10 µA
WS27C256L
4-20
OPERATING RANGE
RANGE TEMPERATURE V
CC
Military –55°C to +125°C +5V ± 10%
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature............................–65° to + 150°C
Voltage on any Pin with
Respect to Ground ....................................–0.6V to +7V
VPPwith Respect to Ground...................–0.6V to + 14V
V
CC
Supply Voltage with
Respect to Ground ....................................–0.6V to +7V
ESD Protection..................................................>2000V
NOTES: 1. The supply current is the sum of I
CC
and IPP. The maximum current value is with Outputs O0to O7unloaded.
2. CMOS inputs: VIL= GND ± 0.3V, VIH= VCC± 0.3 V.
*
NOTICE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
NOTE: 3.
This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing
diagram.
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