SGS Thomson Microelectronics VNV20N07, VNP20N07FI, VNB20N07 Datasheet

VNP20N07FI

VNB20N07/VNV20N07

”OMNIFET”:

FULLY AUTOPROTECTED POWER MOSFET

June 1998

BLOCK DIAGRAM (∗)

TYPE V

clamp

R

DS(on)

I

lim

VNP20N07FI
VNB20N07
VNV20N07

70 V
70 V
70 V

0.05 Ω

0.05 Ω

0.05 Ω

20 A
20 A
20 A

■ LINEAR CURRENT LIMITATION

■ THERMALSHUTDOWN

■ SHORT CIRCUIT PROTECTION

■ INTEGRATEDCLAMP

■ LOW CURRENT DRAWN FROM INPUT PIN

■ DIAGNOSTICFEEDBACKTHROUGH INPUT

PIN

■ ESD PROTECTION

■ DIRECT ACCESS TO THE GATE OF THE

POWERMOSFET(ANALOGDRIVING)

■ COMPATIBLEWITHSTANDARD POWER

MOSFET

DESCRIPTION

The VNP20N07FI, VNB20N07 and VNV20N07
are monolithic devices made using
STMicroelectronics VlPower M0 Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications. Built-in
thermal shut-down, linear current limitation and
overvoltage clamp protect the chip in harsh

enviroments.
Faultfeedback can be detected by monitoring the

voltageat the input pin.

1

10

PowerSO-10

1

2

3

1

3

D2PAK
TO-263

ISOWATT220

(∗) PowerSO-10 PinConfiguration : INPUT = 6,7,8,9,10; SOURCE = 1,2,4,5; DRAIN = TAB



1/13

ABSOLUTEMAXIMUMRATING

Symbol Parameter Value Unit

Po w erSO-10

D2PAK

ISOWATT220

V

DS

Drain-source Voltage (Vin= 0 ) Int er nall y Clamped V

V

in

Input V ol ta ge 18 V

I

D

Drain Current Internally Limited A

I

R

Reverse DC O utput Current -28 A

V

esd

Elect r o st at ic Disc harge (C= 100 pF , R=1. 5 KΩ) 2000 V

P

tot

Tot al Dis s ipation at Tc=25oC8334W

T

j

Oper at i ng Junct ion T em perature Internally Limit ed

o

C

T

c

Case Operating Temperature Internally Limited

o

C

T

stg

St orage Temperat ure -55 to 150

o

C

THERMAL DATA

IS O WATT220 Po werSO-10 D2PA K

R

thj-case

R

thj-amb

Ther mal Resist an ce Juncti on-c ase Max
Ther mal Resist an ce Juncti on-am b ient M a x

3.75

62.5

1.5
50

1.5

62.5

o

C/W

o

C/W

ELECTRICAL CHARACTERISTICS (T

case

=25oC unlessotherwise specified)

OFF

Symbol Parameter Test Condition s Min. Typ. Max. Unit

V

CLAMP

Drain-source Clamp
Volt age

ID= 200 mA Vin= 0 60 70 80 V

V

CLTH

Drain-source Clamp
Thr eshold Vol ta ge

ID=2mA Vin=0 55 V

V

INCL

Input-Source Reverse
Clamp Voltage

Iin=-1mA -1 -0.3 V

I

DSS

Zer o Inpu t V olt ag e
Drain Current (V

in

=0)

V

DS

=13V Vin=0

V

DS

=25V Vin=0

50

200

µA
µA

I

ISS

Supply Current f rom
Input Pin

VDS=0V Vin= 10 V 250 5 00 µA

ON (∗)

Symbol Parameter Test Condition s Min. Typ. Max. Unit

V

IN(th)

Input T hreshold
Volt age

VDS=VinID+Iin=1mA 0.8 3 V

R

DS(on)

St at ic D rain- s our ce On
Resistance

Vin=10V ID=10A
V

in

=5V ID=10A

0.05

0.07

Ω
Ω

DYNAMIC

Symbol Parameter Test Condition s Min. Typ. Max. Unit

g

fs

(∗)Forward

Tr ansc on ductance

VDS=13V ID=10A 13 17 S

C

oss

Out put Capacit anc e VDS=13V f=1MHz Vin= 0 500 8 00 pF

VNP20N07FI-VNB20N07-VNV20N07

2/13

ELECTRICAL CHARACTERISTICS (continued)
SWITCHING(∗∗)

Symbol Parameter Test Condition s Min. Typ. Max. Unit

t

d(on)

t

r

t

d(off)

t

f

Turn-on Delay Time
Rise T ime
Turn-off Delay Time
Fall T ime

VDD=15V Id=10A
V

gen

=10V R

gen

=10Ω

(see figure 3)

90
240
430
150

180
400
800
300

ns
ns
ns
ns

t

d(on)

t

r

t

d(off)

t

f

Turn-on Delay Time
Rise T ime
Turn-off Delay Time
Fall T ime

VDD=15V Id=10A
V

gen

=10V R

gen

= 1000 Ω

(see figure 3)

800

1.5
6

3.5

1200

2.2
10

5.5

ns

µs
µs
µs

(di/dt)

on

Tur n-on Current Slope VDD=15V ID=10A

V

in

=10V R

gen

=10Ω

60 A/µs

Q

i

Total Input Charge VDD=12V ID=10A Vin= 10 V 60 nC

SOURCE DRAIN DIODE

Symbol Parameter Test Condition s Min. Typ. Max. Unit

V

SD

(∗)ForwardOnVoltage ISD=10A Vin=0 1.6 V

t

rr

(∗∗)

Q

rr

(∗∗)

I

RRM

(∗∗)

Reverse Recov ery
Time
Reverse Recov ery
Charge
Reverse Recov ery
Current

I

SD

= 10 A di/dt = 100 A/µs

V

DD

=30V Tj=25oC

(see test circuit, figure 5)

165

0.55

6.5

ns

µC

A

PROTECTION

Symbol Parameter Test Condition s Min. Typ. Max. Unit

I

lim

Drain Cur rent Lim it Vin=10V VDS=13V

V

in

=5V VDS=13V

14
14

20
20

28
28

A
A

t

dlim

(∗∗) Step Res pon se

Current Lim it

Vin=10V
V

in

=5V

29
70

60

140

µs
µs

T

jsh

(∗∗) O vert emperatu r e

Shut dow n

150

o

C

T

jrs

(∗∗) Ov ert emperat u re Reset 135

o

C

I

gf

(∗∗) Fault Sink Current Vin=10V

V

in

=5V

50
20

mA
mA

E

as

(∗∗) Single Puls e

Avalanche Energy

starting Tj=25oCVDD=20V
V

in

=10V R

gen

=1KΩ L=10mH

0.95 J

(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(∗∗) Parameters guaranteed by design/characterization

VNP20N07FI-VNB20N07-VNV20N07

3/13

During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (I

iss

) flows into the Input pin in order to

supplythe internalcircuitry.
The device integrates:

- OVERVOLTAGE CLAMP PROTECTION:

internally set at 70V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductiveloads.

- LINEAR CURRENT LIMITER CIRCUIT: limits

the drain current Id to Ilim whatever the Input
pin voltage. When the current limiter is active,
the device operates in the linear region, so
power dissipation may exceed the capability of
the heatsink. Both case and junction
temperatures increase, and if this phase lasts
long enough, junction temperature may reach
the overtemperaturethresholdT

jsh

.

- OVERTEMPERATURE AND SHORT CIRCUIT

PROTECTION: these are based on sensing
the chip temperatureand are not dependent on
the input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast, accurate detection of the junction
temperature. Overtemperaturecutout occurs at
minimum 150

o

C. The device is automatically
restarted when the chip temperature falls
below135

o

C.

- STATUS FEEDBACK: In the case of an

overtemperature fault condition, a Status
Feedback is provided through the Input pin.
The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.

Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit (witha small increasein R

DS(on)

).

PROTECTION FEATURES

VNP20N07FI-VNB20N07-VNV20N07

4/13