SGS Thomson Microelectronics UPSD3254BV, UPSD3254B, UPSD3254A, UPSD3254, UPSD3253BV Datasheet

...
1/175September 2003
Rev. 1.2
UPSD3254A, UPSD3254BV UPSD3253B, UPSD3253BV
Flash P rogram mable System Devi ces
with 8032 Microcontroller Core
FEATURES SUMMARY
The uPSD325X devices combi ne a Flash PSD
dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervi­sory functions and access via USB, I
2
C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the uPSD325X devices are also in-system pro­grammable (ISP) via a JTAG ISP interface.
Large 32KByte SRAM with battery back-up
option
Dual bank Flash memories
– 128KByte or 256KByte main Flash memory – 32KByte secondary Flash memory
Content Security
– Block access to Flash memory
Programmable Decode PLD for flexible address
mapping of all memories within 8032 space.
High-speed clock standard 8032 core (12-cycle)
USB Interface (some devices only)
I
2
C interface for peripheral connections
5 Pulse Width Modulator (PWM) channels
Analog-to-Digital Converter (ADC)
Standalone Display Data Channel (DDC)
Six I/O ports with up to 46 I/O pin s
3000 gate PLD with 16 macrocells
Supervisor functions with Watchdog Timer
In-System Programming (ISP) via JTAG
Zero-Power Technology
Single Supply Voltage
– 4.5 to 5.5V – 3.0 to 3.6V
Figure 1. 52-lead, Thin, Quad, Flat Package
Figure 2. 80-lead, Thin, Quad, Flat Package
TQFP52 (T)
TQFP80 (U)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
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TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
uPSD325X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
XRAM-DDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Indexed Addressing (Figure 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Arithmetic Instructions (Table 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data T r a nsfe r In s truc tions th a t Acces s Intern al Da ta Memo r y Space (Table 6.) . . . . . . . . . . . . . . 25
Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.) . . . . . . . 26
Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 26
Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data T r a nsfe r In s truc tion tha t Acce ss Externa l Data M e mory S p a c e ( T a b le 10.) . . . . . . . . . . . . . . 27
Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Boolean Instructions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Unconditional Jump Instructions (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
State Sequence in uPSD325X Devices (Figure 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
uPSD325X HARDWARE DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
uPSD325X devices Functional Modules (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
SFR Memory Map (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
List of all SFR (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PSD Module Register Address Offset (Table 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
External Int0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I2C Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
External Int1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DDC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0
USB Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0
USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt System (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SFR Register (Table 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt Priority Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Priority Levels (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Description of the IE Bits (Table 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Description of the IEA Bits (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3
Description of the IP Bits (Table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Description of the IPA Bits (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3
How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Vector Addresses (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
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POWER-SAVING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power-Saving Mode Power Consum ption (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5
Pin Status During Idle and Power-down Mode (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Description of the PCON Bits (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I/O Port Functions (Table 28.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
P1SFS (91H) (Table 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
P3SFS (93H) (Table 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
P4SFS (94H) (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PORT Type and Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8
PORT Type and Description (Part 1) (Figure 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PORT Type and Description (Part 2) (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Oscilla t or (Fig ur e 1 9. ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SUPERVISORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RESET Configuration (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Watchdog Timer Key Register (WDKEY: 0AEH) (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Description of the WDKEY Bits (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
RESET Pulse Width (Figure 21.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3
Watchdog Timer Clear Register (WDRST: 0A6H) (Table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Description of the WDRST Bits (Table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
Control Register (TCON) (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
Description of the TCON Bits (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
TMOD Register (TMOD) (Table 38.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Description of the TMOD Bits (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Timer/Counter Mode 0: 13-bit Counter (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timer/Counter Mode 2: 8-bit Auto-reload (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Timer/Counter Mode 3: Two 8-bit Counters (Figure 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Timer/Counter 2 Control Register (T2CON) (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Description of the T2CON Bits (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Timer/Counter2 Operating Modes (Table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Timer 2 in Capture Mode (Figure 25.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Timer 2 in Auto-Reload Mode (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Multiprocesso r Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Serial Port Mode 0, Waveforms (Figure 28.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Serial Port Mode 1, Waveforms (Figure 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial Port Mode 2, Waveforms (Figure 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Serial Port Mode 3, Waveforms (Figure 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1
A/D Block Diagram (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2
PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Four-Channel 8-bit PWM Block Diagram (Figure 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PWM SFR Memory Map (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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Programmable Period 8-bit PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PWM 4 With Programmable Pulse Width and Frequenc y (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 77
I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Block Diagram of the I2C Bus Serial I/O (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Serial Control Register (SxCON: S1CON, S2CON) (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Description of the SxCON Bits (Table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Selection of the Serial Clock Frequency SCL in Master Mode (Table 52.) . . . . . . . . . . . . . . . . . . . 79
Serial Status Register (SxSTA: S1STA, S2STA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Data Shift Register (SxDAT: S1DAT, S2DAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Serial Status Register (SxSTA) (Table 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Description of the SxSTA Bits (Table 54.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Data Shift Register (SxDAT: S1DAT, S2DAT) (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Address Register (SxADR: S1ADR, S2ADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Address Register (SxADR) (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP) (Table 57.). . . . . . . . . . . . . . . . 81
System Cock of 40MHz (Table 58.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
System Clock Setup Examples (Table 59.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DDC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2
DDC Interface Block Diagram (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Special Function Register for the DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DDC SFR Memory Map (Table 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Description of the DDCON Register Bits (Table 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SWNEB Bit Function (Table 62.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Host Type Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Host Type Detection (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6
DDC1 Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Transmission Protocol in the DDC1 Interface (Figure 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DDC2B Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Conceptual Structure of the DDC Interface (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
USB HARDWARE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
USB Address Register (UADR: 0EEh) (Table 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Description of the UADR Bits (Table 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
USB Interrupt Enable Register (UIEN: 0E9h) (Table 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Description of the UIEN Bits (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
USB Interrupt Status Register (UISTA: 0E8h) (Table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Description of the UISTA Bits (Table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
USB Endpoint0 Transmit Control Register (UCON0: 0EAh) (Table 69.). . . . . . . . . . . . . . . . . . . . . 92
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Description of the UCON0 Bits (Table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) (Table 71.). . . . . . . . . . . . . . . 93
Description of the UCON1 Bits (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
USB Control Register (UCON2: 0ECh) (Table 73.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Description of the UCON2 Bits (Table 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
USB Endpoint0 Status Register (USTA: 0EDh) (Table 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Description of the USTA Bits (Table 76.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
USB Endpoint0 Data Receive Register (UDR0: 0EFh) (Table 77.) . . . . . . . . . . . . . . . . . . . . . . . . . 94
USB Endpoint0 Data Transmit Register (UDT0: 0E7h) (Table 78.) . . . . . . . . . . . . . . . . . . . . . . . . 94
USB Endpoint1 Data Transmit Register (UDT1: 0E6h) (Table 79.) . . . . . . . . . . . . . . . . . . . . . . . . 94
USB SFR Memory Map (Table 80.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6
Low Speed Driver Signal Waveforms (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Differential Input Sensitivity Over Entire Common Mode Range (Figure 45.) . . . . . . . . . . . . . . . . . 97
External USB Pull-Up Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8
USB Data Signal Timing and Voltage Levels (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Receiver Jitter Tolerance (Figure 47.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Differential to EOP Transition Skew and EOP Width (Figure 48.). . . . . . . . . . . . . . . . . . . . . . . . . . 99
Differential Data Jitter (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Transceiver DC Characteristics (Table 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Transceiver AC Characteristics (Table 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PSD MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 1
PSD MODULE Block Diagram (Figure 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Methods of Programming Different Functional Blocks of the PSD MODULE (Table 83.). . . . . . . 103
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PSDsoft Express Development Tool (Figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . 105
Register Address Offset (Table 84.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Primary Flash Memo ry and Seco nd ary Flash memo ry Descr iption . . . . . . . . . . . . . . . . . . . . 106
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Instructions (Table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Status Bit (Table 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Data Polling Flowchart (Figure 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Data Toggle Flowchart (Figure 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Sector Protection/Security Bit Definition – Flash Protection Register (Table 87.). . . . . . . . . . . . . 114
Sector Protection/Security Bit Definition – Secondary Flash Protection Register (Note: 1.) . . . . . 114
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Sector Select and SRAM Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Priority Level of Memory and I/O Components in the PSD MODULE (Figure 54.) . . . . . . . . . . . . 116
VM Register (Table 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Separate Space Mode (Figure 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Combined Space Mode (Figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Page Register (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
DPLD and CPLD Inputs (Table 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
The Turbo Bit in PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLD Diagram (Figure 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 0
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
DPLD Logic Array (Figure 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2
Macrocell and I/O Port (Figure 60.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Output Macrocell Port and Data Bit Assignments (Table 90.). . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4
CPLD Output Macrocell (Figure 61.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Input Macrocell (Figure 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 6
General I/O Port Architecture (Figure 63.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Address Ou t Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
JTAG In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Peripheral I/O Mode (Figure 64.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Port Operating Modes (Table 91.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Port Operating Mode Settings (Table 92.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O Port Latched Address Output Assignments (Table 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Port Configuration Registers (PCR) (Table 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Port Pin Direction Control, Output Enable P.T. Not Defined (Table 95.). . . . . . . . . . . . . . . . . . . . 129
Port Pin Direction Control, Output Enable P.T. Defined (Table 96.) . . . . . . . . . . . . . . . . . . . . . . . 129
Port Direction Assignment Example (Table 97.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Drive Register Pin Assignment (Table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Port A and Port B Structure (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Port C Structure (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Port D Structure (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Port D External Chip Select Signals (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
APD Unit (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Enable Power-down Flow Chart (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Power-down Mode’s Effect on Ports (Table 100.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Power Managemen t Mode Registers PMMR0 (Table 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Power Managemen t Mode Registers PMMR2 (Table 102.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
APD Counter Operation (Table 103.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reset of Flash Memory Erase an d Program Cycle s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reset (RESET) Timing (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Status During Power-on RESET, Warm RESET and Power- d o w n Mod e (Table 104.). . . . . . . . . 140
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
10/175
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 141
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
JTAG Port Signals (Table 105.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
PLD ICC /Frequency Consumption (5V range) (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
PLD ICC /Frequency Consumption (3V range) (Figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
PSD MODULE Example, Typ. Power Calculation at V
CC
= 5.0V (Turbo Mode Off) (Table 106.). 143
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Absolute Maximum Ratings (Table 107.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Operating Conditions (5V Devices) (Table 108.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Operating Conditions (3V Devices) (Table 109.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
AC Symbols for Timing (Table 110.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Switching Waveforms – Key (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
DC Characteristics (5V Devices) (Table 111.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
DC Characteristics (3V Devices) (Table 112.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
External Program Memory READ Cycle (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
External Program Memory AC Characteristics (with the 5V MCU Module) (Table 113.) . . . . . . . 151
External Program Memory AC Characteristics (with the 3V MCU Module) (Table 114.) . . . . . . . 152
External Clock Drive (with the 5V MCU Module) (Table 115.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
External Clock Drive (with the 3V MCU Module) (Table 116.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
External Data Memory READ Cycle (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
External Data Memory WRITE Cycle (Figure 77.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
External Data Memory AC Characteristics (with the 5V MCU Module) (Table 117.). . . . . . . . . . . 154
External Data Memory AC Characteristics (with the 3V MCU Module) (Table 118.). . . . . . . . . . . 155
A/D Analog Specification (Table 119.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Input to Output Disable / Enable (Figure 78.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CPLD Combinatorial Timing (5V Devices) (Table 120.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CPLD Combinatorial Timing (3V Devices) (Table 121.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Synchronous Clock Mode Timing – PLD (Figure 79.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
CPLD Macrocell Synch ronous C lock Mode Timi ng (5V Devices) (Table 122.). . . . . . . . . . . . . . . 157
CPLD Macrocell Synch ronous C lock Mode Timi ng (3V Devices) (Table 123.). . . . . . . . . . . . . . . 158
Asynchronous RESET / Preset (Figure 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous Clock Mode Timing (product term clock) (Figure 81.) . . . . . . . . . . . . . . . . . . . . . . 159
CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) (Table 124.). . . . . . . . . . . . . . 159
CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) (Table 125.). . . . . . . . . . . . . . 160
Input Macrocell Timing (product term clock) (Figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Input Macrocell Timing (5V Devices) (Table 126.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Input Macrocell Timing (3V Devices) (Table 127.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Program, WRITE and Erase Times (5V Devices) (Table 128.). . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Program, WRITE and Erase Times (3V Devices) (Table 129.). . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Peripheral I/O READ Timing (Figure 83.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Port A Peripheral Data Mode READ Timing (5V Devices) (Table 130.) . . . . . . . . . . . . . . . . . . . . 163
Port A Peripheral Data Mode READ Timing (3V Devices) (Table 131.) . . . . . . . . . . . . . . . . . . . . 163
Peripheral I/O WRITE Timing (Figure 84.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Port A Peripheral Data Mode WRITE Timing (5V Devices) (Table 132.) . . . . . . . . . . . . . . . . . . .164
Port A Peripheral Data Mode WRITE Timing (3V Devices) (Table 133.) . . . . . . . . . . . . . . . . . . .164
Reset (RESET) Timing (Figure 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Reset (RESET) Timing (5V Devices) (Table 134.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Reset (RESET) Timing (3V Devices) (Table 135.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
V
STBYON
Definitions Timing (5V Devices) (Table 136.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
V
STBYON
Timing (3V Devices) (Table 137.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ISC Timing (Figure 86.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ISC Timing (5V Devices) (Table 138.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ISC Timing (3V Devices) (Table 139.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
MCU Module AC Measurement I/O Wavef orm (Figure 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
PSD MODULE AC Float I/O Waveform (Figure 88.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
External Clock Cycle (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Recommended Oscillator Circuits (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
PSD MODULE AC Measurement I/O Waveform (Figure 91.). . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
PSD MODULE AC Measurem ent Load Circuit (Figure 92.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Capacitance (Table 140.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
12/175
SUMMARY DESCRIPTION
Dual bank Flash memories
– Concurrent operation, read from memory
while erasing and writing the other. In-Appli­cation Programming (IAP) for remote updates
– Large 128KByte or 256KByte main Flash
memory for applicat ion code, operating sys­tems, or bit maps for graphic user interfaces
– Large 32KByte secondary Flash memory di-
vided in small sectors. Eliminate external EE­PROM with software EEPRO M emu la tion
– Secondary Flash memory is large enough for
sophisticated comm unication protocol (USB) during IAP while continuing critical system tasks
Large SRAM with battery back-up option
– 32KByte SRAM for RTOS, high-level lan-
guages, communication buffers, and stacks
Programmable Decode PLD for flexible address
mapping of all memories – Place individua l Flash and SRAM s ectors on
any address boundary
– Built-in page register breaks restrictive 8 032
limit of 64KByte address space
– Special register swaps Flash memory seg-
ments between 8032 “program” space and “data” space for efficient In-Application Pro­gramming
High-speed clock standard 8032 core (12-cycle)
– 40MHz operation at 5V, 24MHz at 3.3V – 2 UARTs wi th independent baud rate, three
16-bit Timer/Counters and two External Inter­rupts
USB Interface (some devices only)
– Supports USB 1.1 Slow Mode (1.5Mbit/s) – Control endpoin t 0 and interrupt endpoints 1
and 2
I
2
C interface for peripheral connections
– Capable of maste r or slave operation
5 Pulse Width Modulator (PWM) channels
– Four 8-bit PWM units – One 8-bit PWM unit with programmable peri-
od
4-channel, 8-bit Analog-to-Digital Converter
(ADC) with analog supply voltage (V
REF
)
Standalone Display Data Channel (DDC)
– For use in monitor, projector, and TV applica-
tions
– Compliant with VESA standards DDC1 and
DDC2B
– Eliminate external DDC PROM
Six I/O ports with up to 46 I/O pins
– Multifunction I/O: GPIO, DDC, I
2
C, PWM,
PLD I/O, supervisor, and JTAG
– Eliminates need for external latches and logic
3000 gate PLD with 16 macrocells
– Create glue logic, state machines, delays,
etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software...Free
Supervisor functions
– Generates res et upon low voltage or watch-
dog time-out. Eliminate external supervisor
device – RESET
Input pin; Reset output via PLD
In-System Programming (ISP) via JTAG
– Program entire chip in 10 - 25 seconds with
no involvement of 8032 – Allows efficient manu facturing, easy product
testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINK
TM
cable and any PC
Content Security
– Programmable Security Bit blocks access of
device programmers and readers
Zero-Power Technology
– Memories and PLD automatically reach
standby current between input changes
Packages
– 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/
data/control signals for connecting to external
peripherals
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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Table 1. uPSD325X Devices Product Matrix
Figure 3. TQ FP 5 2 C on ne ct i ons
Note: 1. Pull-u p re si stor re quired on pin 5 (2k for 3V devices, 7.5k for 5V devi ces) for all 52-pin devic es, with or wi thout USB function.
2. Pin 7 is Not Connected (NC) for device with no USB function.
Part
No.
Main
Flash
(bit)
Sec.
Flash
(bit)
SRAM
(bit)
Macro
-Cells
I/O
Pins
PWM
Ch.
Timer
/ Ctr
UART
Ch.
I
2
C
ADC
Ch.
DDC USB
V
CC
MHz Pins
uPSD
3254 A-40
2M 256K 256K 16
37 or
46
5 3 2 1 4 yes yes 5V 40
52 or
80
uPSD
3254
BV-24
2M 256K 256K 16 46 5 3 2 1 4 yes 3V 24 80
uPSD
3253 B-40
1M 256K 256K 16 37 5 3 2 1 4 yes 5V 40 52
uPSD
3253
BV-24
1M 256K 256K 16 37 5 3 2 1 4 yes 3V 24 52
39 P1.5 / ADC1 38 P1.4 / ADC0 37 P1.3 / TXD1 36 P1.2 / RXD1 35 P1.1 / T2X 34 P1.0 / T2 33 V
CC
32 XTAL2 31 XTAL1 30 P3.7 / SCL2 29 P3.6 / SDA2 28 P3.5 / T1 27 P3.4 / T0
PD1 PC7 PC6 PC5
USB–
PC4
USB+
V
CC
GND
PC3 PC2 PC1 PC0
1 2 3 4 5
(1)
6 7
(2)
8 9 10 11 12 13
52515049484746454443424140
PB0
PB1
PB2
PB3
PB4
PB5
VREF
GND
RESET
PB6
PB7
P1.7/ADC3
P1.6/ADC2
14151617181920212223242526
P4.7 / PWM4
P4.6 / PWM3
P4.5 / PWM2
P4.4 / PWM1
P4.3 / PWM0
GND
P4.2 / DDC VSYNC
P4.1 / DDC SCL
P4.0 / DDC SDA
P3.0 / RXD
P3.1 / TXD
P3.2 / EXINT0
P3.3 / EXINT1
AI05790C
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
14/175
Figure 4. TQ FP 8 0 C on ne ct i ons
Note: NC = Not Connected
1. Pull- up resis t or required on pi n 8 (2k for 3V devic es, 7.5k for 5V devices) fo r al l 82-pin devices, with or w i th out USB func tion.
2. Pin 10 is Not Connected (NC) for dev i ce with no US B function .
60 P1.5 / ADC1 59 P1.4 / ADC0 58 P1.3 / TXD1 57 P2.3, A11 56 P1.2 / RXD1 55 P2.2, A10 54 P1.1 / T2X 53 P2.1, A9 52 P1.0 / T2 51 P2.0, A8 50 V
CC
49 XTAL2 48 XTAL1 47 P0.7, AD7 46 P3.7 / SCL2 45 P0.6, AD6 44 P3.6 / SDA2 43 P0.5, AD5 42 P3.5 / T1 41 P0.4, AD4
PD2
P3.3 /EXINT1
PD1
PD0, ALE
PC7 PC6 PC5
USB-
PC4
USB+
NC
V
CC
GND
PC3 PC2 PC1
NC P4.7 / PWM4 P4.6 / PWM3
PC0
1 2 3 4 5 6 7 8
(1)
9 10
(2)
11 12 13 14 15 16 17 18 19 20
80797877767574737271706968676665646362
61
PB0
P3.2 / EXINT0
PB1
P3.1 / TXD
PB2
P3.0 / RXD
PB3
PB4
PB5NCVREF
GND
RESET
PB6
PB7
RD, CNTL1
P1.7 / ADC3
PSEN, CNTL2
WR, CNTL0
P1.6 / ADC2
21222324252627282930313233343536373839
40
PA7
PA6
P4.5 / PWM2
PA5
P4.4 / PWM1
PA4
P4.3 / PWM0
PA3
GND
P4.2 / DCC VSYNC
P4.1 / DDC SCL
PA2
P4.0 / DDC SDA
PA1
PA0
AD0, P0.0
AD1, P0.1
AD2, P0.2
AD3, P0.3
P3.4 / T0
AI05791B
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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Table 2. 80-Pin Package Pin Description
Port Pin
Signal
Name
Pin No. In/Out
Function
Basic Alternate
P0.0 AD0 36 I/O
External Bus
Multiplexed Address/Data bus A1/D1 P0.1 AD1 37 I/O Multiplexed Address/Data bus A0/D0 P0.2 AD2 38 I/O Multiplexed Address/Data bus A2/D2 P0.3 AD3 39 I/O Multiplexed Address/Data bus A3/D3 P0.4 AD4 41 I/O Multiplexed Address/Data bus A4/D4 P0.5 AD5 43 I/O Multiplexed Address/Data bus A5/D5 P0.6 AD6 45 I/O Multiplexed Address/Data bus A6/D6 P0.7 AD7 47 I/O Multiplexed Address/Data bus A7/D7 P1.0 T2 52 I/O General I/O port pin Timer 2 Count input P1.1 T2EX 54 I/O General I/O port pin Timer 2 Trigger input P1.2 RxD2 56 I/O General I/O port pin 2nd UART Receive P1.3 TxD2 58 I/O General I/O port pin 2nd UART Transmit P1.4 ADC0 59 I/O General I/O port pin ADC Channel 0 input P1.5 ADC1 60 I/O General I/O port pin ADC Channel 1 input P1.6 ADC2 61 I/O General I/O port pin ADC Channel 2 input P1.7 ADC3 64 I/O General I/O port pin ADC Channel 3 input P2.0 A8 51 O External Bus, Address A8 P2.1 A9 53 O External Bus, Address A9 P2.2 A10 55 O External Bus, Address A10 P2.3 A11 57 O External Bus, Address A11 P3.0 RxD1 75 I/O General I/O port pin UART Receive P3.1 TxD1 77 I/O General I/O port pin UART Transmit
P3.2 INTO 79 I/O General I/O port pin
Interrupt 0 input / Timer 0 gate control
P3.3 INT1 2 I/O General I/O port pin
Interrupt 1 input / Timer 1 gate
control P3.4 T0 40 I/O General I/O port pin Counter 0 input P3.5 T1 42 I/O General I/O port pin Counter 1 input
P3.6 SDA2 44 I/O General I/O port pin
I
2
C Bus serial data I/O
P3.7 SCL2 46 I/O General I/O port pin
I
2
C Bus clock I/O
P4.0 SDA1 33 I/O General I/O port pin
I
2
C serial data I/O for DDC
interface P4.1 SCL1 31 I/O General I/O port pin
I
2
C clock I/O for DDC interface
P4.2 VSYNC 30 I/O General I/O port pin VSYNC input for DDC interface
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
16/175
P4.3 PWM0 27 I/O General I/O port pin
8-bit Pulse Width Modulation
output 0
P4.4 PWM1 25 I/O General I/O port pin
8-bit Pulse Width Modulation
output 1
P4.5 PWM2 23 I/O General I/O port pin
8-bit Pulse Width Modulation
output 2
P4.6 PWM3 19 I/O General I/O port pin
8-bit Pulse Width Modulation
output 3
P4.7 PWM4 18 I/O General I/O port pin
Programmable 8-bit Pulse Width
modulation output 4
USB- 8 I/O
USB Pin. Pull-up resistor required (2k for 3V devices, 7.5k for 5V devices) for all devices, with or without USB function.
USB+ 10 I/O
USB Pin. Pin is not connected for device with no USB function.
AVREF 70 O Reference Voltage input for ADC
RD_ 65 O READ signal, external bus WR_ 62 O WRITE signal, external bus
PSEN_ 63 O PSEN
signal, external bus
ALE 4 O Address Latch signal, external bus
RESET_ 68 I Active low RESET
input XTAL1 48 I Oscillator input pin for system clock XTAL2 49 O Oscillator output pin for system clock
PA0 35 I/O General I/O port pin
1. PLD Macro-cell outputs
2. PLD inputs
3. Latched Address Out (A0-A7)
4. Peripheral I/O Mode
PA1 34 I/O General I/O port pin PA2 32 I/O General I/O port pin PA3 28 I/O General I/O port pin PA4 26 I/O General I/O port pin PA5 24 I/O General I/O port pin PA6 22 I/O General I/O port pin PA7 21 I/O General I/O port pin
Port Pin
Signal
Name
Pin No. In/Out
Function
Basic Alternate
17/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
52 PIN PACKAGE I/O PORT
The 52-pin package members of the uPSD325X devices have the s ame port pins as those of t he 80-pin package except:
Port 0 (P0.0-P0.7, external address/data bus
AD0-AD7)
Port 2 (P2.0-P2.3, external address bus A8-
A11)
Port A (PA0-PA7)
Port D (PD2)
Bus control signal (RD,WR,PSEN,ALE)
Pin 5 requires a pull-up resistor (2k for 3V de­vices, 7.5k for 5V devices) for all devices, wi th or without USB function.
PB0 80 I/O General I/O port pin
1. PLD Macro-cell outputs
2. PLD inputs
3. Latched Address Out (A0-A7)
PB1 78 I/O General I/O port pin PB2 76 I/O General I/O port pin PB3 74 I/O General I/O port pin PB4 73 I/O General I/O port pin PB5 72 I/O General I/O port pin PB6 67 I/O General I/O port pin PB7 66 I/O General I/O port pin PC0 TMS 20 I JTAG pin
1. PLD Macro-cell outputs
2. PLD inputs
3. SRAM sta nd by voltag e input (V
STBY
)
4. SRAM battery-on indicator (PC4)
5. JTAG pins are dedicated pins
PC1 TCK 16 I JTAG pin PC2
V
STBY
15 I/O General I/O port pin PC3 TSTAT 14 I/O General I/O port pin PC4 TERR 9 I/O General I/O port pin PC5 TDI 7 I JTAG pin PC6 TDO 6 O JTAG pin PC7 5 I/O General I/O port pin
PD1 CLKIN 3 I/O General I/O port pin
1. PLD I/O
2. Clock input to PLD and APD
PD2 CSI 1 I/O General I/O port pin
1. PLD I/O
2. Chip select to PSD Module Vcc 12 Vcc 50
GND 13 GND 29 GND 69
NC 11 NC 17 NC 71
Port Pin
Signal
Name
Pin No. In/Out
Function
Basic Alternate
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
18/175
ARCHITECTURE OVERVIEW Memory Organization
The uPSD325X devices’ standard 8032 Core has separate 64KB address spaces for Program mem­ory and Data Memory. Program m em ory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in eit her program or data spac e. The Flash memory consists of two flash memory blocks: the main Flash (1 or 2Mbit) and the Sec­ondary Flash (256Kbit). Except during flash mem­ory programming or update, Flash memory can only be read, not written to. A Page Register is used to access memory beyond the 64K bytes ad­dress space. Refer to the PSD M odule for det ails on mapping of the Flash memory.
The 8032 core h as t wo t ypes of data memory (in­ternal and external) that can be read and written. The internal SRAM c onsists of 256 by tes, and in­cludes the stack area.
The SFR (Special Function Registers) occupies the upper 128 bytes of the internal SRAM, the reg­isters can be accessed by Direct addressing only. There are two separate blocks of external SRAM inside the uPSD325X devices: one 256 bytes block is assigned for DDC data storage . Another 32K bytes resides in the PS D Module that can be mapped to any address space defined by the user.
Figure 5. Memory Map and Address Space
Registers
The 8032 has several registers; these are the Pro­gram Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register).
Figure 6. 8032 MCU Registers
AI06635
SECONDARY FLASH
FLASH
MAIN
32KB
128KB
OR
256KB
FF
7F
0
FFFF
(DDC)
8KB256B
INT. RAM
EXT. RAM
EXT. RAM
Addressing
Indirect
Indirect Direct
or
Addressing
Addressing
Direct
SFR
Internal RAM Space (256 Bytes)
FF00
External RAM Space (MOVX)
Flash Memory Space
AI06636
Accumulator B Register
Stack Pointer Program Counter Program Status Word
General Purpose Register (Bank0-3) Data Pointer Register
PCH
DPTR(DPH)
A B
SP
PCL
PSW
R0-R7
DPTR(DPL)
19/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Accumulator. The Accumulator is the 8-bit gen-
eral purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown below.
Figure 7. Configuration of BA 16-bit Registers
B Register. The B Register is the 8-bit general
purpose register, us ed for an arithmetic o peration such as multiply, division with Accumulator
Stack Pointer. The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack P oin ter is in itializ ed to 07h af ter res et. T his causes the stack to begin at location 08h.
Figure 8. Stack Pointer
Program Counter. The Program Counter is a 16-
bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In RESET
state, the program counter has reset routine address (PCH:00h, PCL:00h).
Program Status Word. The Program Status Word (PSW) contains several bits that reflect the current state of the CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is de­scribed in Figure 9, page 20. It contains the Carry flag, the Auxiliary carry flag, the Half Carry (for BCD operation), the general purpose flag, the Register bank select flags, the Overflow flag, and Pari ty fl ag.
[Carry Flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruc­tion or Rotate Instruction.
[Auxiliary Carry Flag, AC]. After operation, this is set when there is a carry from Bit 3 of ALU or there is no borrow from Bit 4 of ALU.
[Register Bank Select Flags, RS0, RS1]. This flags select one of four bank(00~07H:bank0, 08~0Fh:bank1, 10~ 17h:bank2, 17~1Fh:bank3) in Internal RAM.
[Overflow Flag, OV]. This flag is set to '1' when an overflow occurs as the result of an arithmetic oper­ation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7Fh) or -128 (80h). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is copied to this flag.
[Parity Flag, P]. This flag ref lect on number of Ac­cumulator’s 1. If number of Accumulator’s 1 is odd, P=0. otherwise P=1. Sum of adding Accumulator’s 1 to P is always even.
R0~R7. General purpose 8-bit registers that are locked in the lower portion of internal data area.
Data Pointer Register. Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This register is used as a data pointer for the data transmission with external data memory in the PSD Module.
AI06637
Two 8-bit Registers can be used as a "BA" 16-bit Registers
A
B
AB
AI06638
SP (Stack Pointer) could be in 00h-FFh
SP00h
Stack Area (30h-FFh)
00h-FFh
Hardware Fixed
Bit 15 Bit 0Bit 8 Bit 7
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
20/175
Figure 9. PSW (Program S tat us W o rd) R egi st er
Program Memory
The program memory consists of two Flash mem­ory: 128 KByte (or 256 KByte) Main Flash and 32 KByte of Secondary Flash. The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming.
After reset, the CPU begins execution from loca­tion 0000h. As s ho w n i n F igure 10, e ac h i nterrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that loca­tion, where it commences execution of the service routine. External Interrupt 0, for example, is as­signed to location 0003h. If External Interrupt 0 is going to be used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service location is available as gen eral purpose Program Memory.
The interrupt service locations are spaced at 8­byte intervals: 0003h for External Interrupt 0, 000Bh for Timer 0, 0013 h f or E xternal I nterrupt 1, 001Bh for Timer 1 and so forth. If an interrupt ser­vice routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent in­terrupt locations, if other interrupts are in use.
Data memory
The internal data memory is divided into four phys­ically separ ated blocks: 256 byt es of internal RAM, 128 bytes of Special Function Registers (SFRs) areas, 256 bytes of external RAM (XRAM-DDC) and 32K bytes (XRAM-PSD) in the PSD Module.
RAM
Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, con­tain 128 directly addressable bit locations. The stack depth is only limited by the available internal RAM space of 256 bytes.
Figure 10. Int errupt Locatio n of P rog ra m Memory
XRAM-DDC
The 256 bytes of XRAM-DDC used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. T he ad­dress pointer (DDCADR) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to DDC Interface part). However, it is also possible to addres s the RAM through MOVX com mand as normally used in the internal RAM extension of 80C51 deriva­tives. XRAM-DDC FF00 to FFFF is directly ad­dressable as external data memory locations FF00 to FFFF via MOVX -DPTR instruction or via MOVX-Ri instruction. When XRAM-DDC is dis­abled, the address space FF00 to FFFF can be as­signed to other resources.
XRAM-PSD
The 32K bytes of XRA M-PSD resi des in the PS D Module and can be mapped to any address space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development tool. The XRAM­PSD has a battery backup feature that allow the data to be retained i n the event of a power lost. The battery is connect ed to the Port C PC2 pin. This pin must be configured in PSDSoft to be bat­tery back-up.
AI06639
CY
Reset Value 00h
Parity Flag Bit not assigned
Overflow Flag
Register Bank Select Flags
(to select Bank0-3)
Carry Flag
Auxillary Carry Flag
General Purpose Flag
AC FO RS1 RS0 OV P
MSB
LSB
PSW
AI06640
0000hReset
8 Bytes
Interrupt Location
0003h
000Bh
0013h
008Bh
21/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
SFR
The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15, page 33 gives an overview of the Speci al Function Regis­ters. Sixteen address in the SFRs space are both­byte and bit-addressable. The bit-addressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh.
Table 3. RAM Address
Addressing Modes
The addressing modes in uPS D325X devices in­struction set are as follows
Direct addressing
Indirect addressing
Register addressing
Register-specific addressing
Immediate constants addressing
Indexed addressing
(1) Direct addressing. In a direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs (80~FFH RAM) can be directly addressed.
Example:
mov A, 3EH ; A <----- RAM[3E]
Figure 11. Direct Addressing
(2) Indirect addressing. In indirect addressing
the instruction specifies a register which contains the address of the operand. Both internal and ex­ternal RAM can be indirectly addressed. The ad­dress register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR.
Example:
mov @R1, #40 H ;[R1] <-----40H
Figure 12. Indirect Addressing
Byte Address (in Hexadecimal)
Byte Address
(in Decimal)
↓↓
FFh 255 30h 48
msb Bit Address (Hex) lsb 2Fh 7F 7E 7D 7C 7B 7A 79 78 47 2Eh 77 76 75 74 73 72 71 70 46
2Dh 6F 6E 6D 6C 6B 6A 69 68 45 2Ch 67 66 65 64 63 62 61 60 44
2Bh 5F 5E 5D 5C 5B 5A 59 58 43 2Ah 57 56 55 54 53 52 51 50 42 29h 4F 4E 4D 4C 4B 4A 49 48 41 28h 47 46 45 44 43 42 41 40 40 27h 3F 3E 3D 3C 3B 3A 39 38 39 26h 37 36 35 34 33 32 31 30 38 25h 2F 2E 2D 2C 2B 2A 29 28 37 24h 27 26 25 24 23 22 21 20 36 23h 1F 1E 1D 1C 1B 1A 19 18 35 22h 17 16 15 14 13 12 11 10 34 21h 0F 0E 0D 0C 0B 0A 09 08 33 20h 07 06 05 04 03 02 01 00 32 1Fh
Register Bank 3
31 18h 24 17h
Register Bank 2
23 10h 16 0Fh
Register Bank 1
15 08h 8 07h
Register Bank 0
7
00h 0
AI06641
3Eh
Program Memory
04
A
AI06642
R1
55h
Program Memory
55
40h
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
22/175
(3) Register addressing. The register banks, containing registers R0 through R7, can be ac­cessed by certain instru ctions which carry a 3-bit register specification within the o pcode of the in­struction. Instructions that access the registers this way are code efficient, s ince this mode elimi­nates an address byte. When the instruction is ex­ecuted, one of four banks is selected at execution time by the two bank select bits in the PSW.
Example:
mov PSW, #0001000B ; select Bank0 mov A, #30H mov R1, A
(4) Register-specific addressing. Some in­structions are specific to a certain register. For ex­ample, some instructions always operate on the Accumulator, or Data P ointer, etc., so no addres s byte is needed to point it. The opc ode itself does that.
(5) Immediate constants addressing. The val­ue of a constant can follow the opcode in Program memory.
Example:
mov A, #10H.
(6) Indexed addressing. Only Program memory can be accessed with indexed addressing, a nd it can only be read. This addressing mode is intend­ed for reading look-up tables in Program memory. A 16-bit base register (either DPTR or PC) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program memory is formed by add­ing the Accumulator data to the base pointer.
Example:
movc A, @A+DPTR
Figure 13. Indexed Addressing
Arithmetic Instructions
The arithmetic instructions is listed in Table 4, page 23. The table indicates the addressing modes that can be used with each i nstruction to access the <byte> operand. For example, the ADD A, <byte> instruction can be written as:
ADD a, 7FH (direct addressing) ADD A, @R0 (indirect addressing) ADD a, R7 (register addressing) ADD A, #127 (immediate constant)
Note: Any byte in the internal Data Memory space can be incremented without going through the Ac­cumulator.
One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer is used to generate 16-bit addresses for external memory, so being able to increment it in one 16-bit operations is
a useful feature. The MUL A B instru ction mul tiplies the Accum ula-
tor by the data in the B register and puts the 16-bit product into the concatenat ed B and Accum ulator registers.
The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quo­tient in the Accumulator, and the 8-bit remainder in th e B regis ter.
In shift operations, dividing a num ber by 2 n shifts its “n” bits to the right. Using DIV A B to perform the division completes the shift in 4?s and leaves the B register holding the bits that were shifted out. The DAA instruction is for BCD arithmetic opera­tions. In BCD arithmetic, ADD and ADDC instruc­tions should always be followed by a DAA operation, to ensure that the result is also in BCD.
Note: DAA will not convert a binary number to BCD. The DAA operation produces a meaningful result only as the second step in the addition of two BCD bytes.
AI06643
3Eh
Program Memory
ACC DPTR
3Ah 1E73h
23/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Table 4. Arithmetic Instructions
Logical Instructions
Table 5, page 24 shows list of uPSD325X devices logical instructions. The instructions that perform Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-by­bit basis. That is, if the Accumulator contains 00110101B and byte contains 01010011B, then:
ANL A, <byte> will leave the Accumu lator holdi ng 00010001B. The addressing modes that can be used to access
the <byte> operand are listed in Table 5. The ANL A, <byte> instruction may take any of the
forms:
ANL A,7FH(direct addressing)
ANL A, @R1 (indirect addressing)
ANL A,R6 (register addressing)
ANL A,#53H (immediate constant) Note: Boolean operations can be performed on
any byte in the internal Data Mem ory space with­out going through the Accumulator. The XRL <byte>, #data instruction, for example, offers a quick and easy way to invert port bits, as in
XRL P1, #0FFH.
If the operation is in response to an interrupt, not using the Accumulator saves the time and effort to push it onto the stack in the service routine.
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulato r. This is a useful operation in BCD manipulations. For exam­ple, if the Accumulator contains a b inary number which is known to be less than 100, it can be quick­ly converted to BCD by the following code:
MOVE B,#10 DIV AB SWAP A ADD A,B
Dividing the num ber by 10 leaves the ten s digi t in the low nibble of the Ac cumulator, and the ones digit in the B register. The SWAP and ADD instruc­tions move the tens digit to the high nibble of the Accumulator, and the ones digit to the low nibble.
Mnemonic Operation
Addressing Modes
Dir. Ind. Reg. Imm
ADD A,<byte> A = A + <byte> X X X X ADDC A,<byte> A = A + <byte> + C X X X X SUBB A,<byte> A = A – <byte> – C X X X X
INC A = A + 1 Accumulator only
INC <byte> <byte> = <byte> + 1 X X X
INC DPTR DPTR = DPTR + 1 Data Pointer only
DEC A = A – 1 Accumulator only
DEC <byte> <byte> = <byte> – 1 X X X
MUL AB B:A = B x A Accumulator and B only
DIV AB
A = Int[ A / B ]
B = Mod[ A / B ]
Accumulator and B only
DA A Decimal Adjust Accumulator only
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
24/175
Table 5. Logical Instructions
Mnemonic Operation
Addressing Modes
Dir. Ind. Reg. Imm
ANL A,<byte> A = A .AND. <byte> X X X X
ANL <byte>,A A = <byte> .AND. A X
ANL <byte>,#data A = <byte> .AND. #data X
ORL A,<byte> A = A .OR. <byte> X X X X
ORL <byte>,A A = <byte> .OR. A X
ORL <byte>,#data A = <byte> .OR. #data X
XRL A,<byte> A = A .XOR. <byte> X X X X
XRL <byte>,A A = <byte> .XOR. A X
XRL <byte>,#data A = <byte> .XOR. #data X
CRL A A = 00h Accumulator only CPL A A = .NOT. A Accumulator only
RL A Rotate A Left 1 bit Accumulator only
RLC A Rotate A Left through Carry Accumulator only
RR A Rotate A Right 1 bit Accumulator only
RRC A Rotate A Right through Carry Accumulator only
SWAP A Swap Nibbles in A Accumulator only
25/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Data Transfers Internal RAM. Table 6 shows the menu of in-
structions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used with each one. The MOV <dest>, <src> instruction allows data to be transferred between any two internal RAM or SFR locations without going th rough the Accumulator. Remember, th e Upper 128 b ytes of data RAM can be accessed only by indirect ad­dressing, and SFR space only by di rect address­ing.
Note: In uPSD325X devices, the s tack resides in on-chip RAM, and grows upw ards. The PUSH in­struction first increments the S tack Pointer (SP), then copies the byte into the stack. PUSH and POP use only direct addressing to identify the byte being saved or restored, but the stack itself is ac­cessed by indirect addressin g using the S P regis­ter. This means the stack can go into the Upper 128 bytes of RAM, if they are implemented, but not into SFR space.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data Pointer (DPTR) for look-up tables in Program Memory.
The XCH A, <byte> instruction causes the Accu­mulator and ad-dressed byte to exchange data. The XCHD A, @Ri instruction is similar, but only the low nibbles are involved in the exchange. To see how XCH and XCHD can be used to facilitate data manipulations, c onsider first the problem of shifting and 8-digit BCD number two digits to the right. Table 8 shows how this can be done using XCH instructions. To aid in understanding how the code works, the con tents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the instruction has been executed.
After the routine has been executed, the Accumu­lator contains the two digits that were shifted out on the right. Do ing the routine with direct MOVs uses 14 code bytes. The same operation with XCHs uses only 9 bytes and executes almost twice as fast. To right-shift by an odd number of digits, a one-digit must be executed. Table 9 shows a sample of code that will right-shift a BCD number one digit, using the XCHD instruction. Again, the contents of the registers holding the number and of the accumulator are shown along­side each instruction.
Table 6. Data Transfer Instructions that Access Internal Data Memory Space
Mnemonic Operation
Addressing Modes
Dir. Ind. Reg. Imm
MOV A,<src> A = <src> XXXX
MOV <dest>,A <dest> = A X X X
MOV <dest>,<src> <dest> = <src> XXXX
MOV DPTR,#data16 DPTR = 16-bit immediate constant X
PUSH <src> INC SP; MOV “@SP”,<src> X POP <dest> MOV <dest>,”@SP”; DEC SP X
XCH A,<byte> Exchange contents of A and <byte> X X X
XCHD A,@Ri Exchange low nibbles of A and @Ri X
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
26/175
First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed which leaves the last byte, loca­tion 2EH, holding the l ast two dig its of the s hifted number. The pointers are decremented, and the loop is repeated for location 2DH. The CJ NE in­struction (Compare and Jump if Not equal) is a loop control that will be described later. The l oop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH, and 2BH. At that point the digit that was orig­inally shifted out on the right has propagated to lo­cation 2AH. Since that location should be left with 0s, the lost digit is moved to the Accumulator.
Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)
Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)
Table 9. Shifting a BCD Number One Digit to the Right
2A 2B 2C 2D 2E ACC
MOV A,2Eh 00 12 34 56 78 78 MOV 2Eh,2Dh 00 12 34 56 56 78 MOV 2Dh,2Ch 00 12 34 34 56 78 MOV 2Ch,2Bh 00 12 12 34 56 78 MOV 2Bh,#0 00 00 12 34 56 78
2A 2B 2C 2D 2E ACC
CLR A 00 12 34 56 78 00 XCH A,2Bh 00 00 34 56 78 12 XCH A,2Ch 00 00 12 56 78 34 XCH A,2Dh 00 00 12 34 78 56 XCH A,2Eh 00 00 12 34 56 78
2A 2B 2C 2D 2E ACC
MOV R1,#2Eh 00 12 34 56 78 xx MOV R0,#2Dh 00 12 34 56 78 xx
; loop for R1 = 2Eh
LOOP: MOV A,@R1 00 12 34 56 78 78
XCHD A,@R0 00 12 34 58 78 76 SWAP A 00 12 34 58 78 67 MOV @R1,A 0012345867 67 DEC R1 00 12 34 58 67 67 DEC R0 00 12 34 58 67 67 CNJE R1,#2Ah,LOOP 00 12 34 58 67 67
; loop for R1 = 2Dh 00 12 38 45 67 45 ; loop for R1 = 2Ch 00 18 23 45 67 23 ; loop for R1 = 2Bh 08 01 23 45 67 01
CLR A 0801234567 00 XCH A,2Ah 00 01 23 45 67 08
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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
External RAM. Table 10 shows a l ist of the Data
Transfer instructions that access external Data Memory. Only indirect addressing can be used. The choice is whether t o us e a one-by te address, @Ri, where Ri can be either R0 or R1 of t he se­lected register bank, or a two-byte address, @DTPR.
Note: In all external Data RAM accesses, the Ac­cumulator is always either the destination or source of the data.
Lookup Ta b les. Table 11 shows the t wo instruc­tions that are available for reading lookup tables in Program Memory. Since these instructions access only Program Memory, the lookup tables can only be read, not updated.
The mnemonic is MOVC for “move constant.” The first MOVC instruction in Table 11 can accommo­date a table of up to 256 entries numbered 0 through 255. The number of the desired e ntry is loaded into the Accumulator, and the Data Pointer is set up to point to the beginning of the table. Then:
MOVC A, @A+DPTR
copies the desired table entry into the Accumula­tor.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table base, and the table is accessed through a subroutine. First the num ber of the desired en-try is loaded into the Accumulator, and the subroutine is called:
MOV A , ENTRY NUMBER CALL TABLE
The subroutine “TABLE” would look like this:
TABLE: MOVC A , @A+PC RET
The table itself immediately follows the RET (re­turn) instruction is Program Memory. This type of table can have up to 255 entries, numbered 1 through 255. Number 0 cann ot be used, bec ause at the time the MOVC instruction is exec uted, the PC contains the address of the RET instruction. An entry numbered 0 would be the RET opcode it­self.
Table 10. Data Transfer Instruction that Access External Data Memory Space
Table 11. Lookup Table READ Instruction
Address Width Mnemonic Operation
8 bits MOVX A,@Ri READ external RAM @Ri
8 bits MOVX @Ri,A WRITE external RAM @Ri 16 bits MOVX A,@DPTR READ external RAM @DPTR 16 bits MOVX @DPTR,a WRITE external RAM @DPTR
Mnemonic Operation
MOVC A,@A+DPTR READ program memory at (A+DPTR)
MOVC A,@A+PC READ program memory at (A+PC)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
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Boolean Instructions
The uPSD325X dev ices c ontain a c omp lete B ool­ean (single-bit) processor. One page o f the inter­nal RAM contains 128 address -able bits, and the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one can be treated as a separate single­bit port. The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, OR and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in Table 12. All bits acces ses are by di re ct addressing.
Bit addresses 00h through 7Fh are i n the Lower 128, and bit ad-dresses 80h through FFh are in SFR space.
Note how easily an internal flag can be moved to a port pin:
MOV C,FLA G MOV P1.0,C
In this example, FLAG is the name of any addres­sable bit in the Lower 128 or SFR space. An I/O line (the LSB of Port 1, in this case) is set or cleared depending on whether the Flag Bit is '1' or '0.'
The Carry Bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instruc­tion s th a t r efer to th e Ca rr y B it as C as se mbl e a s Carry-specific instructions (CLR C, etc.). The Car­ry Bit also has a direct address, since it resides in the PSW register, which is bit-addressable.
Note: The Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR) operation. An XRL operat ion is simple to im­plement in software. Suppose, for example, it is re­quired to form the Exclusive OR of two bits:
C = bit 1 .XRL. bit2
The software to do that could be as follows:
MOV C , bit1 JNB bit2, OVER CPL C OVER: (continue)
First, Bit 1 is moved to the Carry. If bit2 = 0, then C now contains the correct result. That is, Bit 1 .XRL. bit2 = bit1 if bit2 = 0. On t he other hand, if bit2 = 1, C now contains the complement of the correct result. It need only be inverted (CPL C) to complete the operation.
This code uses the JNB instruction, one of a series of bit-test instructions which execute a jump if the
addressed bit is set (JC, JB, JBC) or if the ad­dressed bit is not set (JNC, JNB). In the above case, Bit 2 is being tested, and if bit2 = 0, the CPL C instruction is jumped over.
JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a flag can be tested and cleared in one operation. All the PSW bits are directly addressable, so the P arity B it, or the gen­eral-purpose flags, for example, are also available to the bit-test instructions.
Table 12. Boolean Instructions
Relative Offset
The destination address for th ese jumps is spec i­fied to the assembler by a label or by an actual ad­dress in Program memory. How-ever, the destination address assembl es to a relat ive off set byte. This is a signed (two’s complement) offset byte which is added to the PC in two’s complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127 Program Memory bytes relative to the first byte fol­lowing the instruction.
Mnemonic Operation
ANL C,bit C = A .AND. bit
ANL C,/bit C = C .AND. .NOT. bit
ORL C,bit C = A .OR. bit ORL C,/bit C = C .OR. .NOT. bit MOV C,bit C = bit MOV bit,C bit = C
CLR C C = 0
CLR bit bit = 0
SETB C C = 1
SETB bit bit = 1
CPL C C = .NOT. C
CPL bit bit = .NOT. bit
JC rel Jump if C =1
JNC rel Jump if C = 0
JB bit,rel Jump if bit =1 JNB bit,rel Jump if bit = 0 JBC bit,rel Jump if bit = 1; CLR bit
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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Jump Instructions
Table 13 shows the list of unconditional jump in­structions. The table lists a single “JMP add” in­struction, but in fact there are three SJMP, LJM P, and AJMP, which differ in the format of the desti­nation address. JMP is a generic mnemonic which can be used if the programmer does not care which way the jump is en-coded.
The SJMP instruction encodes the destination ad­dress as a relative offset, as described above. The instruction is 2 bytes long, consisting of the op­code and the relative offset byte. The jump dis­tance is limited to a range of -128 to +127 bytes relative to the instruction following the SJMP.
The LJMP instruction encodes the destinat ion ad­dress as a 16-bit constant. The instruction is 3 bytes long, cons isting of the op code and two ad­dress bytes. The destinati on ad dres s c an b e any ­where in the 64K Program Memory space.
The AJMP instruction encodes the destination ad­dress as an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, follo wed by an­other byte containing the low 8 bits of the destina­tion address. When the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The high 5 bits stay the same. Hence the destination has to be within the same 2K block as the instruction following the AJMP.
In all cases the programmer specifies the destina­tion address to the assembler in the same way: as a label or as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instruction will not support the distan ce to the specified destination address, a “Destination out of range” message is written into the List file.
The JMP @A+DPTR instruction supports case jumps. The destination address is computed at ex­ecution time as the sum of the 16-bit DPTR regis­ter and the Accumulator. Typically. DPTR is set up with the address of a jump table. In a 5-way branch, for ex-ample, an integer 0 through 4 is loaded into the Accum ulator. The c ode to be exe­cuted mi ght be as follows :
MOV DPTR,#JUMP TABLE MOV A,INDEX_ N U MBER RL A JMP @A+DPTR
The RL A instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because each entry in the jump table is 2 bytes long:
JUMP TABLE: AJMP CASE 0 AJMP CASE 1 AJMP CASE 2 AJMP CASE 3 AJMP CASE 4
Table 13 shows a single “CALL a ddr” instruction, but there are two of them, LCALL and ACALL, which differ in the format in which the subroutine address is given to the CPU. CALL is a generic mnemonic which c an be used if the prog rammer does not care which way the address is encoded.
The LCALL instruction uses the 16-bit address for­mat, and the subroutine can be anywh ere in the 64K Program Memory space. The ACALL instruc­tion uses the 11-bit format, and the subroutine must be in the same 2K block as the instruction fol­lowing the ACALL.
In any case, the programmer specifies the subrou­tine address to the assembler in the same way: as a label or as a 16-bit constant. The assembler will put the address into the correct format for the giv­en instructions.
Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL.
RETI is used to return from an interrupt service routine. The only difference between RET and RETI is t hat RETI tells t he int e rru pt control system that the interrupt in progress is done. If there is no interrupt in progress at the time RETI is executed, then the RETI is functionally identical to RET.
Table 13. Unconditional Jump Instructions
Mnemonic Operation
JMP addr Jump to addr
JMP @A+DPTR Jump to A+DPTR
CALL addr Call Subroutine at addr
RET Return from subroutine RETI Return from interrupt NOP No operation
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
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Table 14 shows the list of conditional jumps avail­able to the uPSD325X device user. All of these jumps specify the destination address by the rela­tive offset method, and so are limited to a jump dis­tance of -128 to +127 bytes from the instruction following the conditional jump instruction. Impor­tant to note, however, the user specifies to the as­sembler the actual destination address the same way as the other jumps: as a label or a 16-bit con­stant.
There is no Zero Bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that con­dition.
The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N times, load a counter byte with N and terminate the loop with a DJNZ to t he beginning of the loop, as shown below for N = 10:
MOV COUNTER,#10 LOOP: (begin loop)
(end loop) DJNZ COUNTER, LOOP (continue)
The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control as in Ta­ble 9. Two bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes are not equal. In the example of Table 9 Shifting a BCD Number O ne Digits to the Right, the two bytes were data in R1 and the constant 2Ah. The initial data in R1 was 2Eh.
Every time the loop was executed, R1 was decre­mented, and the looping was to continue unt il the R1 data reached 2Ah.
Another application of this instruction is in “greater than, less than” comparisons. The two bytes in the operand field are taken as unsigned integers. If the first is less than the second, then the Carry Bit is set (1). If the first is greater than or equal to the second, then the Carry Bit is cleared
Machine Cycles
A machine cycle consists of a sequence of six states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus, a machine cycle takes 12 oscillator periods or 1µs if the oscil­lator frequency is 12MHz. Refer to Figure 14, page
31. Each state is divided into a Phase 1 half and a
Phase 2 half. State Sequence in uPSD325X devic­es shows that retrieve/execute sequences in states and phases for various kinds of instructions.
Normally two program retrievals are generated during each machine cycle, even if the instruction being executed does
not
require it. If the instruc­tion being executed does not need more code bytes, the CPU sim ply ignores the e xtra retrieval, and the Program Counter is not incremented.
Execution of a one-cycle instruction (Figure 14, page 31) begins during State 1 of the machine cy­cle, when the opcode is latched into the Instruction Register. A second retrieve occurs during S4 of the same machine cycle. Execution is complete at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program retrieval is generated dur­ing the second cycle of a MOVX instruction. This is the only time program retrievals are skipped. The retrieve/execute sequence for MOVX instruc­tion is shown in Figure 14, page 31 (d).
Table 14. Conditional Jump Instructions
Mnemonic Operation
Addressing Modes
Dir. Ind. Reg. Imm
JZ rel Jump if A = 0 Accumulator only
JNZ rel Jump if A 0 Accumulator only
DJNZ <byte>,rel Decrement and jump if not zero X X
CJNE A,<byte>,rel Jump if A <byte> X X
CJNE <byte>,#data,rel Jump if <byte> #data X X
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