Independent supply for CMOS output stage
with 2.5V/3.3V capability
■ SFDR= -68.3 dBc @ Fin=10MHz
■ 1GHz analog bandwidth Track-and-Hold
■ Common clocking between channels
■ Dual simultaneous Sample and Hold inputs
■ Multiplexed outputs
■ Built-in reference voltage with external bias
capability
DESCRIPTION
The TSA1203 is a new generati on of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25µm CMOS techno logy yielding high performances and very low power
consumption.
The TSA1203 is specifically designed for applications requiring very low noise floor, high SFDR
and good isolation b etween channels. It is based
on a pipeline structure and digital error correction
to provide high sta tic linearity at Fs=40M sps, and
Fin=10MHz.
For each channel, a voltage reference is integrated to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capability is available for the outputs, allowing chip s election. The inputs of t he ADC must be differentially
driven.
The TSA1203 is available in extended (0 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS
■ Medical imaging and ultrasound
■ 3G basestation
■ I/Q signal processing applications
■ High speed data acquisition system
■ Portable in st ru me nta t ion
PIN CONNECTIONS (top view)
REFPI
REFMI
INCMI
index
corner
AVCCB
4844 43 42 41 40 39 38
46 45
47
1
AGND
2
INI
3
AGND
4
INIB
5
AGND
6
IPOL
7
8
AGND
INQ
9
10
AGND
11
INBQ
AGND
12
13 14 15 16 17 18 19 20 21 22
REFPQ
INCMQ
REFMQ
AVCC
AVCC
TSA1203
AGND
AVCC
DVCC
GNDBE
VCCBI
VCCBI
OEB
SELECT
CLK
DGND
BLOCK DIAGRAM
SELECT
CLK
Timing
12
12
GND
M
U
X
VINI
VINBI
VINCMI
VREFMI
IPOL
VINQ
VINBQ
common mode
Polar.
common mode
VREFPI
VREFPQ
VREFMQ
VINCMQ
PACKAGE
+2.5V/3.3V
AD 12
I channel
AD 12
Q channel
REF I
REF Q
DGND
VCCBE
12
D0(LSB)
23 24
DVCC
OEB
D1
37
36
34
33
27
26
25
GNDBI
Buffers
GNDBE
35
32
31
30
29
28
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11(MSB)
VCCBE
GNDBE
VCCBE
12
D0
TO
D11
ORDER CODE
Part Number
TSA1203IF0°C to +85°CTQFP48TraySA120 3I
TSA1203IFT0°C to +85°CTQFP48Tape & ReelSA1203I
EVAL1203/BAEvaluation board
TodData Output Delay (Clock edge to Data Valid) 10pF load capacitance9ns
Tpd IData Pipeline delay for I channel7cycles
Tpd QData Pipeline delay for Q channel7.5cycles
TonFalling edge of OEB to digital output valid data1ns
ToffRising edge of OEB to digital output tri-state1ns
2/20
TIMING DIAGRAM
Simultaneous sampling
on I/Q channels
N+3
N+4
N+5
N+6
N+12
TSA1203
N+13
I
Q
CLK
SELECT
OEB
DATA
OUTPUT
sample N-9
I channel
N-1
N
sample N-8
I channel
samp le N-7
Q channel
N+1
N+2
sample N-6
Q channel
PIN CONNECTIONS (top view)
index
corner
1
AGND
2
INI
3
AGND
4
INIB
5
AGND
6
IPOL
7
AVCCB
8
AGND
INQ
9
10
AGND
INBQ
11
AGND
12
N+7
Tpd I + Tod
CLOCK AND SELECT CONNECTED TOGETHER
sample N+1
I channel
GNDBE
REFPI
REFMI
INCMI
AVCC
47
4844 43 42 41 40 39 38
46 45
VCCBI
AVCC
OEB
VCCBE
VCCBI
TSA1203
13 14 15 16 17 18 19 20 21 22
REFPQ
AGND
AVCC
INCMQ
REFMQ
DVCC
SELECT
CLK
DGND
DGND
sample N
Q channe l
D0(LSB)
37
23 24
DVCC
GNDBI
N+8
D1
N+9
Tod
sample N+1
Q channel
sample N+2
I channel
D2
36
D3
35
D4
34
D5
33
32
D6
31
D7
D8
30
D9
29
D10
28
D11(MSB)
27
26
VCCBE
GNDBE
25
N+10
sample N+2
Q channel
sample N+3
I chan n el
N+11
3/20
TSA1203
PIN DESCRIPTION
Pin NoNameDescriptionObservationPin NoNameDescriptionObservatio n
1AGND Analog ground0V25GNDBE Digital buff er ground0V
2INII channel analog input26VCCBE Digital Buffer power supply2.5V/3.3V
3AGND Analog ground0V27D11(MSB) Most Significant Bit outputCMOS output (2.5V/3.3V)
4INBII channel inverted analog input28D10Digital outputCMOS output (2.5V/3.3V)
5AGND Analog ground0V29D9Digital outputC MOS output (2.5V/3.3V)
6IPOLA nalog bias current input30D8Digit al outputCMOS output (2.5V/3.3V)
7AVCCAnalog power supply2.5V31D7Digital outputCMOS output (2.5V/3.3V)
8AGND Analog ground0V32D6Digital outputC MOS output (2.5V/3.3V)
9INQQ channel analog input33D5Digital outputCMOS output (2.5V/3.3V)
10AGND Analog grou nd0V3 4D4Digital ou tputCMOS output (2. 5V/3.3V)
11INBQQ channel inverted analog input35D3Digital outputCMOS output (2.5V/3.3V)
12AGND Analog grou nd0V3 6D2Digital ou tputCMOS output (2. 5V/3.3V)
13REFPQ Q channel top reference voltage37D1Digital outputCMOS output (2.5V/3.3V)
14REFMQ Q channel bottom reference
15INCMQ Q channel input common mode39VCCBE Digital Buffer power supply2.5V/3.3V - See Application
16AGND Analog grou nd0V4 0GNDBE Digital buffer ground0V
17AVCCAnalog power supply2.5V41VCCBIDigital Buffer power supply2.5V
18DVCCDigital power supply2.5V42VCCBIDigital Buffer powe r s upply2.5V
19DGNDDigital ground0V43OEBOutput Enable input2.5V/3.3V CMOS input
20CLKClock input2.5V CMOS input44AVCCAnalog power supply2.5V
21SELECT Channel selection2.5V CMOS input45AVCCAnalog power supply2.5V
22DGNDDigital ground0V46INCMII channel input common mode
23DVCCDigital power supply2.5V47REFMII channel bottom reference voltage 0V
24GNDBI Digital buffer ground0V48REFPII channel top reference voltage
voltage
0V38D0(LSB) Least Significant Bit outputCMOS output (2.5V/3.3V)
Note
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValuesUnit
AVCC
DVCC
VCCBE
VCCBI
Analog Supply voltage
Digital Supply voltage
Digital buffer Supply voltage
Digital buffer Supply voltage
IDoutDigital output current-100 to 100mA
TstgStorage temperature+150°C
ESD
HBM: Human Body Model
CDM: Charged Device Model
Latch-up
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
Class
4)
1)
1)
1)
1)
2)
3)
0 to 3.3V
0 to 3.3V
0 to 3.6V
0 to 3.3V
2
1.5
kV
A
4/20
OPERATING CONDITIONS
SymbolParameterMinTypMaxUnit
AVCCAnalog Supply voltage2.252.52.7V
DVCCDigital Supply voltage2.252.52.7V
VCCBEExternal Digital buffer Supply voltage2.252.53.5V
VCCBIInternal Digital buffer Supply voltage2.252.52.7V
TSA1203
VREFPI
VREFPQ
VREFMI
VREFMQ
INCMI
INCMQ
Forced top voltage reference0.941.4V
Forced bottom reference voltage00.4V
Forced input common mode voltage0.21V
ANALOG INPUTS
SymbolParameterTest conditionsMinTypMaxUnit
VIN-VINB Full scale refere nce voltag eDifferential inputs mandatory1.12.02 .8Vpp