TN8, TS8 and TYNx08 Series
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Fig. 3-2: Relative variation of thermal impedance
junction to ambient versus pulse duration
(recommended pad layout, FR4 PC board for
DPAK).
Fig. 4-1: Relative variation of gate trigger current
and holding current versus junction temperature
for TS8 series.
Fig. 4-2: Relative variation of gate trigger current
and holding current versus junction temperature
for TN8 & TYN series.
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS8 series.
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS8 series.
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS8 series.
1E-2 1E-1 1E+0 1E+1 1E+2 5E+2
0.01
0.10
1.00
K = [Zth(j-a)/Rth(j-a)]
DPAK
TO-220AB
tp(s)
-40 -20 0 20 40 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
IGT,IH,IL [T j] / IG T,IH,IL [Tj = 25°C]
IGT
IH & IL
Rgk = 1kΩ
Tj(°C)
-40 -20 0 20 40 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
IGT,IH,IL [T j] / IG T,IH,IL [Tj = 25°C]
IGT
IH & IL
Tj(°C)
IH[Rgk] / IH[Rgk = 1k ]Ω
Rgk(k )Ω
Rgk(k )Ω
dV/dt[Rgk] / dV/dt [Rgk = 220 ]Ω
0 20 40 60 80 100 120 140 160 180 200 220
0.0
2.5
5.0
7.5
10.0
12.5
15.0
VD = 0.67 x VDRM
Tj = 125°C
Rgk = 220Ω
dV/dt[Cgk] / dV/d t [R g k = 22 0 Ω]
Cgk(nF)