The TS497 2 i s an Audio Pow er Amplifier capable
of delivering 1.6W of continuous RMS ouput power into a 4
This Audio Am plifier is exhibiting 0.1% distortion
level (THD) from a 5V supply for a Pout = 250mW
RMS. An external standby mode cont rol reduces
the supply current to less than 10n A. An internal
shutdown protection is provided.
Ω load @ 5V.
PIN CONNECTIONS (Top View)
TS4972JT - FLIP CHIP
76
Vin
8
Vout1
Vin
12
+
Vcc
Gnd
5
Stdby
Vout2
Bypass
3
4
The TS4972 has been designed for high quality
audio applications such as m obile phones and t o
minimize the number of external components.
The unity-gain stable amplifier can be configured
by external gain setting resistors.
APPLICATIONS
■Mobile Phones (Cellular / Cordless)
■PDAs
■Laptop/Notebook computers
■Portable Audio Devices
ORDER CODE
Part
Number
Temperature
Range
TS4972IJT-40, +85°C
J = Flip Chip Package - only available in Tape & Reel (JT))
January 2003
Package
J
•
Marking
4972
TYPICAL APPLICATION SCHEMATIC
Audio
Input
Rin
Vin-
1
Cin
VCC
Rstb
Vin+
7
Bypass
3
Standby
5
Cb
Cfeed
Rfeed
VCC
6
VCC
-
+
Bias
GND
2
AV = -1
+
Vout 1
Vout 2
8
4
TS4972
Cs
RL
8 Ohms
1/28
TS4972
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
T
T
R
Supply voltage
CC
V
Input Voltage
i
Operating Free Air Temperature Range-40 to + 85°C
oper
Storage Temperature-65 to +150°C
stg
T
Maximum Junction Temperature150°C
j
Thermal Resistance Junction to Ambient
thja
PdPower Dissipation
ESDHuman Body Model2kV
ESDMachine Model200V
Latch-up Latch-up ImmunityClass A
Lead Temperature (soldering, 10sec )250°C
1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed V
3. Device is protected in case of over temperature by a thermal shutdown active @ 150°C.
4. Exceeding the power derating curves during a long period, involves abnormal operating condition.
OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
R
1. With Heat Sink Surface = 125mm2
Supply Voltage2.5 to 5.5V
CC
Common Mode Input Voltage Range
ICM
Standby Voltage Input :
STB
Device ON
Device OFF
R
Load Resistor4 - 32
L
Thermal Resistance Junction to Ambient
thja
1)
2)
3)
Internally Limited
+ 0.3V / GND - 0.3V
CC
G
G
V
- 0.5V ≤ V
CC
1)
6V
GND to V
CC
200°C/W
4)
to VCC - 1.2V
ND
≤ V
STB
≤ 0.5V
≤ V
STB
CC
ND
90°C/W
V
V
V
Ω
2/28
TS4972
ELECTRICAL CHARACTERISTICS
V
= +5V, GND = 0V , T
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic mea surements - 20*log(rms(Vout )/ rms(Vri ppl e)). Vripple is an added sinus signal to Vcc @ f = 217Hz
V
= +3.3V, GND = 0V, T
CC
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
amb
Ω
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
Vripple = 200mV rms
Ω,
= 25°C (unless otherwise specified)3)
68mA
101000nA
520mV
1.2W
0.1%
75dB
70Degrees
20dB
2MHz
SymbolParameterMin.Typ.Max.Unit
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic mea surements - 20*log(rms(Vout )/ rms(Vri ppl e)). Vripple is an added sinus signal to Vcc @ f = 217Hz
3. All electrical values are made by correlation between 2.6V and 5V measurements
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 200mV rms
Ω,
5.58mA
101000nA
520mV
500mW
Ω
0.1%
75dB
70Degrees
20dB
2MHz
3/28
TS4972
ELECTRICAL CHARACTERISTICS
V
= 2.6V, GND = 0V, T
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic mea surements - 20*log(rms(Vout )/ rms(Vri ppl e)). Vripple is an added sinus signal to Vcc @ f = 217Hz
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 200mV rms
Ω,
5.58mA
101000nA
520mV
300mW
Ω
0.1%
75dB
70Degrees
20dB
2MHz
ComponentsFunctional Description
Rin
Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also
forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin))
CinInput coupling capacitor which blocks the DC voltage at the amplifier input terminal
RfeedFeed back resistor which sets the closed loop gain in conjunction with Rin
CsSupply Bypass capacitor which provides power supply filtering
CbBypass pin capacitor which provides half supply filtering
Cfeed
Low pass filter capacitor allowing to cut the high frequency
(low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed))
RstbPull-up resistor which fixes the right supply level on the standby pin
GvClosed loop gain in BTL configuration = 2 x (Rfeed / Rin)
REMARKS
1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF.
2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way,
Fig. 69 : Signal to Noise Ratio vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
100
90
RL=4
RL=8
RL=16
80
70
SNR (dB)
60
50
2.53.03.54.04.55.0
Ω
Ω
Vcc (V)
Ω
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
Fig. 71 : Signal to Noise Ratio vs Power Supply
with Weighte d Fi lte r Type A
110
100
RL=4
RL=8
RL=16
90
Ω
Ω
Ω
Fig. 70 : Signal to Noise Ratio vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
Fig. 72 : Signal to Noise Ratio vs Power Supply
with Weighte d Fi lte r Type A
80
SNR (dB)
70
60
2.53.03.54.04.55.0
Vcc (V)
Fig. 73 : Frequency Response Gain vs Cin, &
Cfeed
10
5
0
-5
-10
Gain (dB)
-15
-20
-25
10100100010000
Cin = 82nF
Cin = 470nF
Cin = 22nF
Frequency (Hz)
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
Fig. 74 : Current Consum ption vs Power
Supply Voltage
Cfeed = 330pF
Cfeed = 680pF
Cfeed = 2.2nF
Rin = Rfeed = 22kΩ
Tamb = 25°C
17/28
TS4972
0.00.51.01.52.02.53.0
0
1
2
3
4
5
6
Vcc = 3.3V
Tamb = 25°C
Icc (mA)
Vstandby (V)
Fig. 75 : C urrent Consumption vs Standby
Voltage @ Vcc = 5V
7
6
5
4
3
Icc (mA)
2
1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vstandby (V)
Vcc = 5V
Tamb = 25°C
Fig. 77 : C urrent Consumption vs Standby
Voltage @ Vcc = 2.6V
6
5
4
3
Icc (mA)
2
Vcc = 2.6V
Tamb = 25°C
Fig. 76 : C urrent Consumption vs Standby
Voltage @ Vcc = 3.3V
Fig. 78 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
0.6
Tamb = 25°C
0.5
0.4
0.3
Vout1 & Vout2
0.2
RL = 4Ω
RL = 8Ω
1
0
0.00.51.01.52.02.5
Vstandby (V)
Fig. 79 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
0.7
RL = 4
RL = 8
Ω
Ω
RL = 16
Ω
18/28
Tamb = 25°C
0.6
0.5
0.4
0.3
Vout1 & Vout2
0.2
0.1
Clipping Voltage Low side (V)
0.0
2.53.03.54.04.55.0
Power supply Voltage (V)
0.1
Clipping Voltage High side (V)
0.0
2.53.03.54.04.55.0
Power supply Voltage (V)
RL = 16Ω
APPLICA TI ON INFORMATION
Fig. 80 : Demoboard Schematic
S1
P1
Neg. Input
P2
Pos. Inp ut
Vcc
S2
GND
VCC
R3
R8
1k
C3
R4
C4
S5
Positive Input mode
VCC
R7
100k
S8
Standby
R5
C11
+
VCC
GND
TS4972
C1
R2
R1
C5
1
7
R6
3
5
C12
+
C8
1u
100n
Vin-
Vin+
Bypass
Standby
C2
VCC
+
C6
C7
100µ
100n
Vout 1
Vout 2
U1
8
4
TS4972
+
+
C9
470µ
C10
470µ
S6
OUT1
S3
GND
S4
GND
S7
OUT2
6
VC
C
-
+
-
AV = -1
+
Bias
G
ND
2
Fig. 81 : Flip-Chip 300µm Demoboard Components Side
19/28
TS4972
Fig. 82 : Flip-Chip 300µm Demoboard Top
Solder Layer
Fig. 83 : Flip-Chip 300µm
Solder Layer
Demoboard Bottom
The output power is:
2
)Vout2(
Pout
=
RMS
R
L
)W(
For the same power supply voltage, the output
power in BTL configuration is four times higher
than the output power in single ended
configuration.
■Gain In Typical Application Schematic
(cf. page 1)
In flat region (no effect of Cin), the output voltage
of the first stage i s:
Vout1 = Vin –
For the second stage : Vout2 = -Vout1 (V)
The differential output voltage is:
Vout2
V o ut 1 = 2Vin –
Rfeed
------------------- - (V)
Rin
Rfeed
------------------- - (V)
Rin
■BTL Configuration Principle
The TS4972 is a monolithic power amplifier with a
BTL output type. BTL (Bridge Tied Load) means
that each end of the load is connected to two
single ended output amplifiers. Thus, we have :
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vo ut (V)
And Vout1 - Vout2 = 2Vout (V)
The differential gain named gain (Gv) for more
convenient usage is:
Vout2Vout1–
Gv =
--------------------------------------- = 2
Vin
Rfeed
------------------- Rin
Remark : Vout2 is in phase with Vin and Vout1 is
180 phased with Vin. It means that the positive
terminal of the l oudspeaker should be connected
to Vout2 and the negative to Vout1.
■Low and high frequency response
In low frequency region, the effect of Cin starts.
Cin with Rin forms a high pass filter with a -3dB cut
off frequency.
CL =
F
In high frequency region, you can limit the
bandwidth by adding a capacitor (Cfeed) in
parallel on Rfeed. Its form a l ow pass filter with a
• Supply voltage is a pure DC source (Vcc)
Regarding the load we have:
V
OUT = V
and
OUT =
I
and
P
OUT =
Then, the average current delivered by the supply
voltage is:
CC
AVG
= 2
I
The power delivered by the supply voltage is
Psupply = Vcc Icc
AVG
(W)
Then, the po wer dissip ated by the amplifier is
Pdiss = Psupply - Pout (W)
P
22Vcc
diss =
---------------------- P OUTPOUT (W)–
πR
L
sinωt (V)
PEAK
V
OUT
---------------- - (A)
L
R
2
PEAK
V
---------------------- (W )
L
2R
PEAK
V
-------------------- (A)
L
πR
The maximum theoret ical value is reached when
Vpeak = Vcc, so
π
----- = 78.5%
4
■Decoupl i ng of the ci rc u it
Two capacitors are needed to bypass properly the
TS4972, a power supply bypass capacitor Cs and
a bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in
high frequency (above 7kHz) and indirectly on the
power supply disturbances.
With 100µF, you can expect similar THD+N
performances like shown in the datasheet.
If Cs is lower than 100µF, in high frequency
increases, THD+N and disturbances on the power
supply rail are less filtered.
To the contrary, if Cs is higher t han 100µF, those
disturbances on the power supply rail are more
filtered.
Cb has an influence on THD+N in lower frequency,
but its function is critical on the final result of PSRR
with input grounded in lower frequency.
If Cb is lower than 1µF, T HD+N increase in lower
frequency (see THD+N vs frequency curves) and
the PSRR worsens up
If Cb is higher than 1µF, the benefit on THD+N in
lower frequency is small but the ben efit on PSRR
is substantial (see PSRR vs. Cb curve : fig.12).
and the maximum value is obtained when:
∂Pdiss
--------------------- - = 0
OUT
∂P
and its value is:
Note that Cin has a non-negligible effect on PSRR
in lower frequency. Lower is its value, higher is the
PSRR (see fig. 13).
■Pop and Click perfo r m ance
Pop and Click performance is intimately linked
with the size of the input capacitor Cin and the bias
voltage bypass capacitor Cb.
Remark : This maximum valu e is only depending
on power supply voltage and load values.
The efficiency is the ratio between the output
power and the power supply
OUT
P
----------------------- - =
η =
Psupply
πV
PEAK
----------------------4VCC
Size of Cin is du e to the lower cut-off frequency
and PSRR value requested. Size of Cb is due to
THD+N and PSRR requested always in lower
frequency.
Moreover, Cb determines the speed that the
amplifier turns ON. The slower th e speed is, the
softer the turn ON noise is.
21/28
TS4972
The charge time of Cb is directly proportional to
the internal generator resistance 50kΩ.
Then, the charge time constant for Cb is
τb = 50kΩxCb (s)
As Cb is directly connected to the non-inverting
input (pin 2 & 3) and if we want to minimize, i n
amplitude and duration, the output spike on Vout1
(pin 5), Cin must be charged faster than Cb. T he
charge time constant of Cin is
τin = (Rin+Rfeed)xCin (s)
Thus we have the relation
τin << τb (s)
The respect of this relation permits to minimize the
pop and click noise.
Remark
: Minimize Cin and Cb has a benefit on
pop and click phenomena but also on cost and
size of the application.
Example
: your target for the -3dB cut off
frequency is 100 Hz. With Rin=Rfeed=22 kΩ,
Cin=72nF (in fact 82nF or 100nF).
With Cb=1µF, if you choose the one of the latest
two values of Cin, the pop and click phenomena at
power supply ON or standby function ON/OFF will
be very small
50 kΩx1µF >> 44kΩx100nF (50ms >> 4.4ms).
Increasing Cin value increas es the pop and click
phenomena to an unpleasant sound at power
supply ON and standby function ON/OFF .
t
DischCs =
5Cs
------------- - = 83 ms
Icc
Now, we must consider the discharge time of Cb.
At power OFF or standby ON, Cb is discharged by
a 100kΩ resistor. So the discharge time i s about
τb
≈ 3xCbx100kΩ (s).
Disch
In the majority of application, Cb=1µF, then
τb
≈300ms >> t
Disch
dischCs
.
■Power amplifier design examples
Given :
• Load impedance : 8Ω
• Output power @ 1% THD+N : 0.5W
• Input impedance : 10kΩ min.
• Input voltage peak to peak : 1Vpp
• Bandwidth frequency : 20Hz to 20kHz (0, -3dB)
• Ambient temperature max = 50°C
• SO8 package
First of all, we must cal culate t he m inimum p ower
supply voltage to obtain 0.5W into 8Ω. With curves
in fig. 15, we can read 3.5V. Thus, the power
supply voltage value min. will be 3.5V.
Following the maximum power dissipation
equation
2
Vcc2
=
maxPdiss
2
π
R
)W(
L
Why Cs is not important in pop and click
consideration ?
Hypothesis :
• Cs = 100µF
• Supply voltage = 5V
• Supply voltage internal resistor = 0.1Ω
• Supply current of the amplifier Icc = 6mA
At power ON of the supply, the supply capacitor is
charged through the internal power supply
resistor. So, to reach 5V you need about five to ten
times the charging time constant of Cs (τs =
0.1xCs (s)).
Then, this time equal 50µs to 100µs << τb in the
majority of application.
At power OFF of the supply, Cs is discharged by a
constant current Icc. The di scharge time from 5V
to 0V of Cs is:
22/28
with 3.5V we have Pdissmax=0.31W.
Refer to power derating curves (fig. 20), with
0.31W the maxim um ambien t temperature will be
100°C. This last value could be higher if you follow
the example layout shown on the demoboard
(better dissipation).
We have Rin > 10kΩ. Let's take Rin = 10kΩ, then
Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ
in normalized value and th e gain will be Gv = 6.
TS4972
In lower frequency we want 20 Hz (-3dB cut off
frequency). Then:
CIN =
1
------------------------------ = 795nF
2π
RinFCL
So, we could use for Cin a 1µF capacitor val ue
which gives 16Hz.
In Higher frequency we want 20k Hz (-3dB cut off
frequency). The Gain Bandwidth Product of the
TS4972 is 2MHz typical and doesn't change when
the amplifier delivers power into the load.
The first amplifier has a gain of:
Rfeed
----------------- = 3
Rin
and the theoretical value of the -3dB cut-off higher
frequency is 2MHz/3 = 660kHz.
We can keep this value or limit the bandwidth by
adding a capacitor Cfeed, in parallel on Rfeed.
Then:
C
FEED =
1
-------------------------------------- - = 265pF
FEEDFCH
2π R
So, we could use for Cfeed a 220pF capacitor
value that gives 24kHz.
Now, we can calculate the value of Cb with the
formula τb = 50kΩxCb >> τin = (Rin+Rfee d)xCin
which permits to redu ce t he po p and click effects.
Then Cb >> 0.8µF.
We can choose for Cb a normalized value of 2.2µF
that gives good results in THD+N and PSRR.
In the following tables, you could find three
another examples with values required for the
demoboard.
Application n°1 : 20Hz to 20kHz bandwidth and
6dB gain BTL power amplifier.
DesignatorPart Type
R8Short Circuit
C5470nF
C6100µF
C7100nF
C9Short Circuit
C10Short Circuit
C121µF
S1, S2, S6, S7
S8
P1SMB Plug
2mm insulated Plug
10.16mm pitch
3 pts connector 2.54mm
pitch
Application n°2 : 20Hz to 20kHz bandwidth and
20dB gai n BTL power am pl i fie r.
We have also : R4 = R5, R1 = R 6, C4 = C5.
The differential gain of the amplifier is:
GVDIFF = 2
Note : Due to the VICM range (see Operating
R1
------- R4
Condition), GVDIFF must have a minim um value
shown in figure 84.
24/28
C7100nF
C9Short Circuit
C10Short Circuit
C121µF
S1, S2, S6, S72mm insulat e d Plu g
10.16mm pitch
S8
P1, P2SMB Plug
3 pts connector 2.54mm
pitch
TS4972
■Note on how to use the PSRR curves
(page 7)
We have finished a design and we have ch osen
the components values :
• Rin=Rfeed=22kΩ
• Cin=100nF
• Cb=1µF
Now, on fig. 13, we can see the PSRR (input
grounded) vs frequency curves. At 217Hz we have
a PSRR value of -36dB.
In reality we want a value about -70dB. So, we
need a gain of 34dB !
Now, on fig. 12 we can see the effect of Cb on the
PSRR (input grounded) vs. frequency. With
Cb=100µF, we can reach the -70dB value.
The process to obtain the final curve (Cb=100µF,
Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer
point by point on each frequency of the curve on
fig. 13 to the curve on fig. 12.
The measurement result is shown on the next
figure.
Fig. 85 : PSRR changes with Cb
How we measure the PSRR
?
Fig. 86 : PSRR measurement schematic
Rfeed
Vripple
Vcc
Cin
Rg
100 Ohms
1
Vin-
Vin+
7
Rin
3
Bypass
5
Standby
Cb
6
VCCGND
-
+
-
+
Bias
2
AV = -1
Vout 1
Vout 2
8
4
TS4972
■Principle of operation
• We fixed the DC voltage supply (Vcc)
• We fixed the AC sinusoidal ripple voltage
(Vripple)
• No bypass capacitor Cs is used
The PSRR value for each frequency is:
What is the PSRR
The PSRR is the Power Suppl y Rejection Ratio.
It's a kind of SVR in a determined frequency range.
The PSRR of a device, is the ratio between a
power supply disturbance and the result on the
output. We can say that the PSRR is the ability of
a device to m inimize the impact o f power supply
disturbances to the output.
?
PSRR dB() = 20 x Log10
Rms V
---------------------------------------- ----Rms Vs
ripple()
- Vs
()
+
-
Remark : The measure of the Rms voltage is not a
Rms selective measure but a full range (2 Hz to
125 kHz) Rms measure. It means that we
measure the effective Rms signal + the noise.
TOP VIEW OF THE DAISY CHAIN MECHANICAL DATA ( all drawings dimensions are in millimeters )
567
567
StdbyVccVin+
StdbyVccVin+
Vout1
8
8
Vout1
VinGnd
VinGnd
12
12
2.26 mm
2.26 mm
Vout2
Vout2
Bypass
Bypass
3
3
1.6 m m
1.6 m m
4
4
REMARKS
Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way
connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed
on the opposite way, where pin connections are not done on daisy chain samples. By that way, just
connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested.
ORDER CODE
Part Number
Temperature
Range
TSDC03IJT-40, +85°C
26/28
Package
J
•
Marking
DC3
TAPE & REEL SPECIFICATION ( top view )
User direction of feed
User direction of feed
User direction of feed
User direction of feed
A72
4972
A72
4972
TS4972
A72
4972
A72
4972
27/28
TS4972
12
3
76
5
8
4
Gnd
Bypass
Vout2
Stdby
Vcc
Vout1
Vin
+
Vin
PIN OUT (Top View)MARKING (Top View)
■ Balls are underneath
PACKAGE MECHANICAL DATA
FLIP CHIP - 8 BU MPS
0.50.5
0.5
■ Die size : (2.26mm ±10%) x (1.6mm ±10%)
■ Die height (including bumps) : 650µm ± 50
1.6
2.262.26
250µm
250µm
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