The TS487 2 i s an Audio Pow er Amplifier capable
of delivering 1W of continuous RMS Ouput Power
into 8
Ω load @ 5V.
This Audio Am plifier is exhibiting 0.1% distortion
level (THD) from a 5V supply for a Pout = 250mW
RMS. An external standby mode cont rol reduces
the supply current to less than 10n A. An internal
shutdown protection is provided.
PIN CONNECTIONS (Top View)
TS4872IJT - FLIP CHIP
8
Vout1
76
+
Vin
Vin
12
Vcc
GND
5
STDBY
Vout2
BYPASS
3
4
The TS4872 has been designed for high quality
audio applications such as m obile phones and t o
minimize the number of external components.
The unity-gain stable amplifier can be configured
by external gain setting resistors.
APPLICATIONS
■Mobile Phones (Cellular / Cordless)
■PDAs
■Laptop/Notebook computers
■Portable Audio Devices
ORDER CODE
Part
Number
Temperature
Range
TS4872IJT-40, +85°C●YW4872
J = Flip Chip Package - only available in Tape & Reel (JT)
October 2002
Package
Marking
J
TYPICAL APPLICATION SCHEMATIC
Cfeed
Vcc
Rfeed
6
Audio
Input
Vcc
Rstb
Rin
1
Vin-
Cin
Vin+
7
Bypass
3
Standby
5
Cb
Vcc
-
+
Bias
GND
2
Av=-1
+
Vout1
Vout2
TS4872
Cs
8
RL
8 Ohm
4
1/29
TS4872
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
T
T
R
Supply voltage
CC
V
Input Voltage
i
Operating Free Air Temperature Range-40 to + 85°C
oper
Storage Temperature-65 to +150°C
stg
T
Maximum Junction Temperature150°C
j
Flip Chip Thermal Resistance Junction to Ambient
thja
PdPower DissipationInternally Limited
ESDHuman Body Model2kV
ESDMachine Model200V
Latch-up Latch-up ImmunityClass A
Lead Te mpera ture (solde ring, 10sec )250°C
1. All voltages values are measured with respect to the ground pin.
2. The magnitude of input signal must never exceed V
3. Device is protected in cas e of over temperature by a thermal shutdown active @ 150°C
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
V
= +3.3V, GND = 0V, T
CC
Supply Current
CC
No input signal, no load
Standby Current
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
1)
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
= 25°C (unless otherwise specified)
amb
Vripple = 200mV rms
Ω,
68mA
101000nA
520mV
1W
Ω
0.1%
75dB
70Degrees
20dB
2MHz
3)
SymbolParameterMin.Typ.Max.Unit
I
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. Standby mode i s actived when Vstdby is tied to Vcc
2. Dynamic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
All electrical values are made by correlatio n bet ween 2.6v and 5v measurem ents
3
Supply Current
CC
No input signal, no load
Standby Current
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
= 8Ω, CL = 500pF
R
L
Gain Bandwidth Product
= 8
R
Ω
L
5.58mA
1)
Ω
Ω
Ω
Ω
2)
RFeed = 22KΩs, Vripple = 100mV rms
Ω,
101000nA
520mV
450mW
0.1%
68dB
70Degrees
20dB
2MHz
3/29
TS4872
ELECTRICAL CHARACTERISTICS
V
= 2.6V, GND = 0V, T
CC
SymbolParameterMin.Typ.Max.Unit
= 25°C (unless otherwise specified)
amb
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. S ta ndby mode is actived when Vstdby is tied to Vcc
2. Dy namic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
= 2.2V, GND = 0V, T
V
CC
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
amb
Ω
Ω
Ω
Ω
2)
RFeed = 22K
Ω,
Vripple = 200mV rms
Ω,
= 25°C (unless otherwise specified)
5.58mA
101000nA
520mV
260mW
0.1%
75dB
70Degrees
20dB
2MHz
SymbolParameterMin.Typ.Max.Unit
I
CC
I
STANDBY
Voo
Po
THD + N
PSRR
Φ
GM
GBP
1. S ta ndby mode is actived when Vstdby is tied to Vcc
2. Dy namic measurements - 20*log(r m s(Vout)/rms(Vripple)). Vripple is the surim posed sinus signal to Vc c @ f = 217Hz
Supply Current
No input signal, no load
Standby Current
1)
No input signal, Vstdby = Vcc, RL = 8
Output Offset Voltage
No input signal, RL = 8
Output Power
THD = 1% Max, f = 1kHz, RL = 8
Total Harmonic Distortion + Noise
Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8
Power Supply Rejection Ratio
f = 217Hz, RL = 8
Phase Margin at Unity Gain
M
R
= 8Ω, CL = 500pF
L
Gain Margin
R
= 8Ω, CL = 500pF
L
Gain Bandwidth Product
R
= 8
Ω
L
Ω
2)
RFeed = 22K
Ω,
Ω
Ω
Vripple = 100mVpp
Ω,
4.5mA
10nA
2mV
180mW
Ω
0.1%
75dB
70Degrees
20dB
2MHz
4/29
ComponentsFunctional Description
TS4872
Rin
Cin
RfeedFeed back resistor which sets the closed loop gain in conjunction with Rin
CsSupply Bypass capacitor which provides power supply filtering
CbBypass pin capacitor which provides half supply filtering
Cfeed
RstbPull-up resistor which fixes the right supply level on the standby pin
GvClosed loop gain in BTL configuration = 2 x (Rfeed / Rin)
Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also
forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin))
Input coupling capacitor which blocks the DC voltage at the amplifier input terminal
Low pass filter capacitor allowing to cut the high frequency
(low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed))
REMARKS
1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF.
2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the
Fig. 69 : Signal to Noise Ratio vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
100
90
RL=4
RL=8
RL=16
80
70
SNR (dB)
60
50
2.53.03.54.04.55.0
Ω
Ω
Vcc (V)
Ω
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
Fig. 71 : Signal to Noise Ratio vs Power Supply
with Weig h t e d Filt e r t y p e A
110
100
RL=4
RL=8
RL=16
90
Ω
Ω
Ω
Fig. 70 : Signa l to Nois e Ratio Vs Power Supply
with Unweighted Filter (20Hz to 20kHz)
Fig. 72 : Signal to Noise Ratio vs Power Supply
with Weighted Filter Type A
80
SNR (dB)
70
60
2.53.03.54.04.55.0
Vcc (V)
Fig. 73 : Frequency Response Gain vs Cin, &
Cfeed
10
5
0
-5
-10
Gain (dB)
-15
-20
-25
10100100010000
Cin = 82nF
18/29
Cin = 470nF
Cin = 22nF
Frequency (Hz)
Gv = 2
Cb = Cin = 1µF
THD+N < 0.4%
Tamb = 25°C
Fig. 74 : Current Consum ption vs Power
Supply Voltage
Cfeed = 330pF
Cfeed = 680pF
Cfeed = 2.2nF
Rin = Rfeed = 22kΩ
Tamb = 25°C
TS4872
2.53.03.54.04.55.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Tamb = 25°C
RL = 16
Ω
RL = 8
Ω
RL = 4
Ω
Vout1 & Vout2
Clipping Voltage Low side (V)
Power supply Voltage (V)
Fig. 75 : C urrent Consumption v s St andby
Voltage @ Vcc = 5V
7
6
5
4
3
Icc (mA)
2
1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vstandby (V)
Vcc = 5V
Tamb = 25°C
Fig. 77 : C urrent Consumption v s St andby
Voltage @ Vcc = 2.6V
6
5
Vcc = 2.6V
Tamb = 25°C
Fig. 76 : C urrent Consumption v s St andby
Voltage @ Vcc = 3.3V
6
5
4
3
Icc (mA)
2
1
0
0.00.51.01.52.02.53.0
Vstandby (V)
Vcc = 3.3V
Tamb = 25°C
Fig. 78 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
4
3
Icc (mA)
2
1
0
0.00.51.01.52.02.5
Fig. 79 : Clipping Voltage vs Power Supply
Voltage and Load Resistor
1.0
0.9
Tamb = 25°C
0.8
0.7
0.6
0.5
0.4
Vout1 & Vout2
0.3
0.2
Clipping Voltage High side (V)
0.1
0.0
2.53.03.54.04.55.0
Vstandby (V)
Power supply Voltage (V)
RL = 8
RL = 4
Ω
RL = 16
Ω
Ω
19/29
TS4872
APPLICA TI ON INFORMATION
Fig. 80 : Demoboard Schematic
Vcc
S1
Vcc
S2
GND
C1
R2
C2
R1
Neg. input
J1
Neg. input
J2
Pos input
J3
Pos input
J4
Vcc
100k
R3
S5
PositiveInput mode
R7
C3
R4
C4R5
S8
Standby
C5
+
C12
C11
1u
1u
+
Fig. 81 : Flip Chip Demoboard Components
Side
Vcc
C7
+
C6
100µ
6
1
Vin-
Vin+
7
R6
Bypass
3
Standby
5
C8
100n
Vcc
-
+
Bias
GND
2
Av=-1
+
100n
Vout1
Vout2
TS4872
U1
8
4
C9
+
470µ
C10
+
470µ
S6
OUT1
S3
GND
S4
GND
S7
Fig. 82 : Flip Chip Demoboard Top Layer
20/29
TS4872
)W(
R
)Vout2(
Pout
L
2
RMS
=
Fig. 83 : Flip C hip Demoboar d Bottom Layer
■BTL Configuration Principle
The TS4872 is a monolithic power amplifier with a
BTL output type. BTL (Bridge Tied Load) means
that each end of the load is connected to two
single ended output amplifiers. Thus, we have :
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vout (V)
And Vout1 - Vout2 = 2Vout (V)
The output power is :
The differential output voltage is
Vout2
V o ut 1 = 2Vin –
Rfeed
------------------- - (V)
Rin
The differential gain named gain (Gv) for more
convenient usage is :
Vout2Vout1–
Gv =
--------------------------------------- = 2
Vin
Rfeed
------------------- Rin
Remark : Vout2 is in phase with Vin and Vout1 is
180 phased with Vin. It means that the positive
terminal of the l oudspeaker should be connected
to Vout2 and the negative to Vout1.
■Low and high frequency response
In low frequency region, the effect of Cin starts.
Cin with Rin forms a high pass filter with a -3dB cut
off frequency
FCL =
1
------------------------------- - Hz()
2π Rin Cin
In high frequency region, you can limit the
bandwidth by adding a capacitor (Cfeed) in parallel
on Rfeed. Its form a low pass filter with a -3dB cut
off frequency
For the same power supply voltage, the output
power in BTL configuration is four times higher
Regarding the load we have :
than the output power in single ended
configuration.
OUT = V
V
PEAK
sinωt (V)
■Gain In Typical Application Schematic (cf.
page 1)
In flat region (no effect of Cin), the output voltage
of the first stage is :
Vout1 = Vin –
Rfeed
------------------- - (V)
Rin
For the second stage : Vout2 = -Vout1 (V)
and
and
OUT =
I
P
OUT =
OUT
V
---------------- - (A)
L
R
PEAK
2R
2
L
V
---------------------- (W )
21/29
TS4872
)W(
R
Vcc2
maxPdiss
L
2
2
π
=
Then, the average current delivered by the supply
voltage is:
V
I
CC
AVG
= 2
PEAK
-------------------- (A)
πR
L
Then, the po wer dissip ated by the amplifier is
Pdiss = Psupply - Pout (W)
22Vcc
diss =
P
---------------------- P OUTPOUT (W)–
L
πR
and the maximum value is obtained when:
∂Pdiss
--------------------- - = 0
∂P
OUT
and its value is:
Remark : This maximum valu e is only depending
on power supply voltage and load values.
The efficiency is the ratio between the output
power and the power supply
η =
OUT
P
----------------------- - =
Psupply
πV
PEAK
----------------------4VCC
The maximum theoret ical value is reached when
Vpeak = V c c, so
π
----- = 78. 5%
4
■Decoupl i ng of the ci rc u it
Two capacitors are needed to bypass properly the
TS4872. A power supply bypass capacitor Cs and
a bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in
high frequency (above 7kHz) and indirectly on the
power supply disturbances.
With 100µF, you can expect similar THD+N
performances like shown in the datasheet.
If Cs is lower than 100µF, in high frequency
increases, THD+N and disturbances on the power
supply rail are less filtered.
To the contrary, if Cs is higher than 100µF, those
disturbances on the power supply rail are more
filtered.
Cb has an influence on THD+N in lower frequency,
but its function is critical on the final result of PSRR
with input grounded in lower frequency.
If Cb is lower than 1µF, T HD+N increase in lower
frequency (see THD+N vs frequency curves) and
the PSRR worsens up
If Cb is higher than 1µF, the benefit on THD+N in
lower frequency is small but the ben efit on PSRR
is substantial (see PSRR vs. Cb curve : fig.12)
Note that Cin has a non-negligible effect on PSRR
in lower frequency. Lower is its value, higher is the
PSRR (see fig. 13).
■Pop a n d C lic k pe rformance
Pop and Click performance is intimately linked with
the size of the input capacitor Cin and the bias
voltage bypass capacitor Cb.
Size of Cin is due to th e lower cut off frequency
and PSRR value request and size of Cb is due to
THD+N and PSRR request always in lower
frequency.
Moreover, Cb determines the speed at which the
amplifier turns ON. The slow er the speed is , the
softer turns ON noise.
The charge time of Cb is directly proportional to
the internal generator resistance 50kΩ.
Then, the charging time constant for Cb is
τb = 50kΩxCb (s)
As Cb is directly connected to the non-inverting
input (pin 3 & 7) and if we want to minimize, in
amplitude and duration, the output spike on Vout1
(pin 8), Cin must be charged faster than Cb. T he
charge time constant of Cin is
τin = (Rin+Rfeed)xCin (s)
Thus we have the relation
τin << τb (s)
The respect of this relation permits to minimize the
pop and click noise.
Remark : Minimize Cin and Cb has a benefit on
pop and click phenomena but also on cost and
size of the application.
22/29
TS4872
Example
: your target for the -3dB cut off
frequency is 100 Hz. With Rin=Rfeed=22 kΩ,
Cin=72nF (in fact 82nF or 100nF).
With Cb=1µF, if you choose the one of the latest
two values of Cin, the pop and click phenomena at
power supply ON or standby function ON/OFF will
be very sma ll
50 kΩx1µF >> 44kΩx100nF (50ms >> 4.4ms).
Increase Cin value increases the pop and click
phenomena to an unpleasant sound at power
supply ON and standby function ON/OFF .
Why Cs is not important in pop and click
consideration ?
Hypothesis :
• Cs = 100µF
• Supply voltage = 5V
• Supply voltage internal resistor = 0.1Ω
• Supply current of the amplifier Icc = 6mA
At power ON of the supply, the supply capacitor is
charged through the internal power supply
resistor. So, to reach 5V you need about five to ten
times the charging time constant of Cs (τs =
0.1xCs (s)).
Then, this time equal 50µs to 100µs << τb in the
majority of application.
First of all, we must cal culate t he m inimum p ower
supply voltage to obtain 0.5W into 8Ω. With curves
in fig. 15, we can read 3.5V.
Thus, the power supply voltage value min. will be
3.5V.
Following the maximum power dissipation
equation
2
Vcc2
=
maxPdiss
2
π
R
)W(
L
with 3.5V we have Pdissmax=0.31W.
Referring to power derating curves (fig. 20), with
0.31W the maxim um ambien t temperature will be
100°C. This last value could be higher if you follow
the example layout shown on the demoboard
(better dissipation).
We have Rin > 10kΩ. Let's take Rin = 10kΩ, then
Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ
in normalized value and th e gain will be Gv = 6.
At power OFF of the supply, Cs is discharged by a
constant current Icc. The di scharge time from 5V
to 0V of Cs is
t
DischCs =
5Cs
------------- - = 83 ms
Icc
Now, we must consider the discharge time of Cb.
At power OFF or standby ON, Cb is discharged by
a 100kΩ resistor. So the discharge time i s about
τb
≈ 3xCbx100kΩ (s).
Disch
In the majority of application, Cb=1µF, then
τb
≈300ms >> t
Disch
dischCs
.
■Power amplifier design examples
Given :
• Load impedance : 8Ω
• Output power @ 1% THD+N : 0.5W
• Input impedance : 10kΩ min.
• Input voltage peak to peak : 1Vpp
• Bandwidth frequency : 20Hz to 20kHz (0, -3dB)
• Ambient temperature max = 50°C
In lower frequency we want 20 Hz (-3dB cut off
frequency). Then
C IN =
1
------------------------------ = 795nF
2π
RinFCL
So, we could use for Cin a 1µF capacitor value that
gives 16Hz.
In Higher frequency we want 20k Hz (-3dB cut off
frequency). The Gain Bandwidth Product of the
TS4872 is 2MHz typical and doesn't change when
the amplifier delivers power into the load.
The first amplifier has a gain of
Rfeed
----------------- = 3
Rin
and the theoretical value of the -3dB cut-off higher
frequency is 2MHz/3 = 660kHz.
We can keep this value or limit the bandwidth by
adding a capacitor Cfeed, in parallel on Rfeed.
23/29
TS4872
Then
CFEED =
1
-------------------------------------- - = 265pF
2π R
FEEDFCH
So, we could use for Cfeed a 220pF capacitor
value that gives 24kHz.
Now, we can calculate the value of Cb with the
formula τb = 50kΩxCb >> τin = (Rin+Rfee d)xCin
which permits to redu ce t he po p and click effects.
Then Cb >> 0.8µF.
We can choose for Cb a normalized value of 2.2µF
that gives good results in THD+N and PSRR.
In the following tables, you could find three another
examples with values required for the demoboard.
Remark : components with (*) marking are
optional.
Application n°1 : 20Hz to 20kHz bandwidth and
6dB gain BTL power amplifier.
Components :
DesignatorPart Type
R122k / 0.125W
Application n°2 : 20Hz to 20kHz bandwidth and
20dB gai n BTL power am pl i fie r.
Now, on fig. 13, we can see the PSRR (input
grounded) vs frequency curves. At 217Hz we have
a PSRR value of -36dB.
In reality we want a value about -70dB. So, we
need a gain of 34dB !
Now, on fig. 12 we can see the effect of Cb on the
PSRR (input grounded) vs. frequency. With
Cb=100µF, we can reach the -70dB value.
The process to obtain the final curve (Cb=100µF,
Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer
point by point on each frequency of the curve on
fig. 13 to the curve on fig. 12.
The measurement results is shown on figu re 84.
What is the PSRR ?
The PSRR is the Power Suppl y Rejection Ratio.
It’s a kind of SVR in a determined frequency
range. The PSRR of a device, is the ratio between
a power supply disturbance and the result on the
output.
Fig. 85 : PSRR measurement schematic
Rfeed
Vripple
Vcc
Rin
Cin
Rg
100 Ohms
1
Vin-
Vin+
7
Bypass
3
Standby
5
Cb
6
Vcc
-
+
Av=-1
+
Bias
GND
2
Vout1
Vout2
TS4872
8
4
■Principle of oper ation
• We fixed the DC voltage supply (Vcc)
• We fixed the AC sinusoidal ripple voltage
(Vripple)
• No bypass capacitor Cs is used
The PSRR value for each frequency is :
Vs-
RL
Vs+
We can say that the PSRR is the ability of a device
to minimize the impact of power supply
disturbances to the output.
How we measure the PSRR ?
For PSRR measurement schematic see figure 85
PSRR dB() = 20 x Log10
Rms V
---------------------------------------- ----Rms Vs
ripple()
- Vs
()
+
-
Remark : The measure of the Rms voltage is not a
Rms selective measure but a full range (2 Hz to
125 kHz) Rms measure. It means that we
measure the effective Rms signal + the noise.
26/29
TS4872
TOP VIEW OF THE DAISY CHAIN MECHANICAL DATA ( all drawings dimensions are in millimeters )
Vout1
8
76
+
Vin
Vin
Vcc
GND
12
3.02
5
STDBY
BYPASS
3
Vout2
1.52
4
REMARKS
Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way
connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed
on the opposite way, where pin connections are not done on daisy chain samples. By that way, just
connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested.
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by i mp lication or otherwise under any patent or patent rights of STMicroelec tron ic s. S pec ificat ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
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