APPLICATION INFORMATION
MONOSTABLEOPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure 2 the externalcapacitor is initiallyheld dischargedby a transistor inside
the timer.
V
CC
Reset
Trigger
Out
3
2
48
7
6
5
1
R
C
Control Voltage
0.01 F
µ
TS3V555
Figure2
CAPACITOR VOLTAGE = 2.0V/div
Ω
Ω
µ
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
R = 9.1k , C = 0.01 F , R = 1.0k
L
Figure3
TYPICAL CHARACTERISTICS
CC
SUPPLYVOLTAGE,V (V)
CC
SUPPLY CURRENT, I ( A)
µ
300
200
100
0481216
Figure 1 : Supply Current (each timer)
versussupply voltage.
Thecircuittriggersona negative-goinginput signal
whenthelevelreaches1/3V
CC
. Oncetriggered,the
circuit remains in this state until the set time has
elapsed,even if it is triggered again during this
interval. The duration of the output HIGH state is
given by t =1.1 R x C.
Noticethat since the chargerate and the threshold
level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. Applying a negative pulse
simultaneouslyto theResetterminal(pin4)andthe
Trigger terminal (pin 2) during the timing cycle
dischargesthe external capacitor and causes the
cycle to start over. The timingcycle now starts on
thepositiveedgeoftheresetpulse.Duringthetime
the reset pulse is applied,the output is driven toits
LOW state.
When a negative trigger pulse is applied to pin 2,
the flip-flop is set,releasing the shortcircuit across
theexternalcapacitorand drivingthe outputHIGH.
The voltage across the capacitor increases exponentiallywith the time constant τ =RxC.
Whenthe voltageacross the capacitor equals 2/3
V
CC
, thecomparatorresets the flip-flopwhichthen
discharges the capacitor rapidly and drives the
output to its LOW state.
Figure3 shows the actualwaveformsgeneratedin
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.
TS3V555
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