POSITIVE AND NEGATIVE OUTPUT CURRENTUP TO 1.2AAND – 1.7A
.
A TWO LEVEL COLLECTOR CURRENT LIMITATION
.
COMPLETETURN OFF AFTERLONG DURATIONOVERLOADS
.
UNDERANDOVER VOLTAGELOCK-OUT
.
SOFT START BY PROGRESSIVE CURRENT
LIMITATION
.
DOUBLEPULSESUPPRESSION
.
BURST MODE OPERATION UNDER STANDBY CONDITIONS
DESCRIPTION
In amasterslave architecture,theTEA2164control
IC achieves the slave function.Primarilydesigned
for TV receivers and monitors applications, this
circuitprovidesaneasy synchronizationand smart
solutionfor low powerstand by operation.
Located at the primary side the TEA2164 Control
IC ensures:
- the powersupply start-up
- the power supply control under stand-by conditions
- the process of the regulation signalssent by the
mastercircuitlocated at the secondaryside
- directbasedriveofthebipolarswitchingtransistor
- the protection of the transistor and the power
supplyunder abnormalconditions.
For more details, refer toapplicationnote AN409.
TEA2164
POWERDIP16
(Plastic Package)
ORDER CODE : TEA2164
PINCONNECTIONS
LONG CAPACITOR OVERLOAD CAPACITOR
OSCILLATOR TIMING RESISTOR
OSCILLATOR TIMING CAPACITOR
December 1992
GROUND
I COPY
SUBSTRATE
SUBSTRATE
PULSE INPUT
VSUPPLY VOLTAGE
1
2
3
4
5
6
7
8
16
CC
OUTPUT STAGE POSITIVE SUPPLY VOLTAGE
15
OUTPUT (BASE CURRENT)
14
SUBSTRATE
13
SUBSTRATE
12
ISENSE
11
C (max.)
LOW FREQUENCY OSCILLATOR CAPACITOR
10
FEEDBACK INPUT IS BURST MODE
9
2164-01.EPS
1/15
TEA2164
BLOCK DIAGRAM
2/15
2164-02.EPS
TEA2164
Figure 1 : SimplifiedApplication Diagram
ABSOLUTEMAXIMUM RATINGS
SymbolParameterValueUnit
V
CC
V+Positive Power Supply of the Output Stage V15-V118V
V–Negative Power Supply V4, 5, 12, 13-V1– 5V
-V–
V
CC
V+ - V–
I
out+
I
out–
T
T
stag
Positive Power Supply V16-V118V
Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 1320V
OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION (continued)
T
syn
T
O
OUTPUT STAGE
I
14/I2
I
BON
VERY LOW FREQUENCY OSCILLATOR
Synchronization Window1.01.5
IcCopy CurrentGain1000
Base Current Starting Pulse300mA
Burst Duty Cycle13%
TEA2164
2164-05.TBL
I. FIELD OF APPLICATION
The TEA2164 control circuit has been designed
primarily for discontinuousmode flybackbuilt with
a master-slave architecture, whatever the field of
application.
Butdue to its capabilityto synchronizethe transistor switching-off with an external signal (line flyback)and dueto an adaptedburst-modeoperation
for a low power stand-by operation, the TEA2164
offers a smart solution for monitors and TV sets
applications.
Powersupply main features:
- maximumoutput power 140W (transistorforced
gain : 3.5)
In this configuration,themastercircuit generatesa
pulsewidthmodulatedsignalissuedfromthemonitoring of the output voltage which needs the best
accuracy(inTVapplications:thehorizontaldeflectionstagesupplyvoltage).Themastercircuitpower
supplycan be suppliedby another output.
The PWM signalare sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon commands; and negative pulsesare transistor
switching-offcommands(Figure 4). In this configuration,only by synchronizingthe masteroscillator,
the switchingtransistor may be synchronizedwith
an externalsignal.
II.2.Stand-byMode
In this configuration the master circuit no longer
Figure 4 : MasterSlave Mode Waveforms
sends PWM signals, the structure is not synchronized ; and the TEA2164 operates in burst mode.
The averagepower consumptionat the secondary
side may be very low 1W ≤ P ≤ 6W (as it is
consumedin TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
outputvoltages.Voltageonfeed-backisappliedon
Pin 9.
Burstperiodis externallyprogrammedbycapacitor
C1.
II.3.Power Supply Start-up
After the mains have been switched-on, the V
CC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectifiedhigh voltage.When VccreachesV
CC
start
threshold(9V typ), theTEA2164startsoperatingin
burst mode. Sinceavailable outputpower islow in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode duringstartup (Figure 6).
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronizationor after Vcc
stopcrossing (Figure7).
In flyback converters, this function protects the
powersupply against outputvoltagerunaway.
Under Voltage Lock-out
The TEA2164 controlcircuitstops operatingwhen
goes under VCCstop.
V
CC
8/15
Power Limitation,Current Protection, Long
Duration OverloadProtection
- Output power limitation : by a pulse by pulse
collectorcurrentlimitation the TEA2164 limits the
maximum output power. V
isthe correspond-
CM1
ing voltagethreshold,its detection is memorized
up to the next period.
- Currentprotection(transistorprotection)
Under particular conditions a hard overload or
short circuit may induce a fluxrunawayin spiteof
the currentlimitation (V
CM1
).
The TEA2164 control circuit features a second
current protection, V
. When this thresholdis
CM2
reached an internal flip-flop memorizes it and
2164-10.EPS
TEA2164
output conduction signals are inhibited. The circuitwill sendbasedrivesagainaftercapacitorC1
discharge(Figure7).
- Longdurationoverloadprotection : (Figure 8)
An overload is detectedwhen thesense-voltage
on Pin 11 reachesV
before a negativepulse
CM3
hasbeenappliedto Pin 6. In thiscasethe capacitor C2 (connectedto Pin3) is charged with I
up to theendof the period and discharged with I
disch until a next V
keeps charging at each period and its voltage
encreasesgradually. When the voltage on Pin3
exceeds V
, the TEA2164 control circuit stops
C2
sending base drives and memorizes this event.
No restart is allowed as long as V
than V
andVCChigherthan 4.8V.
C2
pin 3
is higher
* Remark:
- The harder is the overload the faster is the protection
- The capacitorkeeps chargingbetween two burst
after V
CM2
detection.
2164-11.EPS
Figure 9 : LongDuration Overload Detection
2164-11.EPS
2164-13.EPS
9/15
TEA2164
Figure 10 : RepetitiveOver-current Protection
III. SWITCHINGOSCILLATOR AND SYNCHRONIZATION
III.1. Switchingoscillator
Whenthe TEA2164controlcircuitoperatesin burst
mode, the switching frequencyis fixed by the free
frequency oscillator. The period is determined by
two external componentsC
andRO.
O
III.2. Synchronization
Whenthe master-circuitstarts to send pulsesboth
Figure 11 : Free Frequency Running
oscillators are not synchonuous. In order to avoid
any erratic conductionof the power transistor,the
firstsynchronizationpulse will arrive simultanously
with thesawtoothreturn of the TEA2164oscillator.
Toget synchronizationthe free frequency must be
higher than the synchronizationfrequency.
P1 and P2 are masked due to the synchronization window
Cases (2) (3) (4) donot occur in normal operating.
IV - MAXIMUM DUTY CYCLE LIMITATION
Burstmode :Themaximum dutycycleiscontrolled
by the voltage on Pin 9 (Figure13).
Synchronizedmode : Normallythe maximum duty
cycle is set by the master circuit. Oowever the
maximum conducting time will never exceed the
value given by the comparison of the oscillator
wave-formwith the 2.5Vinternal threshold.
V - OUTPUTSTAGE
TEA2164output stage has beendesignedto drive
switchingbipolar transistor.
- Eachbase drive beginswitha positivepulseI
BON
(2) NEGATIVE PULSE MISSING
Transistor turn-off is ensured by VCM1 current limitation crossing or byan internaltON (max.) limitation set by a 2.5V threshold
(4) Fsynchro < 0.65 Fo
Signal S1 triggers burst oscillator capacitor discharge.
The TEA2164 restarts in burst-mode
thatrealizesan efficienttransistorturn-on.
- After the starting pulse I
, the base currentis
BON
proportionalto the collector current. The current
gain is easily fixed by a resistorR (Figure14).
- A fast and safetransistor turn-off is realized by a
fastpositivebase currentcut-off and by applying
a negativebase drive which draws stored carriers.A typical 0.7sdelaypreventsfromcross-conductionof positiveand negative outputstages.
Remark : In order to reducepower dissipationon
the positiveoutput stage with the lowgain transistors,forhighbasecurrentsthepositiveoutputstage
operatesin saturated mode (Figure 15). This can
be achievedby using a resistorbetween V
CC
and
V+.
2164-17.EPS / 2164-18.EPS
2164-19.EPS
11/15
TEA2164
Figure 13 : MaximumDuty Cycle Limitation
Figure 14 : OutputStage Architectureand Base Drive
2164-20.EPS
V
4-5-12-13
V
I
14
B
R
S
R
B
I
C
The energy of the starting burst must be high
enough to ensure start-up, then the capacitor C1
must be higher in these applicationsthan on TV
application(typ. : 1µF).
1615
V
CC
CURRENT
MIRROR
Virtual
Ground
2
I
COPY
VI - MONITOR APPLICATIONS
In most of monitor applications, the power supply
must start-up under full load conditions and the
stand-by mode is no longer useful.
Information furnished is believed to be accurate andreliable.However, SGS-THOMSONMicroelectronics assumes no responsibility
for the consequences of use of such information norfor any infringement ofpatents or other rights of third partieswhich may result
from itsuse. Nolicence isgranted by implication orotherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics productsare not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I
2
I
C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
2
C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
2
the I
C Standard Specificationsas defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
15/15
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