SGS Thomson Microelectronics TDA9210 Datasheet

150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS

FEATURE

■ 150 MHZ PIXEL RATE

■ 2.7 ns RISE ANDFALL TIME

2

■ I

C BUS CONTROLLED

■ GREY SCALE TRACKING VERSUS BRIGHT-

NESS

■ OSD MIXING

■ NEGATIVE FEED-BACK FOR DC COUPLING

APPLICATION

■ BEAM CURRENT ATTENUATION (ABL)

■ PEDESTRAL CLAMPING ON OUTPUT

STAGE

■ POSSIBILITY OF LIGHT OR DARK GREY

OSD BACKGROUND

■ OSD INDEPENDENT CONTRAST CONTROL

■ ADJUSTABLE BANDWIDTH

■ INPUT BLACK LEVEL CLAMPING WITH

BUILT-IN CLAMPING PULSE

■ STAND-BY MODE

■ 5 V TO 8 V POWER SUPPLY

■ SYNC CLIPPING FUNCTION (SOG)

DESCRIPTION

The TDA9210 is an I2C Bus controlled RGB pre­amplifier designed for Monitor applications, able to
mix the RGB signals coming from any OSD de­vice. The usual Contrast, Brightness, Drive and
Cut-Off Controls are provided.

In addition, it includes the following features:
– OSD contrast,
– Bandwidth adjustment,
– Grey background,
– Internal back porch clamping pulse generator.

TDA9210

PRELIMINARY DATA

DIP20

(Plastic Package)

ORDER CODE: TDA9210

The RGB incoming signals are amplified and
shaped to drive any commonly used video amplifi­ers without intermediate follower stages. Even
though encapsulated in a 24-pin package only,
this IC allows any kind of CRT Cathode coupling:

– AC coupling with DC restore,
– DC coupling with Feed-back from Cathodes,
– DC coupling with Cut-Off controls of the Video

amplifier (ST Amplifiers TDA9533/9530).

As for any ST Video pre-amplifier, the TDA9210 is
able to drive a real load without any external inter­face.

One of the main advantages of ST devices is their
ability to sink and source currents while most of
the devices from our competitors have problems
to sink large currents.

These driving capabilities combined with an origi­nal output stage structure suppress any static cur­rent on the output pins and therefore reduce dra­matically the power dissipation of the device.

Extensive integrationcombinedwith high perform­ance and advanced features make the TDA9210
one of the best choice for any CRT Monitor in the
14” to 17” range.

Perfectly matched with the ST Video Amplifiers
TDA9535/36, these 2 products offer a complete
solution for high performance and cost-optimized
Video Board Application.

Version 3.1

March 2000 1/19

This is preliminary information on anew product now in development or undergoing evaluation. Details are subject to change without notice.

1

TDA9210

1 - PIN CONNECTIONS

IN1

ABL

IN2

GNDL

IN3

GNDA

V

CCA

OSD1
OSD2

OSD3

10

1
2
3

4

5

6
7
8

9

20
19

18

17
16
15

14

13
12
11

BLK
HSYNC or BPCP

OUT1
V

CCP

OUT2
GNDP
OUT3

SDA
SCL

FBLK

2 - PIN DESCRIPTION

Pin Number Symbol Description

1 IN1 Red Video Input
2 ABL ABL Input
3 IN2 Green Video Input
4 GNDL Logic Ground
5 IN3 Blue Video Input
6 GNDA Analog Ground
7V
8 OSD1 Red OSD Input

9 OSD2 Green OSD Input
10 OSD3 Blue OSD Input
11 FBLK Fast Blanking
12 SCL SCL
13 SDA SDA
14 OUT3 Blue Video Output
15 GNDP Power Ground
16 OUT2 Green Video Output
17 V
18 OUT1 Red Video Output
19 HSYNC/BPCP HSYNC/BPCP
20 BLK Blanking Input

CCA

CCP

Analog VCC(5V)

Power VCC(5 V to 8 V)

2/19

3 - BLOCK DIAGRAM

TDA9210

IN1

IN2

IN3

ABL

GNDL

GNDA

VCCA

TDA9210

V

REF

1

Clamp

3

5

2

BPCP

4

6
7

19 13 12 8 9 10

HSYNC SDA SCL

or BPCP

BLK

20

Contrast/8bit

Latches

2

I

C

Bus

Decoder

Contrast

D/A

OSD
Cont.

4bits

FBLK

11

Output Clamp Pulse

(OCL)

Drive

Green Channel

Blue Channel

Brightness

8bits

OSD1 OSD2 OSD3

Drive

3x8bits

I C

Output

Stage

Cut-off

8bits

VCCP

17

DC Level

V

REF

Output

4bits

18

16

14

15

OUT1

OUT2

OUT3

GNDP

See Figure 8 for complete BPCP and OCL generation diagram

4 - FUNCTIONAL DESCRIPTION

4.1 - RGB Input

The three RGBinputs have to be supplied through
coupling capacitors (100 nF).

The maximum input peak-to-peak video amplitude
is 1 V.

The input stage includes a clamping function. The
clamp uses the input serial capacitor as a ”memo­ry capacitor”.

To avoid a discharge of the serial capacitorduring
the line (due to leakage current), the input voltage
is referenced to the ground.

The clamp is gated by an internally generated
”Back Porch Clamping Pulse” (BPCP). Register 8
allows to choose the way to generate this BPCP
(see Figure 1).

When bit 0 is set to 0, the BPCP is synchronized
on the trailing or leading edge of HSYNC (Pin 19)
(bit 1 = 0: trailing edge, bit 1 = 1: leading edge).

3/19

TDA9210

Additionally, the IC automatically workswith either
positive or negative HSYNC pulses.

– When bit 0 is set to 1, BPCP is synchronized on

the leading edge of the blanking pulse BLK
(Pin 20). One can use a positive or negative
blanking pulse by programming bit 0 in
Register 9 (See I2C Table 3).

– BPCPwidth canbeadjusted withbit 2 and3(see

Register 8, I2C table 2).

– If the application already provides the Back

Porch Clamping Pulse, bit 4 must be set to 1
(providing a direct connection between Pin 19
and internal BPCP).

4.2 - Synchro Clipping Function

This function is available on channel 2 (Green
Channel). When using the Sync On Green (SOG)
(Synchro pulse included in the green channel in-

Figure 1.

R8b0=0 and R8b1=0

HSYNC/BPCP (Pin19)

Internal BPCP

put) the synchro clipping function must be activat­ed (bit 7 set to 1 in register 9) in order to keep the
right green output levels and avoid unbalanced
colours.

4.3 - Blanking Input

The Blanking pin (FBLK) is TTL compatible.
The Blanking pulse can be:
– positive or negative
– line or Composite-type (but not Frame-type).

4.4 - Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling si­multaneously the gain of the three internal amplifi­ers through the I2C bus interface. Register 1 al­lows the adjustment in a range of48 dB.

R8b0=0 and R8b1=1

HSYNC/BPCP (Pin19)

Internal BPCP

R8b0=1

R8b4 =1

HSYNC/BPCP (Pin19)

BLK (Pin20)

Internal BPCP

Internal BPCP

4.5 - ABL Control

The TDA9210 includes an ABL (automatic beam
limitation) input to attenuate the RGB Video sig­nals depending on the beam intensity.

The operating range is 2 V(from3 V to 1 V). A typ­ical 15 dB maximum attenuation is applied to the
output signal whatever the contrast adjustment is.
(See Figure 2 ).

When the ABL feature is not used, the ABL input
(Pin 2) must be connected to a5 V supplyvoltage.

4/19

TDA9210

Figure 2.

Attenuation (dB)

0

-2

-4

-6

-8

-10

-12

-14

-16
0

(V)

V

ABL

4321

5

4.6 - Brightness Adjustment (8 bits)
Brightness adjustment iscontrolled by the I2C Bus

via Register 2. It consists of adding the same DC
voltage to the three RGB signals, after contrast ad­justment. When the blanking pulse equals 0, the
DC voltageis set to a value which canbe adjusted
between 0 and 2V with 8mV steps (see Figure 3).

The DC output level is forced to the ”Infra Black”
level (VDC) when the blanking pulse is equal to 1.

4.7 - Drive Adjustment (3 x 8 bits)
In order to adjust the white balance, the TDA9210

offers the possibility of adjusting separately the
overall gain of each channel thanks to the I2C bus
(Registers 3, 4 and 5).

The very large drive adjustment range (48 dB) al­lows different standards or custom color tempera­tures.

It can also be usedto adjust theoutput voltages at
the optimum amplitude to drive the CRT drivers,
keeping the whole contrast control for the end­user only.

The drive adjustment is located after the Contrast,
Brightness and OSD switch blocks, so it does not
affect the white balance setting when the BRT is
adjusted. It also operates on the OSD portion of
the signal.

4.8 - OSD Inputs

The TDA9210 allows to mix the OSD signals into
the RGB main picture. The four pins dedicated to
this function are the following:

– ThreeTTLRGB inputs(Pins 8, 9, 10) connected

to the three outputs of the corresponding OSD
processor.

– One TTL fast blanking input (Pin 11) also con-

nected to the FBLK output of the OSDprocessor.

When a high level is present on the FBLK, the IC
acts as follows:

– The three main picture RGB input signals (IN1,

IN2, IN3) are internally switched to the internal
input clamp reference voltage.

– The three output signals are set tothe voltage

corresponding to the three OSD input logic
states (0 or 1). (See Figure3).

If the OSD input is at low level, the output and
brightness voltages (V

) are equal.

BRT

If the OSD input is at high level,the output voltage
is V

, where V

OSD

OSD=VBRT

+ OSD and OSD is

an I2C bus-controlled voltage.
OSD varies between 0 V to 4.9 V by 320 mV steps

via Register 7 (4 bits). The same variation is ap­plied simultaneously to the three channels provid­ing the OSD contrast.

The grey color can be obtained on output signals
when:

– OSD1 = 1, OSD2 = 0 and OSD3 = 1,
– A special bit (bit 5 or 6) in Register 9 is set to 1.
If R9b5 is set to 1, lightgrey is obtained on output.
If R9b6 is set to 1, dark grey is obtained on output.
In the case where R9b5 and R9b6are set to 0, the

normal operation is provided on output signals.

4.9 - Output Stage

The overall waveforms of the output signal are
shown in Figure 3 and Figure 4. The three output
stages, which are large bandwidth output amplifi­ers, are able to deliver up to 4.4 VPPfor0.7VPPon
input.

When a high level is applied on the BLK input
(Pin 20), the three outputs are forced to ”Infra
Black” level (VDC)thanks to a sample and hold cir­cuit (described below).

The black level (which is the output voltage out­side the blanking pulse with minimum brightness
and no Video input signals) is 400 mV higher than
VDC.

The brightness level (V

) is then obtained by

BRT

programming register 2 (see I2C table 1).
The sample and hold circuit is used to control the

”Infra Black” level in the range of 0.5 V to 2.5 V via
Register 6 (in case of AC coupling) or Registers
10, 11, 12 (in case of DC coupling) .

This sampling occurs during an internal pulse
(OCL) generated inside the blanking pulse win­dow.

Refer to “CRT cathode coupling” part for further
details.

5/19

TDA9210

Functioning with 5 V Power V

CC

To simplify the application, it is possible to supply
the power VCCwith 5 V (insteadof 8 V nominal)at
the expense of output swing voltage.

Functioning without Blanking Pulse

If noblanking pulse is applied to the TDA9210, the
internal BPCP can be connected to the sample

Figure 3. Waveforms VOUT, BRT, CONT, OSD

HSYNC

BPCP

BLK

Video IN

FBLK

OSD IN

and hold circuit (Register 8, bit 7 = 1 and BLK pin
grounded) so that the output DC level is still con­trolled by I2C.

To ensure the device correct behavior in the worst
possible conditions, the Brightness Register must
be set to 0.

Notes :

V

1.
V

2.
V

3.
V

4.
V

5.

DC
BLACK
BRT
CONT
OSD

V
V
V

V
V

0.5 to 2.5V

=

V

=

V

=

V

=

V

=

V

V

OUT1 ,

(4)

CONT

(5)

OSD

(3)

BRT

(2)

BLACK

(1)

DC

+ 0.4V

DC

+ BRT (with BRT = 0 to 2V)

BLACK

+ CONT = k x Video IN (CONT = 4.4VPPmax. for VIN= 0.7VPP)

BRT

+ OSD (OSD max. = 4.9VPP, OSD min = 0VPP)

BRT

OUT2

,V

OUT3

OSD

CONT
BRT

0.4V fixed

6/19