SGS Thomson Microelectronics TDA9210 Datasheet

150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS

FEATURE

■ 150 MHZ PIXEL RATE

■ 2.7 ns RISE ANDFALL TIME

2

■ I

C BUS CONTROLLED

■ GREY SCALE TRACKING VERSUS BRIGHT-

NESS

■ OSD MIXING

■ NEGATIVE FEED-BACK FOR DC COUPLING

APPLICATION

■ BEAM CURRENT ATTENUATION (ABL)

■ PEDESTRAL CLAMPING ON OUTPUT

STAGE

■ POSSIBILITY OF LIGHT OR DARK GREY

OSD BACKGROUND

■ OSD INDEPENDENT CONTRAST CONTROL

■ ADJUSTABLE BANDWIDTH

■ INPUT BLACK LEVEL CLAMPING WITH

BUILT-IN CLAMPING PULSE

■ STAND-BY MODE

■ 5 V TO 8 V POWER SUPPLY

■ SYNC CLIPPING FUNCTION (SOG)

DESCRIPTION

The TDA9210 is an I2C Bus controlled RGB pre­amplifier designed for Monitor applications, able to
mix the RGB signals coming from any OSD de­vice. The usual Contrast, Brightness, Drive and
Cut-Off Controls are provided.

In addition, it includes the following features:
– OSD contrast,
– Bandwidth adjustment,
– Grey background,
– Internal back porch clamping pulse generator.

TDA9210

PRELIMINARY DATA

DIP20

(Plastic Package)

ORDER CODE: TDA9210

The RGB incoming signals are amplified and
shaped to drive any commonly used video amplifi­ers without intermediate follower stages. Even
though encapsulated in a 24-pin package only,
this IC allows any kind of CRT Cathode coupling:

– AC coupling with DC restore,
– DC coupling with Feed-back from Cathodes,
– DC coupling with Cut-Off controls of the Video

amplifier (ST Amplifiers TDA9533/9530).

As for any ST Video pre-amplifier, the TDA9210 is
able to drive a real load without any external inter­face.

One of the main advantages of ST devices is their
ability to sink and source currents while most of
the devices from our competitors have problems
to sink large currents.

These driving capabilities combined with an origi­nal output stage structure suppress any static cur­rent on the output pins and therefore reduce dra­matically the power dissipation of the device.

Extensive integrationcombinedwith high perform­ance and advanced features make the TDA9210
one of the best choice for any CRT Monitor in the
14” to 17” range.

Perfectly matched with the ST Video Amplifiers
TDA9535/36, these 2 products offer a complete
solution for high performance and cost-optimized
Video Board Application.

Version 3.1

March 2000 1/19

This is preliminary information on anew product now in development or undergoing evaluation. Details are subject to change without notice.

1

TDA9210

1 - PIN CONNECTIONS

IN1

ABL

IN2

GNDL

IN3

GNDA

V

CCA

OSD1
OSD2

OSD3

10

1
2
3

4

5

6
7
8

9

20
19

18

17
16
15

14

13
12
11

BLK
HSYNC or BPCP

OUT1
V

CCP

OUT2
GNDP
OUT3

SDA
SCL

FBLK

2 - PIN DESCRIPTION

Pin Number Symbol Description

1 IN1 Red Video Input
2 ABL ABL Input
3 IN2 Green Video Input
4 GNDL Logic Ground
5 IN3 Blue Video Input
6 GNDA Analog Ground
7V
8 OSD1 Red OSD Input

9 OSD2 Green OSD Input
10 OSD3 Blue OSD Input
11 FBLK Fast Blanking
12 SCL SCL
13 SDA SDA
14 OUT3 Blue Video Output
15 GNDP Power Ground
16 OUT2 Green Video Output
17 V
18 OUT1 Red Video Output
19 HSYNC/BPCP HSYNC/BPCP
20 BLK Blanking Input

CCA

CCP

Analog VCC(5V)

Power VCC(5 V to 8 V)

2/19

3 - BLOCK DIAGRAM

TDA9210

IN1

IN2

IN3

ABL

GNDL

GNDA

VCCA

TDA9210

V

REF

1

Clamp

3

5

2

BPCP

4

6
7

19 13 12 8 9 10

HSYNC SDA SCL

or BPCP

BLK

20

Contrast/8bit

Latches

2

I

C

Bus

Decoder

Contrast

D/A

OSD
Cont.

4bits

FBLK

11

Output Clamp Pulse

(OCL)

Drive

Green Channel

Blue Channel

Brightness

8bits

OSD1 OSD2 OSD3

Drive

3x8bits

I C

Output

Stage

Cut-off

8bits

VCCP

17

DC Level

V

REF

Output

4bits

18

16

14

15

OUT1

OUT2

OUT3

GNDP

See Figure 8 for complete BPCP and OCL generation diagram

4 - FUNCTIONAL DESCRIPTION

4.1 - RGB Input

The three RGBinputs have to be supplied through
coupling capacitors (100 nF).

The maximum input peak-to-peak video amplitude
is 1 V.

The input stage includes a clamping function. The
clamp uses the input serial capacitor as a ”memo­ry capacitor”.

To avoid a discharge of the serial capacitorduring
the line (due to leakage current), the input voltage
is referenced to the ground.

The clamp is gated by an internally generated
”Back Porch Clamping Pulse” (BPCP). Register 8
allows to choose the way to generate this BPCP
(see Figure 1).

When bit 0 is set to 0, the BPCP is synchronized
on the trailing or leading edge of HSYNC (Pin 19)
(bit 1 = 0: trailing edge, bit 1 = 1: leading edge).

3/19

TDA9210

Additionally, the IC automatically workswith either
positive or negative HSYNC pulses.

– When bit 0 is set to 1, BPCP is synchronized on

the leading edge of the blanking pulse BLK
(Pin 20). One can use a positive or negative
blanking pulse by programming bit 0 in
Register 9 (See I2C Table 3).

– BPCPwidth canbeadjusted withbit 2 and3(see

Register 8, I2C table 2).

– If the application already provides the Back

Porch Clamping Pulse, bit 4 must be set to 1
(providing a direct connection between Pin 19
and internal BPCP).

4.2 - Synchro Clipping Function

This function is available on channel 2 (Green
Channel). When using the Sync On Green (SOG)
(Synchro pulse included in the green channel in-

Figure 1.

R8b0=0 and R8b1=0

HSYNC/BPCP (Pin19)

Internal BPCP

put) the synchro clipping function must be activat­ed (bit 7 set to 1 in register 9) in order to keep the
right green output levels and avoid unbalanced
colours.

4.3 - Blanking Input

The Blanking pin (FBLK) is TTL compatible.
The Blanking pulse can be:
– positive or negative
– line or Composite-type (but not Frame-type).

4.4 - Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling si­multaneously the gain of the three internal amplifi­ers through the I2C bus interface. Register 1 al­lows the adjustment in a range of48 dB.

R8b0=0 and R8b1=1

HSYNC/BPCP (Pin19)

Internal BPCP

R8b0=1

R8b4 =1

HSYNC/BPCP (Pin19)

BLK (Pin20)

Internal BPCP

Internal BPCP

4.5 - ABL Control

The TDA9210 includes an ABL (automatic beam
limitation) input to attenuate the RGB Video sig­nals depending on the beam intensity.

The operating range is 2 V(from3 V to 1 V). A typ­ical 15 dB maximum attenuation is applied to the
output signal whatever the contrast adjustment is.
(See Figure 2 ).

When the ABL feature is not used, the ABL input
(Pin 2) must be connected to a5 V supplyvoltage.

4/19

TDA9210

Figure 2.

Attenuation (dB)

0

-2

-4

-6

-8

-10

-12

-14

-16
0

(V)

V

ABL

4321

5

4.6 - Brightness Adjustment (8 bits)
Brightness adjustment iscontrolled by the I2C Bus

via Register 2. It consists of adding the same DC
voltage to the three RGB signals, after contrast ad­justment. When the blanking pulse equals 0, the
DC voltageis set to a value which canbe adjusted
between 0 and 2V with 8mV steps (see Figure 3).

The DC output level is forced to the ”Infra Black”
level (VDC) when the blanking pulse is equal to 1.

4.7 - Drive Adjustment (3 x 8 bits)
In order to adjust the white balance, the TDA9210

offers the possibility of adjusting separately the
overall gain of each channel thanks to the I2C bus
(Registers 3, 4 and 5).

The very large drive adjustment range (48 dB) al­lows different standards or custom color tempera­tures.

It can also be usedto adjust theoutput voltages at
the optimum amplitude to drive the CRT drivers,
keeping the whole contrast control for the end­user only.

The drive adjustment is located after the Contrast,
Brightness and OSD switch blocks, so it does not
affect the white balance setting when the BRT is
adjusted. It also operates on the OSD portion of
the signal.

4.8 - OSD Inputs

The TDA9210 allows to mix the OSD signals into
the RGB main picture. The four pins dedicated to
this function are the following:

– ThreeTTLRGB inputs(Pins 8, 9, 10) connected

to the three outputs of the corresponding OSD
processor.

– One TTL fast blanking input (Pin 11) also con-

nected to the FBLK output of the OSDprocessor.

When a high level is present on the FBLK, the IC
acts as follows:

– The three main picture RGB input signals (IN1,

IN2, IN3) are internally switched to the internal
input clamp reference voltage.

– The three output signals are set tothe voltage

corresponding to the three OSD input logic
states (0 or 1). (See Figure3).

If the OSD input is at low level, the output and
brightness voltages (V

) are equal.

BRT

If the OSD input is at high level,the output voltage
is V

, where V

OSD

OSD=VBRT

+ OSD and OSD is

an I2C bus-controlled voltage.
OSD varies between 0 V to 4.9 V by 320 mV steps

via Register 7 (4 bits). The same variation is ap­plied simultaneously to the three channels provid­ing the OSD contrast.

The grey color can be obtained on output signals
when:

– OSD1 = 1, OSD2 = 0 and OSD3 = 1,
– A special bit (bit 5 or 6) in Register 9 is set to 1.
If R9b5 is set to 1, lightgrey is obtained on output.
If R9b6 is set to 1, dark grey is obtained on output.
In the case where R9b5 and R9b6are set to 0, the

normal operation is provided on output signals.

4.9 - Output Stage

The overall waveforms of the output signal are
shown in Figure 3 and Figure 4. The three output
stages, which are large bandwidth output amplifi­ers, are able to deliver up to 4.4 VPPfor0.7VPPon
input.

When a high level is applied on the BLK input
(Pin 20), the three outputs are forced to ”Infra
Black” level (VDC)thanks to a sample and hold cir­cuit (described below).

The black level (which is the output voltage out­side the blanking pulse with minimum brightness
and no Video input signals) is 400 mV higher than
VDC.

The brightness level (V

) is then obtained by

BRT

programming register 2 (see I2C table 1).
The sample and hold circuit is used to control the

”Infra Black” level in the range of 0.5 V to 2.5 V via
Register 6 (in case of AC coupling) or Registers
10, 11, 12 (in case of DC coupling) .

This sampling occurs during an internal pulse
(OCL) generated inside the blanking pulse win­dow.

Refer to “CRT cathode coupling” part for further
details.

5/19

TDA9210

Functioning with 5 V Power V

CC

To simplify the application, it is possible to supply
the power VCCwith 5 V (insteadof 8 V nominal)at
the expense of output swing voltage.

Functioning without Blanking Pulse

If noblanking pulse is applied to the TDA9210, the
internal BPCP can be connected to the sample

Figure 3. Waveforms VOUT, BRT, CONT, OSD

HSYNC

BPCP

BLK

Video IN

FBLK

OSD IN

and hold circuit (Register 8, bit 7 = 1 and BLK pin
grounded) so that the output DC level is still con­trolled by I2C.

To ensure the device correct behavior in the worst
possible conditions, the Brightness Register must
be set to 0.

Notes :

V

1.
V

2.
V

3.
V

4.
V

5.

DC
BLACK
BRT
CONT
OSD

V
V
V

V
V

0.5 to 2.5V

=

V

=

V

=

V

=

V

=

V

V

OUT1 ,

(4)

CONT

(5)

OSD

(3)

BRT

(2)

BLACK

(1)

DC

+ 0.4V

DC

+ BRT (with BRT = 0 to 2V)

BLACK

+ CONT = k x Video IN (CONT = 4.4VPPmax. for VIN= 0.7VPP)

BRT

+ OSD (OSD max. = 4.9VPP, OSD min = 0VPP)

BRT

OUT2

,V

OUT3

OSD

CONT
BRT

0.4V fixed

6/19

Figure 4. Waveforms (Drive adjustment)

HSYNC

BPCP

BLK

Video IN

BFLK

OSD IN

V

OUT1,VOUT2,VOUT3

V

OSD

V

BRT

V

CONT

TDA9210

V

BLACK

V

DC

Note :

1.Drive adjustment modifies the following voltages : V
Drive adjustment doesn’t modify the following voltages : V

Two examples of drive
adjustment

4.10 - Bandwidth Adjustment

A new feature: Bandwidth adjustment, has been
implemented on the TDA9210.

This function has several advantages:
– Depending on the external capacitive load and

on thepeak-to-peak output voltage, the band­width can be adjusted to avoid any slew-rate
phenomenon.

– The preamp bandwidth canbe adjusted in order

to reduce electromagnetic radiation, since it is
possible to slow down the signal rise/fall time at
the CRT driver input without too much affecting
the rise/fall time at the CRT driver output.

– It is possible to optimize the ratio ofthe frequen-

cy response versus the CRT driver power con­sumption forany kind of chassis, as the preamp
bandwidth adjustment also allows the adjust­ment of the rise/fall time on the cathode (through
the CRT driver).

(1)

CONT,VBRT

DC

and V

and V

OSD

BLACK

.

.

– In still picture mode, whena high Video swing

voltage is of greater interest than rise/fall time,
bandwidth adjustmentis used to avoid any slew­rate phenomenonatthe CRTdriveroutputand to
meet electromagnetic radiation requirements.

4.11 - CRT Cathode Coupling (Figure 5)
The TDA9210 is designed to be used in DC cou-

pling mode, enabling to build a powerful video sys­tem on a small PCBBoard andgivingasubstantial
cost saving compared with any other solution
available on the market.

The preamplifier outputs controldirectly thecut-off
levels.

The output DC level (VDC) is adjusted independ­ently for each channel from 0.5 V to 2.5 V via reg­isters 10, 11 and 12.

In DC coupling mode, bit 2 must be set to 1 and
bit3 to 0 in Register 9.

7/19

TDA9210

Figure 5. DC Coupling

TDA 9210

OUTPUT 1,2,3 DC LEVEL

0.5V to 2.5V (8bits)

4.12 - Stand-by Mode

The TDA9210 has a stand-by mode. As soon as
the VCCpower (Pin 17) gets lower than 3V (typ.),
the device is set in stand-by mode whatever the
voltage on analog V
blocks are internally switched-off while the logic

(Pin 7) is. The analog

CCA

parts (I2C bus, power-on reset) are still supplied.
In stand-by mode, the power consumption is be-

low 20 mW.

4.13 - Serial Interface

The 2-wire serial interface is an I2C interface. The
slave address of TDA9210 is DC hex.

A6 A5 A4 A3 A2 A1 A0 W

11011100

The host MCU can write into the TDA9210 regis­ters. Read mode is not available.

Pins 14-16-18

CRT
Driver

CRT

In order to write data into the TDA9210, after the
“start” message, the MCU must send the following
data (see Figure 6):

– the I2C addressslave bytewith alow level for the

R/W bit,

– the byte to the internal register address where

the MCU wants to write data,
– the data.
All bytes are sent with MSB bit first. The transfer of

written data is ended with a “stop” message.
When transmitting several data, the register ad-

dresses and data can be written with no need to
repeat the startand slave addresses.

4.14 - Power-on Reset

A power-on reset function is implemented on the
TDA9210 so that the I2C registers have a deter­mined status after power-on. The Power-on reset
threshold for a rising supply on V

3.8 V (typ.) and 3.2V when the VCCdecreases.

CCA

(Pin 7) is

Figure 6. I2C Write Operation

SCL

SDA

2

C Slave AddressStart

8/19

W

A7 A6 A5 A4 A3 A2 A1 A0

Register Address ACKACKI

D7 D6 D5 D4 D3 D2 D1 D0

Data Byte ACK Stop

TDA9210

5 - ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Pin Value Units

Max.

V

CCA

Max.

V

CCP

Max. Voltage at any Input Pins (except Video inputs) and Input/Output Pins - 5.5 V

V

in

Max. Voltage at Video Inputs 1, 3, 5 1.4 V

V

I

T

stg

T

oper

Supply Voltage on Analog V
Supply Voltage on Power V

CC

CC

20

7

5.5

8.8VV

Storage Temperature - - °C
Operating Junction Temperature - +150 °C

6 - THERMAL DATA

Symbol Parameter Value Units

R

th(j-a)

T

j

Max. Junction-ambient Thermal Resistance 69 °C/W
Typ. Junction Temperature at T

=25°C80°C

amb

7 - DC ELECTRICAL CHARACTERISTICS

T

=25°C, V

amb

Symbol Parameter Test Conditions Min. Typ. Max. Units

V

CCA

V

CCP

I

CCA

I

CCP

V

I

Vo Output Voltage Range 0.5
V

IL

V

I

H

I

I

N

R

HS

CCA

=5V,V

= 8V, unless otherwise specified.

CCP

Analog Supply Voltage Pin 7 4.5 5 5.5 V
Power Supply Voltage Pin 17 4.5 8 8.8 V
Analog Supply Current V
Power Supply Current V

=5V 70 mA

CCA

=8V 55 mA

CCP

Video Input Voltage Amplitude 0.7 1 V

V

CCP

-0.5V

Low Level Input Voltage
High Level Input Voltage

OSD, FBLK, BLK, HSYNC

0.8 V

2.4

Input Current OSD, FBLK, BLK -1 1 µA
Input Resistor HSYNC 40 kΩ

V

V

9/19

TDA9210

8 - AC ELECTRICAL CHARACTERISTICS

T

=25°C, V

amb

RS= 100Ω, serial between output pin and C

Symbol Parameter Test Conditions Min. Typ. Max. Units

VIDEO INPUTS (PINS 1, 3, 5)

V

VIDEO OUTPUT SIGNAL (PINS 14, 16, 18) - GENERAL

GAM Maximum Gain Max Contrast and Drive

VOM Maximum Video Output Voltage

VON

CAR Contrast Attenuation Range

DAR Drive Attenuation Range From Max. Drive (DRV = 254 dec)

GM Gain Matching Contrast and Drive at POR
t

R,tF

BW Large Signal Bandwidth V
BW Bandwidth Adjustment Range V

CT Crosstalk between Video Outputs V

VIDEO OUTPUT SIGNAL — BRIGHTNESS

BRTmax Maximum Brightness Level Max. Brightness (BRT = 255 dec)

BRTmin Minimum Brightness Level Min. Brightness (BRT = 0 dec)

VIP Insertion Pulse 0.4 V
BRTM Brightness Matching Brightness and Drive at POR

VIDEO OUTPUT SIGNAL — OSD

OSDmax
OSDmin

VIDEO OUTPUT SIGNAL — DC LEVEL (DC COUPLING MODE)

DCLmax
DCLmin

DCLstep Output DC Level Step 10 mV
DCLTD Output DC Level Drift Tj variation=100°C 0.5 %

Note 1 : Assuming that VOMremains within the range of Vo (between 0.5V and V
Note 2 : t

Video Input Voltage Amplitude Max. Contrast and Drive 0.7 1 V

I

(Note 1)
Nominal Video Output Voltage

Rise Time, Fall Time (Note 2)

Maximum OSD Output Level
Minimum OSD Output Level

Maximum Output DC Level
Minimum Output DC Level

are calculated values, assuming an ideal input rise/fall time of 0ns (tR=

R,tF

CCA

=5V,V

=8V,Vi= 0.7 VPP,C

CCP

= 5pF

LOAD

, unless otherwise specified.

LOAD

(CRT = DRV = 254 dec)
Max Contrast and Drive

(CRT = DRV = 254 dec)
Contrast and Drive at POR

(CRT = DRV = 180 dec)
From max.Contrast (CRT=254 dec)
to min. Contrast (CRT = 1 dec)

to min Drive (DRV = 1 dec)

=2VPP(BW = 15 dec)

V

OUT

=2VPP(BW = 0 dec)

V

OUT

=2V

OUT
OUT

Minimum bandwidth (BW = 0 dec)

=2V

PP
PP

Maximum bandwidth (BW =15 dec)

OUT

=2V

PP

@ f = 10 MHz
@ f = 50 MHz

and Max. Drive (DRV = 254 dec)

and Max. Drive (DRV = 254 dec)

Max. Drive (DRV = 254 dec)

Max. OSD (OSD = 15 dec)
Min. OSD (OSD = 0 dec)

Max. Cut-off (Cut-off = 255 dec)
Min. Cut-off (Cut-off = 40 dec)

CCP

- 0.5V)

t

ROUT

16 dB

4.4 V

2.2 V

48 dB

48 dB

±0.1 dB

2.7

4.3

130 MHz

80

130

60
35

2V

0V

±10 mV

4.9
0

2.5

0.4

2

+t

RIN

2

=

,tF

t

FOUT

2

ns
ns

MHz
MHz

dB
dB

V
V

V
V

+t

FIN

2

10/19

TDA9210

AC ELECTRICAL CHARACTERISTICS

T

=25°C, V

amb

CCA

= 5V, V

= 8V, Vi= 0.7 VPP,C

CCP

= 5 pF, unless otherwise specified

LOAD

Symbol Parameter Test Conditions Min. Typ. Max. Units

ABL (PIN 2)

GABL

min

GABLmax
V

ABL

IABLhigh
IABLlow

ABL Mini Attenuation
ABL Maxi Attenuation

V

V

ABL

ABL

3.2 V

≥

=1V

ABL Threshold Voltage For output attenuation 3 V

V
V

ABL
ABL

= 3.2V
=1V

High ABL Input Current
Low ABL Input Current

0

15

0

-2

9-I2C ELECTRICAL CHARACTERISTICS

T

=25°C, V

amb

Symbol Parameter Test Conditions Min. Typ. Max. Units

V

IL

V

IH

I

IN

f

SCL(Max.)

V

OL

Low Level Input Voltage On Pins SDA, SCL 1.5 V
High Level Input Voltage 3 V
Input Current (Pins SDA, SCL) 0.4 V < VIN< 4.5 V -10 +10 µA
SCL Maximum Clock Frequency 200 0.25 kHz

Low Level Output Voltage

= 5V, unless otherwise specified

CCA

SDA Pin
when ACK Sink Current = 6mA

0.6 V

dB
dB

µA
µA

10 - I2C INTERFACE TIMING REQUIREMENTS

(see Figure 11)

Symbol Parameter Min. Typ. Max. Units

t

BUF

t

HDS

t

SUP

t

LOW

t

HIGH

t

HDAT

t

SUDAT

t

R,tF

Figure 7. I2C Timing Diagram

Time the bus must be free between two accesses 1300 ns
Hold Time for Start Condition 600 ns
Set-up Time for Stop Condition 600 ns
The Low Period of Clock 1300 ns
The High Period ofClock 600 ns
Hold Time Data 300 ns
Set-up Time Data 250 ns
Rise and Fall Time of both SDA and SCL 20 300 ns

t

BUF

t

HDAT

SDA

t

HDS

t

SUDAT

t

SUP

SCL

t

HIGH

t

LOW

11/19

TDA9210

11 - I2C REGISTER DESCRIPTION

Register Sub-addressed - I2C Table 1

Sub-address

Hex Dec Hex Dec Hex Dec

01 01 Contrast (CRT) 8-bit DAC B4 180 FE 254
02 02 Brightness (BRT) 8-bit DAC B4 180 FF 255
03 03 Drive 1 (DRV) 8-bit DAC B4 180 FE 254
04 04 Drive 2 (DRV) 8-bit DAC B4 180 FE 254
05 05 Drive 3 (DRV) 8-bit DAC B4 180 FE 254
06 06 Not Used - - - ­07 07 OSD Contrast (OSD) 4-bit DAC 09 09 0F 15
08 08 BPCP & OCL Refer to the I
09 09 Miscellaneous Refer to the I
0A 10 Cut Off Out 1 DC Level (Cut-off) 8-bit DAC B4 180 FF 255
0B 11 Cut Off Out 2 DC Level (Cut-off) 8-bit DAC B4 180 FF 255
0C 12 Cut Off Out 3 DC Level (Cut-off) 8-bit DAC B4 180 FF 255
0D 13 Bandwidth Adjustment (BW) 4-bit DAC 07 07 0F 15

For Contrast & Drive adjustment, code 00 (dec) and 255 (dec) are not allowed.
For Output DC Level, code 00(dec), 01(dec), 02(dec) are not allowed (Register 06).
For Cut Off Output DC Level, output voltage is linear between code 10 and code 235 (Registers 0A, 0B, 0C).

Register Names

2

C table 2 04 04

2

C table 3 1C 28

POR Value

Max.

Value

BPCP & OCL Register (R8)- I2C Table 2 (see also Figure 8)

b7 b6 b5 b4 b3 b2 b1 b0 Function POR Value

0 0 Internal BPCP triggered by HSYNC x
0 1 Internal BPCP triggered by BLK
0 0 Internal BPCP synchronized by the trailing edge x
0 1 Internal BPCP synchronized by the leading edge
0 0 0 Internal BPCP Width = 0.33µs
0 0 1 Internal BPCP Width = 0.66µsx
0 1 0 Internal BPCP Width = 1 µs
0 1 1 Internal BPCP Width = 1.33µs

1 Internal BPCP = BPCP input (Pin 23)
0 Normal Operation x
1 Reserved (Force BPCP to 1 in test)

0 Normal Operation x

1 Reserved (Force OCL to 1 in test)
0 Internal OCL pulse triggered by BLK (pin 24) x
1 Internal OCL pulse = Internal BPCP

12/19

TDA9210

Miscellaneous Register (R9) - I2C Table 3

b7 b6 b5 b4 b3 b2 b1 b0 Function POR Value

0 Positive Blanking Polarity x

1 Negative Blanking Polarity
0 Soft Blanking = OFF x
1 Soft Blanking = ON

x 0 1 DC Coupling Mode (Note 3)
0 0 Light Grey on OSD Outputs = OFF x
0 1 Light Grey on OSD Outputs = ON
0 0 Dark Grey on OSD Outputs = OFF x
1 0 Dark Grey on OSD Outputs = ON

0 SOG Clipping = OFF x
1 SOG Clipping = ON

Note 3 : After Power ON, the DC coupling mode must be programmed in Register 9 by setting bit2=1 and bit3=0.

Bandwidth Adjustment (R13) - I2C Table 4

b7 b6 b5 b4 b3 b2 b1 b0 Function POR Value

1111130MHz
0111100MHz x

000080MHz
0 0 Normal Operation x
0 1 BW DAC output connected to BLK input (for test)

10

BW DAC complementary output connected to BLK input
(for test)

Figure 8. BPCP and OCL Generation

Source

Selection

R8b0

HS/BPCP

(External)

23

BLK

(External)

24

Automatic

Polarity

Polarity

Selection

BLK Polarity

Selection

R9b0

HS edge

Selection

R8b1

Edge

Selection

Width

Selection

R8b2b3

Pulse

Generation

Pulse

Generation

BPCP Source

Selection

R8b4

BPCP

(Internal)

OCL

(Internal)

OCL Source

Selection

R8b7

13/19

TDA9210

12 - INTERNAL SCHEMATICS

Figure 9.

(Pins1-3-5)

Figure 10.

ABL

IN

Figure 12.

V

CC5

30k

V

CCA

7

(8V)

LOGIC

HIGH

PART

IMPEDANCE

GNDA

GNDA

6

Figure 13.

V

V

CCA

OSD-FBLK-HS-BLK

1k

2

Pins8-9-10
11-19-20

GNDA

CCA

GNDA

GNDL

Figure 11.

GNDL

Figure 14.

V

CCA

HSYNC

4

GNDA

19

GNDA

GNDL

14/19

2

Figure 15.

TDA9210

SCL

12

GNDA

SCA 13

GNDA

Figure 16.

GNDP

15

(8V)

V

30kΩ

4pF

GNDL

30kΩ

4pF

GNDL

CCP

GNDA

Figure 17.

Pins 14-16-18

V

CCP

OUT

17

(20V)

GNDA GNDP

15/19

TDA9210

Figure 18. TDA9210 - TDA9535/9536 Demonstration Board: Silk Screen and Trace (scale 1:1)

16/19

Figure 19. TDA9210 - TDA9535/9536 Demonstration Board Schematic

F2(2)

R23 150R

L3

R22

Heater

0.33uH

120R

R28

TDA9535/36

F1(2)

G2

J8

C19

8

R

GND_CRT

110V

J7

7

G2

C21

10nF/2KV

G1 G

GND

100nF/ 250V

56

R27 150R

1

C14

10nF/400V

9

H2

101112

H1BGND

J5

10R

E

0.33uH

120R

GND3

R15 150R

110V

D7(2)

FDH400

L2

R31

S_R

R14

47uF

C8

12V

C7(1)

100nF

VCC

IN2

IN3

47pF

C24

R33

24R

0.33uH

120R

GND2

D9(2)

FDH400

110V

110V

R32

S_R

4.7uF/150V

C18

R26(2) 39R

C10(1)

100nF/ 250V

1

2345678910

VDD

47pF

24R

OUT1

GND1

IN1

C25

47pF

R24

24R

OUT2

R7 150R

D2(2)

FDH400

110V

L1

R30

S_R

R6

transientresponse optimisation

D

11

OUT3

U2

C23

R29

TDA9210

F4(2)

11Wednesday,February16,2000

E

4.7nF/1kV

C20

Version1.4

CRT3with TDA9210+ TDA9535/36

Custom

Title

Size DocumentNumber Rev

Date: Sheet of

G1

D

HsOut

R20 100R

R1 100R

C1(1)

8V

100pF

VsOut

R18 100R

R11 2R7

U1

R4

2R7

5V

5V

D1

J1

4 4

C

B

A

12

20

1

R2 15R

C3 100nF

1N4148

GRN

15R/33R

R13 15R/33R

R9

17

18

19

HS

BLK

OUT1

VCCP

IN1

ABL

IN2

GNDL

2

3

4

R8 15R

C9(1) 100nF

C4 100nF

D4

1N4148

5V

D5

1N4148

5V

D3

1N4148

D6

R5

75R

R3

75R

BLU

RED

R17 15R/33R

5V

C5(1)100nF

15

16

OUT2

GNDP

IN3

GNDA

5

6

R12 15R

C22(1)100nF

5V

C6 100nF

D8

1N4148

1N4148

R10

75R

1234567891011

Video

R21 2K7

R19 2K7

12

13

14

SCA

OUT3

VCCA

OSD1

7

8

9

R16 2R7

3 3

SCL

OSD2

10 11

OSD3 FBLK

5V

C13

100pF

TDA9210

110V

J10

I2C

123

4

C12

100pF

1: All capacitorsfollowed by (1) are decouplingcapacitors

which must be connectedas close as possible to the device

2: The purpose of all components followedby (2) is to ensure a

good protectionagainst overvoltage(arcing protection)

Notes:

VsOut

G1

Heater

C15

C17

12V

47uF

47uF

C16

47uF

5V

8V

12345

J16

Power

12345

J17

2 2

HsOut

6

Supply

1 1

C

B

A

17/19

TDA9210

13 - PACKAGE MECHANICAL DATA

20 Pins — Plastic Dip

Dimensions

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000
E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053

18/19

Min. Typ. Max. Min. Typ. Max.

Millimeters Inches

TDA9210

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights ofthird parties which may result from its use. No license is granted by implication or otherwise under any
patent orpatent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change
without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.

The ST logois a trademark of STMicroelectronics.

 2000 STMicroelectronics - All Rights Reserved

Purchase of I

Rights to use these components in a I

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco

2

C Components of STMicroelectronics, conveys a license under the Philips I2C Patent.

Standard Specifications as defined by Philips.

STMicroelectronics GROUP OF COMPANIES

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

2

C system, is granted provided that the system conforms to the I2C

http://www.st.com

19/19

3