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I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
.
70MHz TYPICAL BANDWIDTH AT 4VPPOUTPUTWITH12pFCAPACITIVELOAD
.
5.5ns TYPICAL RISE/FALL TIME AT 4V
OUTPUTWITH 12pF CAPACITIVELOAD
.
POWERFULLOUTPUTDRIVE CAPABILITY
.
BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSEWIDTH AREI
.
INTERNAL BACK-PORCH CLAMPING
PULSEGENERATOR
.
OSD WHITEBALANCETRACKING
.
INTERNALOSD SWITCHES
.
BLANKINGAND FAST-BLANKINGINPUTS
.
VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
.
SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
.
ABLCONTROL
2
C BUS CONTROLLED
TDA9203A
PP
SHRINK 24
(Plastic Package)
ORDER CODE : TDA9203A
DESCRIPTION
The TDA9203A is a digitaly controlled wideband
video preamplifier intended for use in mid range
color monitor. All controls and adjustments are
digitaly performed thanks to I
trast, brightness and DC output level of RGB signals are common to the 3 channels and drive
adjustmentisseparatefor eachchannel.ThreeI
gain controlled OSD inputs can be switched with
RGBsignalsusingfastblankingcommand.Clampingof RGBsignalsis performedthanksto aflexible
integrated system. The white balance adjustment
is effectiveon brightness,video and OSD signals.
The TDA9203Aworks for application using AC or
DC coupledCRT driver.
The ABL input provides a 12dB Max. attenuation
on the current contrast value according average
beamlimitation voltage.
Because of its features and due to component
saving the TDA9203Aleads to a very performant
and cost effectiveapplication.
2
C serial bus. Con-
2
C
PIN CONNECTIONS
IN1
OSD1
AV
IN2
OSD2
AGND
IN3
OSD3
ABL
LGND
SDA
SCL
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
HSYNC
PV
CC1
OUT1
PGND1
PV
CC2
OUT2
PGND2
PV
CC3
OUT3
PGND3
BLK
FBLK
9203A-01.EPS
June 1998
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TDA9203A
PIN DESCRIPTION
Name Pin Type Function
IN1 1 I 1
OSD1 2 I 1
AV
3 I 12V Analog V
DD
IN2 4 I 2ndChannel Main Picture Input
OSD2 5 I 2
AGND 6 I/O Analog Ground
IN3 7 I 3
OSD3 8 I 3
ABL 9 I ABL Input
LGND 10 I/O Logic Ground
SDA 11 I/O Serial Data Line
SCL 12 I Serial Clock Line
BLOCKDIAGRAM
st
Channel Main Picture Input
st
Channel OSD Input
DD
nd
Channel OSD Input
rd
Channel Main Picture Input
rd
Channel OSD Input
Name Pin Type Function
FBLK 13 I Fast Blanking Input
BLK 14 I Blanking Input
rd
PGND3 15 I/O 3
OUT3 16 O 3
PV
17 I 3rdChannel Power V
CC3
Channel Power Ground
rd
Channel Output
CC
PGND2 18 I/O 2ndChannel Power Ground
nd
OUT2 19 O 2
PV
20 I 2ndChannel Power V
CC2
Channel Output
CC
PGND1 21 I/O 1stChannel Power Ground
st
OUT1 22 O 1
PV
23 I 1stChannel Power V
CC1
Channel Output
CC
HSYNC 24 I Horizontal Synch Input
9203A-01.TBL
AV
IN1
AGND
IN2
IN3
ABL
LGND
3
DD
1
6
4
7
9
10
TDA9203A
V
REF
BLUECHANNEL
GREEN CHANNEL
BPCP
24
LATCHES
BUS
DECODER
11 12
CLAMP
2
C
I
SCLSDAHSYNC
FBLKBLK
CONTRAST
D/A
OSD
CONT
1314
BRIGHTNESS
2
OSD1 OSD2 OSD3
5
DRIVE
8 bits
8
2
C
I
BPCP
OUTPUT
STAGE
V
REF
PV
CC1
23
OUTPUT
DC LEVEL
ADJUST
22
21
20
19
18
16
17
15
OUT1
PGND1
PV
CC2
OUT2
PGND2
OUT3
PV
CC3
PGND3
9203A-02.EPS
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FUNCTIONAL DESCRIPTION
InputStage
The R, G and B signals must be fed to the three
inputsthroughcoupling capacitors(100nF).
Themaximuminput peak-to-peakvideo amplitude
is 1V.
Theinput stage includesa clampingfunction.This
clamp is using the input serial capacitor as ”memory capacitor”and is gatedby an internally generated”Back-Porch-Clamping-Pulse(BPCP)”.
Thesynchronizationedge of the BPCPis selected
accordingbit 0 of registerR8.
WhenB0R8 is set to 1, the BPCPis synchronized
ontheleadingedgeoftheblankingpulseBLKinputs
onPin14(seeFigure1).B7R8allowstousepositive
or negativeblankingsignal on Pin 14. Atpower on
resetTDA9203Ause onlypositive blanking.
Figure1
BLK
HSYNC
BPCP
2
Internal pulse width is controlled by I
C
WhenB0R8is clearto0, theBPCPissynchronized
onthesecondedgeof thehorizontalpulseHSYNC
inputs on Pin 24. An automatic function allows to
usepositive or negativehorizontalpulseon Pin24
(seeFigure 2).
Figure2
HSYNC
BPCP
2
Internal pulse width is controlled by I
In both case BPCP width is adjustable by I
C
2
C, B1
and B2 of registerR8 (see R8 TableP8).
Contrast Adjustment (8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers throughthe I
2
C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
ABLControl
The TDA9203AI
2
C preamplifier provides an ABL
input (automatic beam limitation) to attenuate
TDA9203A
R,G,Bvideo signals according to beam intensity.
The operating range is 2.5V typicaly,from 5.3V to
2.8V.A typical 12dBMax. attenuationis appliedto
the signal whatever the current gain is. Refer to
Figure 3 forABL input attenuationrange.
In case of software control,the ABLinput must be
pulled to AV
consumption(see Figure 11).
ABL input voltage must not exceeed AV
resistoris 10kΩ and equivalentschematic givenin
Figure 11.
Figure 3
Attenuation (dB)
2
0
-2
-4
-6
-8
-10
-12
9203A-03.EPS
-14
123456789
BrightnessAdjustment (8 bits)
As for the contrast adjustment, the brightness is
controlledby I
The brightnessfunction consiststo add the same
DC offsetto the threeR,G, B signalsafter contrast
amplification. This DC-Offset is present only outside the blankingpulse (see Figure 4).
The DC output level during the blanking pulse, is
forced to”INFRA-BLACK”level (V
DriveAdjustment (3x 8 bits)
9203A-04.EPS
Inordertoadjustthewhitebalance, theTDA9203A
offersthepossibilitytoadjustseparatelythe overall
gain of each complete video channel. The gain of
each channel is controlledby I
Theverylargedriveadjustmentrange(48dB)allows
differentstandardor customcolortemperature.
It can also be usedto adjustthe outputvoltagesat
the optimum amplitude to drive the C.R.T drivers,
keepingthewholecontrastcontrolforend-useronly.
The drive adjustment is located after the CONTRAST,BRIGHTNESSand OSDswitchblocks,so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portionof the signal.
through a resistor to limit power
DD
2
C.
).
DC
2
C (8bits each).
DD
. Input
VIN(V)
9203A-0X .EPS
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TDA9203A
FUNCTIONAL DESCRIPTION(continued)
OSD Inputs
TheTDA9203Aincludes allthe circuitrynecessary
tomixOSDsignals intotheRGBmain-picture.Four
pins arededicated to this function as follow.
Three TTL RGB On Screen Displayinputs (Pin 2,
5 and 8). These three inputs are connectedto the
three outputs of the corresponding ON-SCREENDISPLAYprocessor(ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAYprocessor.
When a high level is present on FBLK, the IC will
acts as follow:
- The three main picture RGB input signals are
internally switched to the internal input clamp
referencevoltage.
- The three output signals are set to voltages correspondingto the state(0 or 1)on thethree OSD
inputs (see Figure4).
Example:
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to V
V
BRT,VOSD
where: V
BRTis the brightnessDC level I
,
BRT=VBLACK
+ BRT, V
OSD=VBRT
2
C adjustable.
OSD is the On-Screen Display signal value I
adjustablefrom 0V to 5.5V
bystep of 0.36V.
PP
Semi-transparent function is controlled thanks to
Bit6 of R8register(seeTable1).
When semi-transparent mode is activated, video
signalis dividedby 2 (CONT).
Table 1
FBLK OSD1 OSD2 OSD3 B6R8
0 x x x 0 Video
1 x x x 0 OSD (1)
0 x x x 1 Video
1 0 x x 1 OSD
1x1x1 OSD
1xx01 OSD
1 1 0 1 1 Semi-trans-
Notes : 1. All OSD colors are displayed.
2. One OSD color is displayed as semi-transparent video
without effect on brightness and DC level adjustment.
Signal (OUTn)
parent (2)
+ OSD
Output
OSD
2
C
Output Stage
Thethreeoutputstagesincorporatethreefunctions
which are :
- The blanking stage : When high level is applied
to the BLK input (Pin 14), the three outputs are
switchedto a voltagewhich is 400mV lower than
the BLACK level. The black level is the output
voltagewithminimumbrightness wheninput signal video amplitude is equalto ”0”.
- The output stage itself : It is a large bandwidth
output amplifier whichallow to deliverup to 5V
on the threeoutputs(for 0.7V videosignal onthe
inputs).
- The output CLAMP : The IC also incorporates
three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I
2
C with4 bits. Practicaly, the DC output
level allowto adjustthe BLK level (V
underV
)from0.9Vto 2.9Vwith12 x165mV.
BLACK
Theoverallwaveforms ofthe outputsignalaccording to the different adjustment are shown in Fig-
,
ures 4 and 5.
Serial Interface
2
The 2-wiresserial interface is an I
C interface.
The slave address of the TDA9203A is DC (in
hexadecimal).
A6 A5 A4 A3 A2 A1 A0 W
11011100
Data Transfer
The host MCU can write data into the TDA9203A
registers.Read mode is not available.
To write data into the TDA9203A,after a start,the
MCU must send (see Figure6) :
2
- The I
C addressslavebytewitha lowlevel forthe
R/W bit.
- The byte of the internal register address where
the MCU wants to write data(s).
- The data.
All bytes are sent MSB bit first and the write data
transteris closedby a stop.
=400mV
DC
PP
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