Datasheet TDA9113 Datasheet (SGS Thomson Microelectronics)

TDA9113

LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR

FOR MULTISYNC MONITOR

FEATURES
General

■ ADVANCED I

2

C BUS CONTROLLED
DEFLECTION PROCESSOR DEDICATED
FOR HIGH-END CRT MONITORS

■ SINGLE SUPPLY VOLTAGE 12V

■ VERY LOW JITTER

■ DC/DC CONVERTER CONTROLLER

■ ADVANCED EW DRIVE

■ ADVANCED ASYMMETRY CORRECTIONS

■ AUTOMATIC MULTISTANDARD

SYNCHRONIZATION

■ 2 DYNAMIC CORRECTION WAVEFORM

OUTPUTS

■ X-RAY PROTECTION AND SOFT-START &

STOP ON HORIZONTAL AND DC/DC DRIVE
OUTPUTS

2

■ I

C BUS STATUS REGISTER

Horizontal section

■ 150 kHz maximum frequency

■ Corrections of geometric asymmetry:

Pin cushion asymmetry, Parallelogram

■ Tracking of asymmetrycorrections with vertical

size and position

■ Fully integrated horizontal moiré cancellation

Vertical section

■ 200 Hz maximum frequency

■ Vertical ramp for DC-coupled output stage with

adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position

■ Vertical moiré cancellation through vertical

ramp waveform

■ Compensation of vertical breathing with EHT

variation

EW section

■ Symmetricalgeometrycorrections:Pin cushion,

Keystone, Top/Bottom corners separately

■ Horizontal size adjustment

■ Tracking of EW waveform with Vertical sizeand

position and adaptation to frequency

■ Compensation of horizontal breathing through

EW waveform

Dynamic correction section

■ Generates waveforms for dynamic corrections

like focus, brightness uniformity, ...

■ 1 output with vertical dynamic correction

waveform

■ 1 output with horizontal dynamic correction

waveform

■ Fixed on screen by means of tracking system

DC/DC controller section

■ Step-up and step-down conversion modes

■ External sawtooth configuration

■ Bus-controlled output voltage

■ Synchronization on hor. frequency with phase

selection

■ Selectable polarity of drive signal

DESCRIPTION

The TDA9113 is a monolithic integrated circuit as­sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.

The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9113 suitable for very high performance mon­itors, using few external components.

Combined with other ST components dedicated
for CRTmonitors (microcontroller, video preampli­fier, video amplifier, OSD controller) the TDA9113
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of ex­ternal components.

SHRINK 32 (Plastic Package)

ORDER CODE: TDA9113

Version 4.3

October 2001 1/50

1

TABLE OF CONTENTS

1 -PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 -BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 -PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 -QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 -ABSOLUTE MAXIMUM RATINGS . . . . . . . ........................................ 8

6 -ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . ................. 9

6.1 -THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2 -SUPPLY AND REFERENCE VOLTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.3 -SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.4 -HORIZONTAL SECTION . . ................................................ 10

6.5 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.6 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.7 -DYNAMIC CORRECTIONOUTPUTS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.8 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . ................17

6.9 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . ................................... 18

7 -TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8-I2C BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 -OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1 -SUPPLY AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1.1 -Power supply and voltage references .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1.2 -I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2 -SYNC. PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.1 -Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.2 -Sync. presence detection flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2.3 -MCU controlled sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2.4 -Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 -HORIZONTAL SECTION . . ................................................ 27

9.3.1 -General . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3.2 -PLL1 . . . . . . . . . . . . . ................................................ 27

9.3.3 -Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.3.4 -PLL2 . . . . . . . . . . . . . ................................................ 29

9.3.5 -Dynamic PLL2 phase control . . . . . . . . . . ................................ 29

9.3.6 -Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................30

9.3.7 -Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . ................30

9.3.8 -Horizontal moiré cancellation . . . ....................................... 30

9.4 -VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.4.1 -General . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.4.2 -Vertical moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.5 -EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.6 -DYNAMIC CORRECTIONOUTPUTS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.6.1 -Horizontal dynamic correction output HDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.6.2 -Vertical dynamic correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.7 -DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . ................36

9.8 -MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . ................................... 38

9.8.1 -Safety functions . . . . ................................................ 38

9.8.2 -Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.8.3 -X-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.8.4 -Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3

2/50

10 -INTERNAL SCHEMATICS . . . . . . . . . . . . . ....................................... 42

11 -PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12 -GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/50

TDA9113

1 - PIN CONFIGURATION

H/HVSyn

VSyn

HLckVBk

HOscF

HPLL2C

CO

HGND

RO

HPLL1F

HPosF

HDyCor

HFly

RefOut
BComp
BRegIn

BISense

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

VDyCor
SDA
SCL
Vcc
BOut
GND
HOut
XRay
EWOut
VOut
VCap
VGND
VAGCCap
VOscF
VEHTIn
HEHTIn

4/50

2 - BLOCK DIAGRAM

H/HVSyn

HLckVBk

SDA
SCL

Vcc

RefOut

GND

HGND

7

HPosF

10

HPLL1F

9

R0

HOscF

C0

4

6

8

HFly

12

H-sync

1

detection

Polarity

handling

Phase/frequency

comparator

Horizontal position

Lock detection

3

V-blank

H-lock

31

30

I2C Bus

interface

2

C Bus registers

I

: Functions controlled via I2C Bus

Horizontal

VCO

PLL1

H-moiré controller

H-moiré amplitude

Phase comparator
Phase shifter
H duty controller

Pin cushion asymm.
Parallelogram
Hor. duty cycle

HPLL2C

5

PLL2

H-drive

buffer

Safety

processor

B+

DC/DC
converter
controller

B+ ref.

26

25

28

16

15

14

HOut

XRay

BOut
BISense
BRegIn
BComp

H-dynamic

29

13

27

Supply

supervision

Reference

generation

Internal

ref.

V-sync detection

Input selection

Polarity handling

V-sync

extraction

& detection

Vertical oscillator

with AGC

S-correction
C-correction

V-dynamic

correction

(focus, bright.)

VDyCor amplitude

Geometry

tracking

V-ramp control
Tracking EHT

Vertical size
Vertical position
Vertical moiré

correction

(focus,brightness)

HDyCor amplitude
HDyCor symmetry

EW generator

H size

Pin cushion
Keystone
Top corners
Bottom corners

11

24

HDyCor

EWOut

5/50

2

VSyn

21

VGND

19

VOscF

20 22

VAGCCap

VCap

32

VDyCor

23

VOut

18

VEHTIn

17

HEHTIn

TDA9113

TDA9113

TDA9113

3 - PIN FUNCTION REFERENCE

Pin Name Function

1 H/HVSyn TTL compatible Horizontal /Horizontal and Vertical Sync. input
2 VSyn TTL compatible Vertical Sync. input
3 HLckVBk Horizontal PLL1 Lock detection and Vertical early Blanking composite output
4 HOscF High Horizontal Oscillator sawtooth threshold level Filter input
5 HPLL2C Horizontal PLL2 loop Capacitive filter input
6 CO Horizontal Oscillator Capacitor input
7 HGND Horizontal section GrouND
8 RO Horizontal Oscillator Resistor input
9 HPLL1F Horizontal PLL1 loop Filter input
10 HPosF Horizontal Position Filter and soft-start time constant capacitor input
11 HDyCor Horizontal Dynamic Correction output
12 HFly Horizontal Flyback input
13 RefOut Reference voltage Output
14 BComp B+ DC/DC error amplifier (Comparator) output
15 BRegIn Regulation feedback Input of the B+ DC/DC converter controller
16 BISense B+ DC/DC converter current (I) Sense input
17 HEHTIn Input for compensation of Horizontal amplitude versus EHT variation
18 VEHTIn Input for compensation of Vertical amplitude versus EHT variation
19 VOscF Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND)
20 VAGCCap Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator
21 VGND Vertical section GrouND
22 VCap Vertical sawtooth generator Capacitor
23 VOut Vertical deflection drive Output for a DC-coupled output stage
24 EWOut E/WOutput
25 XRay X-Ray protection input
26 HOut Horizontal drive Output
27 GND Main GrouND
28 BOut B+ DC/DC converter controller Output
29 Vcc Supply voltage
30 SCL I
31 SDA I
32 VDyCor Vertical Dynamic Correction output

2

C bus Serial CLock Input

2

C bus Serial DAta input/output

6/50

TDA9113

4 - QUICK REFERENCE DATA

Characteristic Value Unit

General

Package SDIP 32
Supply voltage 12 V
Supply current 65 mA
Application category Mid-range
Means of control/Maximum clock frequency I
EW drive Yes
DC/DC converter controller Yes

Horizontal section

Frequency range 15 to 150 kHz
Autosync frequency ratio (can be enlarged in application) 4.28
Positive/Negative polarity of horizontal sync signal/Automatic adaptation Yes/Yes/Yes
Duty cycle range of the drive signal 30 to 65 %
Position adjustment range with respect to H period ±10 %
Soft start/Soft stop feature Yes/Yes
Hardware/Software PLL lock indication Yes/Yes
Parallelogram Yes
Pin cushion asymmetry correction (also called Side pin balance) Yes
Top/Bottom/Common corner asymmetry correction No/No/No
Tracking of asymmetry corrections with vertical size & position Yes
Horizontal moiré cancellation (int.) for Combined/Separated architecture Yes/Yes

Vertical section

Frequency range 35 to 200 Hz
Autosync frequency range (150nF at VCap and 470nF at VAGCCap) 50 to 180 Hz
Positive/Negative polarity of vertical sync signa/Automatic adaptationl Yes/Yes/Yes
S-correction/C-correction/Super-flat tubecharacteristic Yes/Yes/Yes
Vertical size/Vertical position adjustment Yes/Yes
Vertical moiré cancellation (internal) Yes
Vertical breathing compensation Yes

EW section

Pin cushion correction Yes
Keystone correction Yes
Top/Bottom/Common corner correction Yes/Yes/No
Horizontal size adjustment Yes
Tracking of EW waveform with Frequency/Vertical size & position Yes/Yes
Breathing compensation on EW waveform Yes

Dynamic correction section (dyn. focus, dyn. brightness,...)

Vertical dynamic correction output VDyCor Yes
Horizontal dynamic correction output HDyCor Yes
Composite HV dynamic correction output HVDyCor No
Tracking of horizontal waveform component with Horizontal size/EHT Yes/Yes
Tracking of vertical waveforms (component) with V. size & position Yes

DC/DC controller section

Step-up/Step-down conversion mode Yes/Yes
Internal/External sawtooth configuration No/Yes
Bus-controlled output voltage Yes
Soft start/Soft stop feature Yes/Yes
Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal Yes/Yes

2

C Bus/400 kHz

7/50

TDA9113

5 - ABSOLUTE MAXIMUM RATINGS

All voltages are given with respect to ground.
Currents flowing from the device (sourced)are signed negative. Currents flowing tothe device aresigned

positive.

Symbol Parameter

V

CC

Supply voltage (pin Vcc) -0.4 13.5 V
Pins HEHTIn, VEHTIn, XRay, HOut, BOut

Pins H/HVSyn, VSyn, SCL, SDA

V

(pin)

Pins HLckVBk, CO, RO, HPLL1F, HPosF, HDyCor, BRegIn, BI­Sense, VAGCCap, VCap, VDyCor, HOscF, VOscF
Pin HPLL2C
Pin HFly

V

T

ESD

stg

T

j

ESD susceptibility
(human body model: discharge of 100pF through 1.5kΩ) -2000 2000 V

Storage temperature -40 150 °C
Junction temperature 150 °C

Value

Min Max

V

V

5.5

V

RefO

RefO

V

RefO

CC

-0.4

-0.4

-0.4

-0.4

-0.4

Unit

V
V
V

/2

V
V

8/50

TDA9113

6 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS

Medium (middle) value of an I2C Bus control or adjustment register composed of bits D0, D1,...,Dn is the
one having Dn at ”1” and all other bits at ”0”. Minimum value is the one with all bits at 0, maximum value
is the one with all at ”1”.

Currents flowing from the device (sourced)are signed negative. Currents flowing tothe device aresigned
positive.
THis period of horizontal deflection.

6.1 - THERMAL DATA

Symbol Parameter

T

R

amb

th(j-a)

Operating ambient temperature 0 70 °C
Junction-ambience thermal resistance 65 °C/W

6.2 - SUPPLY AND REFERENCE VOLTAGES

T

=25°C

amb

Symbol Parameter Test Conditions

V

V

I

RefO

CC

I

CC

RefO

Supply voltage at Vcc pin 10.8 12 13.2 V
Supply current to Vcc pin VCC=12V 65 mA
Reference output voltage at RefOut pin VCC=12V,I
Current sourced by RefOutoutput -5 0 mA

6.3 - SYNCHRONIZATION INPUTS

Vcc = 12V, T

Symbol Parameter Test Conditions

V

LoH/HVSyn

V

HiH/HVSyn

V

LoVSyn

V

HiVSyn

R

PdSyn

t

PulseHSyn

t

PulseHSyn/TH

t

PulseVSyn

t

PulseVSyn/TV

t

extrV/TH

t

HPolDet

=25°C

amb

LOW level voltage on H/HVSyn 0 0.8 V
HIGH level voltage on H/HVSyn 2.2 5 V
LOW level voltage on VSyn 0 0.8 V
HIGH level voltage on VSyn 2.2 5 V
Internal pull-down on H/HVSyn, VSyn 100 175 250 kΩ
H sync. pulse duration on H/HVSyn pin 0.5 µs
Proportion of H sync pulse to H period Pin H/HVSyn 0.2
V sync. pulse duration Pins H/HVSyn, VSyn 0.5 750 µs
Proportion of V sync pulse to V period Pins H/HVSyn, VSyn 0.15
Proportion of sync pulse length to H peri-

od for extraction as V sync pulse

Pin H/HVSyn,
cap. on pin CO = 820pF

Polarity detection time (after change) Pin H/HVSyn 0.75 ms

Value

Min. Typ. Max.

Value

Min. Typ. Max.

= -2mA 7.65 8.0 8.2 V

RefO

Value

Min. Typ. Max.

0.21 0.3

Unit

Units

Units

9/50

TDA9113

6.4 - HORIZONTAL SECTION

Vcc = 12V, T

amb

=25°C

Symbol Parameter Test Conditions

PLL1

I

RO

C

CO

f

HO

f

HO(0)

f

HOCapt

f

∆

HO 0()

-----------------------------

f

HO 0()

∆f

/∆V

HO

V

HO

V

HOThrfr

V

HPosF

Current load on RO pin 1.5 mA
Capacitance on CO pin 390 pF
Frequency of hor. oscillator 150 kHz
Free-running frequency of hor. oscill.
Hor. PLL1 capture frequency

(4)

Temperature drift of free-running freq.

(1)

RRO=5.23kΩ,CCO=820pF 27 28.5 29.9 kHz

f

= 28.5kHz 29 122 kHz

HO(0)

(3)

T∆⋅

Average horizontal oscillator sensitivity f

HO

H. oscill. control voltage on pin HPLL1F V
Threshold on H. oscill. control voltage on

HPLL1F pin for tracking of EW with freq.

Control voltage on HPosF pin

= 28.5kHz 19.6 kHz/V

HO(0)

=8V 1.4 6.0 V

RefO

V

=8V 5.0 V

RefO

HPOS

(Sad01):
11111111b
10000000b
00000000b

V

HOThrLo

V

HOThrHi

Bottom of hor. oscillator sawtooth
Top of hor. oscillator sawtooth

(6)

(6)

PLL2

R

In(HFly)

I

InHFly

V

ThrHFly

V

S(0)

V

BotHPLL2C

V

TopHPLL2C

(min)/T

t

ph

(max)/T

t

ph

Input impedance on HFly input V

(HFly)>VThrHFly

Current into HFly input At top of H flyback pulse 5 mA
Voltage threshold on HFly input 0.6 0.7 V

H flyback lock middle point
Low clamping voltage on HPLL2C pin

High clamping voltage on HPLL2C pin
Min. advance of H-drive OFF before

H

middle of H flyback
Max. advance of H-drive OFF before

H

middle of H flyback

(7)

(8)

(6)

No PLL2 phase modula­tion

(5)
(5)

Null asym. correction 0 %

Null asym. correction 44 %

H-drive output on pin HOut

I

HOut

t

Hoff/TH

Current into HOut output Output driven LOW 30 mA

HDUTY

Duty cycle of H-drive signal

(Sad00):
x1111111b
x0000000b

Soft-start/Soft-stopvalue

Picture geometry corrections through PLL1 & PLL2

HPOS

(Sad01):
11111111b
00000000b

t

Hph/TH

H-flyback (center) static phase vs. sync
signal (via PLL1), see Figure 7

(2)

Value

Units

Min. Typ. Max.

-150 ppm/°C

2.6

3.2

3.8

2.8

3.4

4.0

3.0

3.6

4.2

1.6 V

6.4 V

300 500 700 Ω

4.0 V

1.6 V

3.9 4.05 4.2 V

27
65
85

+11

-11

V
V
V

%
%
%

%
%

10/50

TDA9113

Symbol Parameter Test Conditions

Value

Units

Min. Typ. Max.

PCAC

(Sad11h) full span

(9)

VPOS

VSIZE
VSIZE
VSIZE

PARAL

(9)

VPOS

VSIZE
VSIZE
VSIZE

VPOS

VSIZE

at medium

at minimum
at medium
at maximum

(Sad12h) fullspan

at medium

at minimum
at medium
at maximum

at max. or min.

at minimum

±1.0
±1.8
±2.8

±1.75

±2.2
±2.8

±1.75

%
%
%

%
%
%

%

t

PCAC/TH

t

ParalC/TH

Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners

Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners

Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must

always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in R

the free-running frequency is f

and CCOpositions so as to always meet this condition. The formula to calculate

RO

=0.12125/(RROCCO)

HO(0)

Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of

about 500Ω and a resistance to ground of about 20kΩ.

Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with

respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.

Note 6: Internal threshold. See Figure 10.
Note 7: Thet

(min)/THparameter is fixed by the application. For correct operation of asymmetry corrections through

ph

dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of V

TopHPLL2C

high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10.

Note 8: Thet

(max)/THparameter is fixed by the application. For correct operation of asymmetry corrections through

ph

dynamic phase modulation, this maximum must be reduced by maximum of thetotal dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of V

BotHPLL2C

low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 10 .

Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.

11/50

TDA9113

6.5 - VERTICAL SECTION

VCC= 12V,T

Symbol Parameter Test Conditions

amb

=25°C

Value

Units

Min. Typ. Max.

RefO

=8V

RefO

∆V

amp/Vamp

No load on VOscF pin
AGC loop stabilized

V sync present
No V sync

VCap
VCap
VCap

AGC loop stabilized,

AGC loop stabilized,

tVR=1/4 T

tVR=3/4 T
AGC loop stabilized,
tVR=1/2 T

CCOR

x0000000b
x1000000b
x1111111b

AGC loop stabilized

f

VOCapt

=8V

VPOS

x0000000b
x1000000b
x1111111b 3.65

VSIZE

x0000000b
x1000000b
x1111111b 3.5

V

VEHT

V

VEHT

(R=∞) ≤1% 65 MΩ

(11)

1.85 1.95 2.1 V

5

4.9

V

V
=150nF 80 µs
=150nF 100 Hz
=150nF 50 185 Hz

(15)

VR

VR

(15)

VR

(Sad0A):

(min)≤f

VO≤fVOCapt

(12)

(13)

(14)

(max)

0.5 %

-5

+5

-3
0

+3

200

ppm/Hz

%
%

%
%
%

(Sad08):

3.2

3.5

3.8

3.3 V
V
V

(Sad07):

2.25

3.0

3.75

2.5 V
V
V

-5 5 mA

>

VRefO

(min)≤V

VEHT≤VRefO

1

VRefO

0

2.5

V

%/V
%/V

AGC-controlled vertical oscillator sawtooth; V

R

L(VAGCCap)

V

VOB

V

VOT

t

VODis

f

VO(0)

f

VOCapt

∆

V

VOdev

---------------------------------

V

VOamp

V

∆

--------------------------------

V

∆

V

--------------------------------

V

∆

---------------------------------------- -

V

VOampfVO

VOS cor–

VOamp

VOC cor–

VOamp

V

VOamp

16()

∆⋅

Ext. load resistance on
VAGCCap pin

Sawtooth bottom voltage on
VCap pin

(10)

(11)

Sawtooth top voltage on VCap
pin

Sawtooth Discharge time C
Free-running frequency C
AGC loop capture frequency C

Sawtooth non-linearity

(12)

S-correction range

C-correction range

Frequency drift of sawtooth
amplitude

(17)(18)

Vertical output drive signal (on pin VOut);V

V

mid(VOut)

V

amp

V

offVOut

I

VOut

V

VEHT

V

∆

amp

------------------------------------------

∆⋅

V

ampVVEHT

Middle point on VOut sawtooth

Amplitude of VOut sawtooth
(peak-to-peak voltage)

Level on VOut pin at V-drive ”off” I2Cbit VOutEn at 0 3.8 V
Current delivered by VOut out-

put
Control input voltage range on

VEHTIn pin

Breathing compensation

Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc.,

V

for less than 1% of

amp

change.

12/50

TDA9113

Note 11: The threshold for V

influence the value of V

is generated internally and routed to VOscF pin. Any DC current on this pin will

VOB

VOB

.

Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null

CCOR

(Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin.

SCOR

Note 13: Maximum
Note 14: Null
Note 15:”t

SCOR

” istime from thebeginning of vertical ramp of V-drive signal on VOut pin. ”TVR” isduration of this ramp, see

VR

(Sad09 at x1111111b), null

(Sad09 at x0000000b).

CCOR

(Sad0A at x1000000b).

chapter TYPICAL OUTPUT WAVEFORMS and Figure20.

Note 16: V

VOamp

= V

VOT-VVOB

Note 17: The same rate applies to V-drive signal on VOut pin.
Note 18: Informative, not tested on each unit.

6.6 - EW DRIVE SECTION

VCC= 12V, T

Symbol Parameter Test Conditions

V

EW

I

EWOut

V

HEHT

V

EW-DC

V

∆

EW DC–

-----------------------------

∆

V

HEH T

V

∆

EW DC–

-------------------------------------

V

EW DC–

V

EW-PCC

V

EW PCC–

--------------------------------------------------------

EW PC C–

tvrTVR=[]

=25°C

amb

Output voltage on EWOut pin 1.8 6.5 V
Current sourced by EWOut out-

put
Control voltage range on HEH-

TIn pin

DC component of the EW-drive
signal on EWOut pin

Breathing compensation on

V

Temperature drift of DC compo­nent of the EW-drive signal on

T∆⋅

EWOut pin

Pin cushion correction compo­nent of the EW-drive signal on
EWOut pin

tvr0=[]

Tracking of PCC component of
the EW-drive signalwith vertical
position adjustment

EW-DC

(19)(22)(23)(30)

tVR=1/2 T

HSIZE

VR

(Sad10h):
00000000b
10000000b
11111111b

(19)(20)(21)(22)

tVR=1/2 T

V

HEHT>VRefO

V

HEHT

(18)(19)(21)(23)(30)

tVR=1/2 T

(19)(20)(21)(23)(24)(25)(26)(30)

VSIZE
PCC

(15)

VR

(min)≤V

VR

at maximum

(Sad0C):
x0000000b
x1000000b
x1111111b

Tracking with

PCC

at x1000000b

VSIZE

(Sad07):
x0000000b
x1000000b

(19)(20)(21)(24)(27)(29)(30)

PCC

at x1111111b

VPOS

(Sad08):
x0000000b
x1111111b

(15)

HEHT

(15)

VSIZE

SCOR

(Sad09 at x0000000b) and null

Value

Min. Typ. Max.

-1.5 0 mA

1 V

3.25

4.5

≤

VRefO

-0.125

100 ppm/°C

0.7

1.5

:

0.25

0.5

0.52

1.92

Units

RefO

2

V

V
V
V

0

V/V
V/V

0

V
V
V

V
V

13/50

TDA9113

Symbol Parameter Test Conditions

Value

Units

Min. Typ. Max.

Keystone correction component

V

EW-Key

of the EW-drive signal on
EWOut pin

Top corner correction compo-

V

EW-TCor

nent of the EW-drive signal on
EWOut pin

Bottom corner correction compo-

V

EW-BCor

∆V

------------------------------------------------------- -

VEWf

---------------------------------------------------------- -

V

EW AC–

Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:

EW

[]∆V

⋅

max

V

∆

EW AC–

V

∆⋅

HEHT

KEYST
TCC

at medium (neutral) value.

BCC

at medium (neutral) value.

PCC

at minimum value.

VPOS

HSIZE

nent of the EW-drive signal on
EWOut pin

Tracking of EW-drive signal with
horizontal frequency

HO

Breathing compensation on

(31)

V

EW-AC

at medium (neutral) value.

at medium (neutral) value.

at minimum value.

Note 25: Defined as difference of (voltage at t
Note 26: Defined as difference of (voltage at t
Note 27:

Note 28: Difference (voltage at t

VSIZE

at maximum value.

=0) minus (voltage at tVR=TVR).

VR

(32)

=0) minus (voltage at tVR=1/2 TVR).

VR
VR=TVR

(20)(21)(22)(23)(24)(27)(28)(30)

KEYST

(Sad0D):
x0000000b
x1111111b

(19)(21)(22)(23)(24)(25)(27)(30)

TCC

(Sad0E):

x0000000b

x1000000b

x1111111b

(19)(20)(22)(23)(24)(26)(27)(30)

BCC

(Sad0F):

x0000000b

x1000000b

x1111111b

VHO>

VHOThrfr

VHO(min)≤VHO≤V

(25)(26)

V

>

HEHT

VRefO

V

(min)≤V

HEHT

HEHT

HOThrfr

≤

VRefO

) minus (voltage at tVR=1/2 TVR).

0.4

-0.4

-1.25
0

+1.25

-1.25
0

+1.25

0

20

0

1.75

Note 29: Ratio ”A/B”of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR.
Note 30: V
Note 31: V

>

, V

HEHT

VRefO

is sum of all components other than V

EW-AC

VEHT

>

VRefO

(contribution of PCC, keystone correction and corner

EW-DC

corrections).

Note 32: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by

external components on PLL1 pins. V

[fmax] is the value at condition VHO>V

EW

HOThrfr

.

V
V

V
V
V

V
V
V

%/V
%/V

%/V
%/V

14/50

6.7 - DYNAMIC CORRECTION OUTPUTS SECTION

TDA9113

VCC= 12V, T

amb

=25°C

Symbol Parameter Test Conditions

Horizontal Dynamic Correction output HDyCor

I

HDyCor

V

HD-DC

V

∆

HD DC–

------------------------------------

V

HD DC–

V

HD-H

Current delivered by HDyCor
output

DC component of the drive signal
on HDyCor output

Temperature drift of DCcomponent
of the drive signal on HDyCor

T∆⋅

Amplitude of H-parabola compo­nent of the drive signal on HDyCor
output

R

L(HDyCor)

(18)

(33)(34)

HDyCorTr Off

HDC-AMP

x0000000b
x1000000b
x1111111b

V

V

-------------------------------------------------- -

V

V

------------------------------------------------------ -

V

TrHSOn[]

HD H–

TrHSOff[]

HD H–

TrEHTOn[]

HD H–

TrEHTOf f[]

HD H–

Impact of horizontal size adjust­ment on HDyCor parabola
(tracking)

Impact of voltage on HEHTIninput
on HDyCor parabola

(35)

(36)

HEHT

HSIZE

00000000b
11111111b

HSIZE

V

HEHT

V

HEHT

HDC-SYM

t

HD-Hoffset/TH

Offset (phase) of parabola on HDy­Cor output

(38)

x0000000b
x1000000b

x1111111b

t

HD-Hflat

Duration of the flat part at the start
of parabola on HDyCor output

fHO=31kHz 500 ns

(38)

Vertical Dynamic Correction output VDyCor

I

VDyCor

V

VD-DC

Current delivered by VDyCor out­put

DC component of the drive signal
on VDyCor output

R

L(VDyCor)

(23)

VSIZE
VDC-AMP

x0000000b

IV

I

VD-V

Amplitude of V-parabola on VDy­Cor output

(40)

x1000000b

x1111111b

VDC-AMP
VSIZE

x0000000b
x1111111b

V

VD V–tvr

--------------------------------------------------

V

VD V–tvrTVR

Note 33:
Note 34:

=[]

HDC-AMP
HDC-SYM

0=[]

Tracking of V-parabola on VDyCor
output with vertical position

at minimum.
at medium.

(37)

VDC-AMP
VPOS

x0000000b
x1111111b

Value

Units

Min. Typ. Max.

-2 0 mA

=10kΩ 2.1 V

200 ppm/°C

(Sad04):

3.7

1.5

0.9

V
V
V

constant

(Sad10h):

(1.34)

2

1

constant

>

VRefO

=

VRefO

-4V

1

(1.07)

2

(Sad05):

(39)

+24.5

0

-24.5

%
%
%

-1.5 0 mA

=10kΩ 4V

at medium

(Sad15h):

0

0.5
1

at maximum

(Sad07):

0.6

1.6

at maximum

(Sad08):

0.52

1.92

V
V
V

V
V

15/50

TDA9113

Note 35: Ratio of the amplitude at

register map”) as a quadratic function of horizontal size adjustment.

Note 36: Ratio of the amplitude at

register map”) as a quadratic function of V

Note 37: Ratio of parabola voltage at t
Note 38: Refer to Figure 14.
Note 39: Taken for reference at given position of
Note 40: Unsigned value. Polarity selection by

HDyCorTr=1 to the amplitude at HDyCorTr=0 (refer to chapter ”I

HDyCorTr=1 to the amplitude at HDyCorTr=0 (refer to chapter ”I

=0 versus parabola voltage at tVR=TVR.

VR

.

HEHT

HDyCorPh flag.

VDyCorPol I

2

C Bus control

2

C Bus control

2

C Bus bit. Refer to section I2C Bus control register map.

16/50

6.8 - DC/DC CONTROLLER SECTION

TDA9113

VCC= 12V, T

amb

=25°C

Symbol Parameter Test Conditions

R

B+FB

A

OLG

f

UGBW

I

RI

I

BComp

A

BISense

V

ThrBIsCurr

I

BISense

t

BOn

I

BOut

V

BOSat

V

BReg

Ext. resistance applied between

BComp output and BRegIn input

Open loop gain of error amplifier
on BRegIn input

Unity gain bandwidth of error am-

Low frequency

(18)

plifier on BRegIn input
Bias current delivered by regula-

tion input BRegIn

Output current capability of BComp
output.

Voltage gain on BISense input 3
Threshold voltage on BISense input

corresponding to current limitation
Input current sourcedby BISense input -1 µA
Conduction time of the power transistor TH- t
Output current capability of BOut out-

put
Saturation voltage of the internal output

transistor on BOut

Regulation reference for BRegIn volt-

(42)

age

HBOutEn = ”Enable”
HBOutEn = ”Disable”

I

=10mA 0.25 0.4 V

BOut

V

=8V

RefO

BREF

(Sad03):
x0000000b
x1000000b
x1111111b

Delay of BOut “Off-to-On” edge after

t

BTrigDel/TH

middle of flyback pulse, as part of T

(43)

BOutPh = ”0” 16 %

H

(18)

Value

Units

Min. Typ. Max.

5kΩ

100 dB

6 MHz

-0.2 µA

(41)

-0.5

0.5

2.0 mA
mA

1.98 2.1 2.22 V

HD-Hflat

010mA

3.65

4.65

5.65

3.85

4.9

5.9

4.05

5.15

6.15

V
V
V

Note 41: A current sink is provided by the BComp output while BOut is disabled:
Note 42: Internal reference related to V

. The same values to be found on pin BRegIn, while regulation loop is

RefO

stabilized.

Note 43: Only applies to configuration specified in ”Testconditions” column, i.e. synchronization of BOut “Off-to-On”

edge with horizontal flyback signal. Refer to chapter ”DC/DC controller” for more details.

17/50

TDA9113

6.9 - MISCELLANEOUS

VCC= 12V, T

Symbol Parameter Test Conditions

amb

=25°C

Value

Units

Min. Typ. Max.

Vertical blanking and horizontal lock indication composite output HLckVBk

I

SinkLckBk

Sink current to HLckVBk pin Note

(44)

100 µA

V.blank H.lock

V

OLckBk

Output voltage on HLckVBk output

No Yes

Yes Yes

No No

Yes No

0.1

1.1
5
6

Horizontal moiré canceller

∆

T

HH moire–()

--------------------------------------­T

H

Modulation of T

by H. moiré function

H

HMOIRE

x0000000b

(Sad02):

x1111111b

0

0.02

Vertical moiré canceller

V

V-moiré

Amplitude of modulation of V-drive sig­nal on VOut pin by vertical moiré.

VMOIRE

x0000000b

(Sad0Bh):

x1111111b

0
3

mV
mV

Protection functions

V

ThrXRay

t

XRayDelay

V

CCEn

V

CCDis

Input threshold on XRayinput
Delay time between XRay detection

event and protection action

VCCvalue for start of operation at V

ramp-up

VCCvalue for stop of operation at V

ramp-down

(46)

(46)

Control voltages on HPosF pin for Soft start/stop operation

V

HOn

V

BOn

V

HBNorm f

Threshold for start/stop of H-drive sig­nal

Threshold for start/stop of B-drive sig­nal

Threshold for full operational duty cycle
of H-drive and B-drive signals

(45)

CC

CC

(18)(47)

7.65 7.9 8.2 V
2T

H

8.5 V

6.5 V

1V

1.7 V

2.4

Normal operation

V

HPosF

Voltage on HPosF pin asfunction of ad­justment of

HPOS

register

HPOS

(Sad01)
00000000b
11111111b

3.8

2.6

4.0

2.8

4.2

3.0

Note 44: Current sunk by the pin if the external voltage is higher than one the circuit tries to force.
Note 45: The threshold is equal to actual V

RefO

.

Note 46: In the regions of VCCwhere the device’s operation is disabled, the H-drive, V-drive and B+-drive signals on

2

HOut, VOut and BOut pins, resp., are inhibited, the I

C Bus does not accept any data and the XRayAlarm

flag is reset. Also see Figure 16

Note 47: See Figure 10

V
V
V
V

%
%

V
V

18/50

7 - TYPICAL OUTPUT WAVEFORMS

Note (48)

Function Sad Pin Byte Waveform Effect on Screen

V

x0000000

Vertical Size 07 VOut

x1111111

amp(min)

V

amp(max)

V

mid(VOut)

V

mid(VOut)

TDA9113

Vertical

Position 08 VOut

S-correction 09 VOut

C-correction 0A VOut

x0000000

x1000000

x1111111

x0000000:

Null

x1111111:

Max.

x0000000

x1000000 :

Null

V

VOamp

V

VOamp

V

VOamp

V

VOamp

V

mid(VOut)

V

VOS-cor

0 1/4T

VR

0 1/2T

V

mid(VOut)

V

mid(VOut)

3/4 T

V

VOC-cor

VR

VRTVR

T

VR

3.5V

3.5V

3.5V

t

VR

t

VR

x1111111

V

VOamp

0 1/2T

V

VOC-cor

VR

T

VR

t

VR

19/50

TDA9113

Function Sad Pin Byte Waveform Effect on Screen

V

amp

(n-1)T

V

amp

(n-1)T

V

EW-DC(min)

V

EW-DC(max)

V

V

0 1/2T

0 1/2T

nT

nT

(n+1)T

V

V

VR

VR

V

V-moiré

(n+1)T

V

t

V

t

T

VR

t

VR

T

VR

t

VR

Vertical moiré

amplitude

0B VOut

Horizontal size 10h EWOut

x0000000:

Null

x1111111:

Max.

00000000

11111111

Keystone

correction

Pin cushion

correction

Top corner

correction

Bottom corner

correction

0D EWOut

0C EWOut

0E EWOut

0F EWOut

x0000000

x1111111

x0000000

x1111111

x1111111

x0000000

x1111111

x0000000

V

EW-key

V

EW-key

V

EW-PCC(min)

0 1/2 T

V

EW-PCC(max)

0 1/2 T

V

EW-TCor(max)

0

V

EW-TCor(min)

0 1/2 T

V

EW-TBot(max)

0 1/2 T

V

EW-TBot(min)

0 1/2 T

1/2 T

VR

VR

VR

VR

VR

VR

V

EW-DC

V

EW-DC

T

VR

t

VR

T

t

VR

VR

T

t

VR

VR

T

t

VR

VR

T

VR

t

VR

T

VR

t

VR

20/50

TDA9113

Function Sad Pin Byte Waveform Effect on Screen

Parallelogram

correction

Pin cushion

asymmetry

correction

Vertical

dynamic
correction
amplitude

HDyCor
horizontal

adjustments

12h

Internal

11h

Internal

15h VDyCor

04

&

HDyCor See Figure 14 on page 36 Application dependent

05

x0000000

x1111111

x0000000

x1111111

01111111

x0000000

11111111

t

ParalC(min)

0 1/2T

t

ParalC(max)

0 1/2T

t

PCAC(max)

0 1/2 T

t

PCAC(max)

0 1/2 T

V

0 1/2 T

V

0 1/2 T

V

0 1/2 T

VD-V(max)

VD-V(max)

VD-V(max)

static phase

VR

static phase

VR

VR

VR

VR

VR

VR

T

VR

t

VR

T

VR

t

VR

static
H-phase

T

VR

t

VR

static
H-phase

T

VR

t

VR

VDyCorP

V

VD-DC

T

VR

t

VR

V

VD-DC

T

VR

t

VR

VDyCorP

V

VD-DC

T

VR

t

VR

Application dependent

Note 48: For any H and V correction component of the waveforms on EWOut and VOut pins and for internal waveform

for corrections of H asymmetry,displayed in the table, weight of the other relevant components is nullified
(minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram,
parabola asymmetry correction, written in corresponding registers).

21/50

TDA9113

8-I2C BUS CONTROL REGISTER MAP

The device slave address is 8C in write mode and 8D in read mode.
Bold weight denotes default value at Power-On-Reset.

I2C Bus data in the adjustment register isbuffered and internally applied with dischargeof the vertical os­cillator
In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0.

(49)

.

SadD7 D6D5D4D3D2D1D0

WRITE MODE (SLAVE ADDRESS = 8C)

HDutySyncV

00

1: Synchro.
0: Asynchro.

01

02

03

04

05

06

07

08

09 Reserved

0A Reserved

0B Reserved

0C Reserved

0D Reserved

0E Reserved

0F Reserved

10

1 000000

HMoiré

1: Separated
0: Combined

B+SyncV

0: Asynchro.

HDyCorTr

0: Not active

HDyCorPh

1: Middle
0: Start

BOutPol

0: Type N

BOutPh

0: H-flyback
1: H-drive

EWTrHFr

0: No tracking

1 000000

0000000

0000000

1000000

1000000

1000000

1000000

1000000

1000000

1000000

0000000

1000000

1000000

1000000

1000000

HDUTY (Horizontal duty cycle)

HPOS (Horizontal position)

HMOIRE (Horizontal moiré amplitude)

BREF (B+reference)

HDC-AMP (HDyCor amplitude)

HDC-SYM (HDyCor symmetry)

Reserved

VSIZE (Vertical size)

VPOS (Vertical position)

SCOR (S-correction)

CCOR (C-correction)

VMOIRE (Vertical moiré amplitude)

PCC (Pin cushion correction)

KEYST (Keystone correction)

TCC (Top corner correction)

BCC (Bottom corner correction)

HSIZE (Horizontal size)

Reserved

Reserved

22/50

TDA9113

SadD7 D6D5D4D3D2D1D0

11 Reserved

12 Reserved
13 Reserved

14 Reserved

VDyCorPol

15

16

17

READ MODE (SLAVE ADDRESS = 8D)

XX

(50)

Note 49: With exception of

0:”∪”

XRayReset

0: No effect
1: Reset

TV

(51)

0:Off

HLock

0: Locked

1: Not locked

1000000

1000000

1000000

VSyncAuto

1:On

TH

0:Off

VLock

0: Locked
1: Not lock.

HDUTY

(51)

VSyncSel

0:Comp
1:Sep

TVM

0:Off

XRayAlarm
1: On

0: Off

and

BREF

(51)

adjustments data that can take effect instantaneously if switches

HDutySyncV and B+SyncV are at 0 respectively.

Note 50: In Read Mode, the device always outputs data of the status register, regardless of sub address previously

selected.

Note 51: The TV,TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.

PCAC (Pin cushion asymmetry correction)

PARAL (Parallelogram correction)

VDC-AMP (Vertical dynamic correction amplitude)

SDetReset

0: No effect
1: Reset

THM

(51)

0: Off

Polarity detection Sync detection

HVPol

1: Negative

0

BOHEdge

0: Falling

VPol

1: Negative

PLL1Pump

1: Fast
0: Slow

HBOutEn

0: Disable

VExtrDet

0: Not det.

PLL1InhEn

1:On

VOutEn

0: Disable

HVDet

0: Not det.

HLockEn

1:On

BlankMode

1: Perm.

VDet

0: Not det.

Description of I2C Bus switches and flags
Write-to bits
Sad00/D7 - HDutySyncV

Synchronization of internal application of Hori-

zontal Duty cycle data, buffered in I2C Bus latch,
with internal discharge of Vertical oscillator

0: Asynchronous mode, new data applied

with ACK bit of I2C Bus transfer on this sub
address

1: Synchronous mode

Sad02/D7 - HMoiré

Horizontal Moiré characteristics

0: Adaptedto an architecturewith EHTgener-

ated in deflection section

1: Adapted to an architecture with separated

deflection and EHT sections

Sad03/D7 - B+SyncV

Same as HDutySyncV, applicable for B+ refer-
ence data

Sad04/D7 - HDyCorTr

Tracking of Horizontal Dynamic Correction

waveform amplitude with Horizontal Size at ad­justment andEHT variation (voltage of HEHTIn).

0: Not active
1: Active

Sad05/D7 - HDyCorPh

Phase of start of Horizontal Dynamic Correction

waveform in relation to horizontal flyback pulse.

0: Start of the flyback
1: Middle of the flyback

Sad06/D7 - BOutPol

Polarity of B+ drive signal on BOut pin

0: adapted to N type of power MOS - high

level to make it conductive

1: adaptedtoP typeof power MOS - low level

to make it conductive

23/50

TDA9113

Sad07/D7 - BOutPh

Phase of start of B+ drive signal on BOut pin

0: Just after horizontal flyback pulse
1: With one of edges of line drive signal on

HOut pin, selected by BOHEdge bit

Sad08/D7 - EWTrHFr

Tracking of all corrections contained in wave-

form on pin EWOut with Horizontal Frequency

0: Not active
1: Active

Sad15/D7 - VDyCorPol

Polarity of Vertical Dynamic Correction wave-

form (parabola)

0: Concave (minimum in the middle of the pa-

rabola)

1: Convex (maximum in the middle of the pa-

rabola)

Sad16/D0 - HLockEn

Enable of output of Horizontal PLL1 Lock/unlock
status signal on pin HLckVBk

0: Disabled, vertical blanking only on the pin

HLckVBk

1: Enabled

Sad16/D1 - PLL1InhEn

Enable of Inhibition of horizontal PLL1 during

extracted vertical synchronization pulse

0: Disabled, PLL1 is never inhibited
1: Enabled

Sad16/D2 - PLL1Pump

Horizontal PLL1 charge Pump current

0: Slow PLL1, low current
1: Fast PLL1, high current

Sad16/D4 - SDetReset

Reset to 0 of Synchronization Detection flags

VDet, HVDet and VExtrDet of status register ef-

fected with ACK bit of I2C Bus data transfer into
register containing the SDetReset bit. Also see
description of the flags.

0: No effect
1: Reset with automatic return of the bit to 0

Sad16/D5 - VSyncSel

Vertical Synchronization input Selection be-

tween the one extracted from composite HV sig­nal on pin H/HVSyn and the one on pin VSyn.
No effect if VSyncAuto bit is at 1.

0: V.sync extractedfromcomposite signal on

H/HVSyn pin selected

1: V. sync applied on VSyn pin selected

Sad16/D6 - VSyncAuto

Vertical Synchronization input selection Auto-

matic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the
one on pin VSyn, based on detection mecha­nism. If both are present, the one coming first is
kept.

0: Disabled, selection done according to bit

VSyncSel

1: Enabled, the bit VSyncSel has no effect

Sad16/D7 - XRayReset

Reset to 0 of XRay flag of status register effect-

ed with ACK bit of I2C Bus data transfer into reg­ister containing the XRayReset bit. Also see de­scription of the flag.

0: No effect
1: Reset with automatic return of the bit to 0

Sad17/D0 - BlankMode

Blanking operation Mode

0: Blanking pulse starting with detection of

vertical synchronization pulse and ending
with end of vertical oscillator discharge
(startofvertical sawtoothramp onthe VOut
pin)

1: Permanentblanking -high blanking level in

composite signal on pin HLckVBk is per­manent

24/50

Sad17/D1 - VOutEn

Vertical Output Enable

0: Disabled, V

Vertical section)

on VOut pin (see 6.5 -

offVOut

1: Enabled,verticalrampwith vertical position

offset on VOut pin

TDA9113

Sad17/D2 - HBOutEn

Horizontal and B+ Output Enable

0: Disabled, levels corresponding to “power

transistor off”on HOutand BOut pins(high
for HOut,high or low for BOut, depending
on BOutPol bit).

SadXX/D2 - VExtrDet

Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V sig­nal applied on H/HVSyn pin

0: Not detected
1: Detected

(52)

1: Enabled, horizontal deflection drive signal

on HOutpin providingthat it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin.

Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in ex­ternal sawtooth configuration.

Sad17/D3 - BOHEdge

Selection of Edge of Horizontal drive signal to
phase B+ drive Output signal on BOut pin. Only
applies if the bit BOutPh is set to 1, otherwise

BOHEdge has no effect.

0: Falling edge
1: Rising edge

Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV

Test bits. They must be kept at 0 level by appli­cation S/W.

Read-out flags
SadXX/D0 - VDet

(52)

Flag indicating Detection of V synchronization
pulses on VSyn pin.

0: Not detected
1: Detected

SadXX/D1 - HVDet

(52)

SadXX/D3 - VPol

Flag indicating Polarity of V synchronization
pulses appliedon VSynpin withrespect tomean
level of the sync signal

0: Positive
1: Negative

SadXX/D4 - HVPol

Flag indicating Polarity of H or HV synchroniza­tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal

0: Positive
1: Negative

SadXX/D5 - XRayAlarm

Alarm indicating that an event of excessive volt-

age has passed on XRay pin. Can only be reset
to 0 through I2C Bus bit XRayResetor by power­on reset.

0: No excess since last reset of the bit
1: At least one event of excess appeared

since thelast resetof thebit, HOutinhibited

SadXX/D6 - VLock

Status of “Locking” or stabilization of Vertical os­cillator amplitude to an internal reference by
AGC regulation loop.

0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)

Flag indicating Detection of H or HV synchroni­zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.

0: Not detected

SadXX/D7 - HLock

Status of Locking of Horizontal PLL1

0: Locked
1: Not locked

1: Detected.

Note 52: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last

reset (by means of the
that enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through
out of status register.

SDetReset I

2

C Bus bit). This is to be taken into account by application S/W in a way

SDetReset bit and validation of information provided in the flag after read-

25/50

TDA9113

9 - OPERATING DESCRIPTION

9.1 - SUPPLY AND CONTROL

9.1.1 - Power supply and voltage references

The device is designed for a typical value of power
supply voltage of 12 V.

In order to avoid erratic operation of the circuit at
power supply ramp-up or ramp-down, the value of

VCCis monitored. See Figure 1 and electrical

specifications. At switch-on, the device enters a
“normal operation” as the supply voltage exceeds

V
V

ence, a hysteresis to bridge potential noise. Out­side the “normal operation”, the signals on HOut,
BOut and VOut outputs are inhibited and the I2C
bus interface is inactive (high impedance on SDA,
SCL pins, no ACK), all I2C bus control registers
being reset to their default values (see chapter I2C
BUS CONTROL REGISTER MAP on page 22).

Figure 1. Supply voltage monitoring

Internal thresholds in all parts of the circuit are de­rived from a common internal reference supply

V

tering against ground as well as for external use
with load currents limited to I
necessary to minimize interference in output sig­nals, causing adverse effects like e.g. jitter.

9.1.2 - I2C Bus Control

The I2C bus isa 2 linebi-directional serial commu­nication bus introduced by Philips. For its general
description, refer to corresponding Philips I2Cbus
specification.

This device is an I2C bus slave, compatible with
fast (400kHz) I2C bus protocol, with write mode
slave address of 8C (read mode slave address
8D). Integrators are employed at the SCL (Serial

and stays there until it decreases bellow

CCEn

. The two thresholds provide, by their differ-

CCDis

V

V

(Vcc)

that is lead out to RefOut pin for external fil-

RefO

CC

V

CCEn

Disabled Disabled

hysteresis

Normal operation

RefO

. The filtering is

V

CCDis

t

Clock) input and atthe inputbuffer ofthe SDA (Se­rial Data)input/output to filter off thespikes ofup to
50ns.

The device supports multiple data byte messages
(with automatic incrementation of the I2C bus sub­address) as well as repeated Start Condition for
I2C bus subaddress change inside the I2Cbus
messages. All I2C bus registers with specified I2C
bus subaddress areof WRITE ONLY type, where­as the status register providing a feedback infor­mation to the master I2C bus device has no attrib­uted I2C bus subaddress and is of READ ONLY
type. Themaster I2C busdevice reads this register
sending directly, after the Start Condition, the
READ device I2C bus slave address (8D) followed
by the register read-out, NAK (No Acknowledge)
signal and the Stop Condition.

For the I2C buscontrol register map, refer to chap­ter I2C BUS CONTROL REGISTER MAP on
page 22.

9.2 - SYNC. PROCESSOR

9.2.1 - Synchronization signals

The device has two inputs for TTL-levelsynchroni­zation signals, both with hysteresis to avoid erratic
detection and with a pull-down resistor. On H/
HVSyn input, pure horizontal or composite hori­zontal/vertical signal is accepted. On VSyn input,
only pure vertical sync. signal is accepted. Both
positive and negative polarities may be applied on
either input, see Figure 2. Polarity detector and
programmable inverter are provided on each of
the twoinputs. The signal applied on H/HVSyn pin,
after polarity treatment, is directly lead to horizon­tal part andto an extractor of vertical sync. pulses,
working on principle of integration, see Figure 3.
The vertical sync. signal applied to thevertical de­flection processor is selected between the signal
extracted from the composite signal on H/HVSyn
input and the one applied on VSyn input. The se­lector is controlled by VSyncSel I2C bus bit.

Besides the polarity detection, the device is capa­ble of detecting the presence of sync. signals on
each of the inputs and at the output of vertical
sync. extractor. The information from all detectors
is provided in the I2C bus status register (5 flags:
VDet, HVDet, VExtrDet, VPol, HVPol). The device
is equipped with an automatic mode (switched on
or off byVSyncAuto I2C bus bit) that alsouses the
detection information.

26/50

TDA9113

Figure 2. Horizontal sync signal

show in real time the presence or absence of the
corresponding sync. signal. They are latched to 1
as soon as a single sync. pulse is detected. In or-

Positive

T

H

t

PulseHSyn

der to reset them to 0 (all at once), a 1 must be
written into SDetReset I2C bus bit,the reset action
taking effect with ACK bit of the I2C bus transfer to
the register containing the SDetReset bit. The de­tection circuits are then ready to capture another

Negative

event (pulse). See Note 52.

9.2.2 - Sync. presence detection flags

The sync. signal presence detection flags in the
status register (VDet, HVDet, VExtrDet) do not

Figure 3. Extraction of V-sync signal from H/V-sync signal

H/V-sync

Internal

Integration

Extracted

V-sync

T

H

t

PulseHsyn

t

extrV

9.2.3 - MCU controlled sync. selection mode

I2C bus bit VSyncAuto is set to 0. The MCU reads
the polarity and signal presence detection flags,
after setting the SDetReset bit to 1 and an appro­priate delay, to obtain a true informationof the sig­nals applied, reads and evaluates this information
and controls the verticalsignal selector according­ly. The MCU has no access to polarity inverters,
they are controlled automatically.

See also chapter I2C BUS CONTROL REGISTER
MAP on page 22.

9.2.4 - Automatic sync. selection mode

I2C bus bit VSyncAuto is set to 1. In this mode, the
device itself controls the I2C bus bits switching the
polarity inverters (HVPol, VPol) and the vertical
sync. signal selector (VSyncSel), using the infor­mation provided by detection circuitry. If both ex­tracted and pure vertical sync.signals arepresent,
the one already selected is maintained. No inter­vention of the MCU is necessary.

9.3 - HORIZONTAL SECTION

9.3.1 - General

The horizontal section consists of two PLLs with
various adjustments and corrections, working on
horizontal deflection frequency, then phase shift-

ing and output driving circuitry providing H-drive
signal on HOut pin. Input signal to the horizontal
section is output of the polarity inverter on H/
HVSyn input. The device ensures automatically
that this polarity be always positive.

9.3.2 - PLL1

The PLL1 block diagram is in Figure 5. It consists
of a voltage-controlled oscillator (VCO), a shaper
with adjustablethreshold, a charge pump withinhi­bition circuit, a frequency and phase comparator
and timing circuitry. The goal of the PLL1 is to
make theVCO ramp signal match infrequency the
sync. signal and to lock this ramp in phase to the
sync. signal, with a possibility to adjust a perma­nent phase offset. On the screen, this offset re­sults inthe change ofhorizontal position of thepic­ture. The loop, by tuning the VCO accordingly,
gets and maintains in coincidence the rising edge
of inputsync. signal withsignal REF1, which is de­rived from the VCO ramp by a comparator with
threshold adjustable through

HPOS

I2C bus con­trol. The coincidence is identified and flagged by
lock detection circuit on pin HLckVBk aswell as by
HLock I2C bus flag.

The charge pump provides positive and negative
currents charging the external loop filter on HPosF
pin. The loop is independent of the trailing edge of
sync. signal and only locks to its leading edge. By
design, the PLL1 does not suffer from any dead

27/50

TDA9113

band even while locked. The speed of the PLL1
depends on the current value provided by the
charge pump. While notlocked, the currentis very
low, to slow down the changes of VCO frequency
and thus protect the external power components
at sync. signal change. In locked state, the cur­rents are much higher, two different values being
selectable via PLL1Pump I2C bus bit to provide a
mean to control the PLL1 speed by S/W. Lower
values make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depends on the choice of ex­ternal components making up the loop filter. A
“CRC” filter is generally used (see Figure 4 on
page 28).

Figure 5. Horizontal PLL1 block diagram

Figure 4. H-PLL1 filter configuration

HPLL1F

9

R

2

C

2

C

1

The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac­count missing or wrong pulses on the phase com­parator. Inhibitionis obtained byforcing thecharge
pump output to high impedance state. The inhibi­tion mechanism can be disabled through
PLL1Pump I2C bus bit.

The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control

HPOS

.

H/HVSyn

1

Sync

Polarity

INPUT

INTERFACE

Extracted

V-sync

PLL1

LOCK

DETECTOR

COMP

REF1

High

Low

Lock

Status

2

(pin & I

CHARGE

PUMP

PLL1Pump

2

(I

C)

PLL1InhEn

(I

C)

2

V-sync (extracted)

C)

PLL

INHIBITION

HPosF

10

SHAPER

HPLL1F R0 C0

86

9

VCO

HOSC

HPOS

2

(I

C)

HOscF

4

28/50

Figure 6. Horizontal oscillator (VCO) schematic diagram

(PLL1 filter)

HPLL1F

from charge pump

I

0

I

2

V

HO

9

+

-

RO

0

4I

8

0

V

HOThrHi

V

6

4

HOThrLo

CO

HOscF

+

-

-

+

V

HOThrHi

V

HOThrLo

TDA9113

RS

Flip-Flop

VCO discharge

control

9.3.3 - Voltage controlled oscillator

The VCO makes part of both PLL1 and PLL2
loops, being an “output” to PLL1 and “input” to
PLL2. It delivers a linear sawtooth. Figure 6 ex­plains itsprinciple of operation. The linears are ob­tained bycharging anddischarging an external ca­pacitor on pinCO, with currents proportional to the
current forced through an external resistor on pin
RO, which itself depends on the input tuning volt­age VHO(filtered charge pump output). The rising
and falling linears are limited by V

V

HOThrHi

thresholds filtered through HOscF pin.

HOThrLo

and

At no signal condition, the VHOtuning voltage is
clamped to its minimum (see chapter ELECTRI­CAL PARAMETERS AND OPERATING CONDI­TIONS, part horizontal section), which corre­sponds to the free-running VCO frequency f
Refer to Note 1 forthe formula to calculate thisfre-

HO(0)

quency usingexternal components values.The ra­tio between the frequency corresponding to maxi­mum VHOand the one corresponding to minimum

VHO(free-running frequency) is about 4.5. This

range can easily be increased in the application.
The PLL1 can onlylock to input frequenciesfalling
inside these two limits.

9.3.4 - PLL2

The goal of the PLL2 is, by means of phasing the
signal driving the power deflection transistor, to
lock the middle of the horizontal flyback to a cer­tain threshold of the VCO sawtooth. This internal
threshold is affected by geometry phase correc­tions, like e.g., parallelogram. The PLL2 is much
faster thanPLL1 to be able to follow the dynamism
of thisphase modulation.The PLL2control current
(see Figure 7) is significantly increased during dis­charge of vertical oscillator (during vertical retrace
period) to be able to make up for the difference of
dynamic phase at the bottom and at the top of the
picture. The PLL2 control current is integrated on

the external filter on pin HPLL2C to obtain
smoothed voltage, used, in comparison with VCO
ramp, asa threshold for H-drive risingedge gener­ation.

As both leading and trailing edges of the H-drive
signal in the Figure 7 must fallinside therising part
of the VCO ramp, an optimum middle position of
the threshold has been found to provide enough
margin forhorizontal outputtransistor storage time
as well as for the trailing edge of H-drive signal
with maximum duty cycle. Yet, the constraints
thereof must be taken into account while consider­ing the application frequency range and H-flyback
duration. The Figure 7 also shows regions for ris­ing and fallingedges of theH-drive signal onHOut
pin. As it is forced high during the H-flyback pulse
and lowduring theVCO discharge period, no edge

.

during these two events takes effect.
The flyback input configuration is in Figure 8.

9.3.5 - Dynamic PLL2 phase control

The dynamic phase control of PLL2 is used to
compensate for picture asymmetry versus vertical
axis across the middle of the picture. It is done by
modulating the phase of the horizontal deflection
with respect to the incoming video (synchroniza­tion). Inside the device, the threshold V
pared with the VCO ramp, the PLL2 locking the
middle of H-flyback to the moment of their match.
The dynamic phase is obtained by modulation of
the threshold by correction waveforms. Refer to
Figure 12 and to chapter TYPICAL OUTPUT
WAVEFORMS. The correction waveforms have
no effect in vertical middle of the screen (for mid­dle verticalposition).As they are summed, their ef­fect onthe phase tends to reachmaximum span at
top and bottom of the picture. As all the compo­nents of the resulting correction waveform (linear
for parallelogram correction and parabola of 2nd
order for Pin cushion asymmetry correction) are

S(0)

iscom-

29/50

TDA9113

generated from the output vertical deflection drive
waveform, they both track with real vertical ampli­tude and position (including breathing compensa­tion), thus being fixed on the screen. Refer to I2C
BUS CONTROL REGISTER MAP on page 22 for
details on I2C bus controls.

Figure 7. Horizontal timing diagram

t

H-sync

(polarized)

PLL1 lock

REF1

(internal)

V

HPosF

max.

H-Osc

(VCO)

H-flyback

PLL2

control

control
current

H-drive

(on HOut)

H-drive

region

H-drive

region

t

: HOTstorage time

S

med.

min.

ON

t

ph(max)

Hph

min max

t

S

+

V

S(0)

7/8T

H

T

H

V

ThrHFly

-

OFF

t

Hoff

forced high forced low

inhibited

ON

V

HOThrHi

V

HPOS

(I2C)

max.
med.
min.

HOThrLo

PLL1

Figure 8. HFly input configuration

~500Ω

HFly

12

~20kΩ

int.ext.

GND

9.3.6 - Output Section

The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCCis too low, when
X-ray protection is activated (XRayAlarm I2C bus
flag set to 1) and when I2C bus bit HBOutEn is set
to 0 (default position).

The duty cycle of the H-drive signal is controlled
via I2C bus register

HDUTY

. This is overruled dur­ing soft-start and soft-stop procedures (see sub
chapter Soft-start and soft-stop on H-drive on
page 30 and Figure 10).

The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see sub chapter Horizontal moiré cancellation on
page 30)

The output stage consists of a NPN bipolar tran­sistor, the collector of which is routed to HOut pin
(see Figure 9).

Figure 9. HOut configuration

26

HOut

int. ext.

Non-conductive state of HOT (Horizontal Output
Transistor) must correspond to non-conductive
state of the device output transistor.

9.3.7 - Soft-start and soft-stop on H-drive

PLL2

The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I2C bus bit or after re­set of XRayAlarm I2C bus flag, to protect external
power components.By itssecond function, the ex­ternal capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of H­drive signal starts at its maximum (“t

Hoff/TH

start/stop” in electrical specifications) and slowly
decreases to the value determined by the control
I2C bus register

HDUTY

(vice versa at soft-stop).
This is controlled by voltage on pin HPosF. See
Figure 10 and sub chapter Safety functions on
page 38.

9.3.8 - Horizontal moiré cancellation

The horizontalmoiré cancelleris intended toblur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes vis­ible moiré patterns in the picture.

It introduces a microscopic indent on horizontal
scan lines by injecting little controlled phase shifts
to output circuitry of the horizontal section. Their
amplitude is adjustable through

HMOIRE

control.
The behaviour of horizontal moiré is to be opti-

mised fordifferent deflectiondesign configurations
using HMoiré I2C bus bit.This bit is to be kept at 0
for common architecture (B+ and EHT common

for soft

I2C bus

30/50

regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).

Figure 10. Control of HOut and BOut at start/stop at nominal V

TDA9113

cc

V

V

(HPosF)

V

HOn

HOut
H-duty cycle

BOut (positive)
B-duty cycle

V

BOn

V

Soft start

Start
HOut

V

HBNorm

Start

BOut

HPosMax

HPosMin

Normal operation

9.4 - VERTICAL SECTION

9.4.1 - General

The goal of the vertical section is to drive vertical
deflection output stage. It delivers a sawtooth
waveform with an amplitude independent of de­flection frequency, on whichvertical geometry cor­rections of C- and S-type are superimposed (see
chapter TYPICAL OUTPUT WAVEFORMS).

Block diagram is inFigure 11. The sawtooth is ob­tained by charging an external capacitor on pin
VCap with controlled current and by discharging it
via transistor Q1. This is controlled by the CON­TROLLER. The charging starts when the voltage
across the capacitor drops below V
The discharging starts either when it exceeds V
threshold or a short time after arrival of synchroni­zation pulse. This time is necessary for the AGC
loop to sample the voltage at the top of the saw­tooth. The V

reference is routed out onto VO-

VOB

scF pin in order to allow for further filtration.
The charging current influences amplitude and

shape of the sawtooth. Just before the discharge,
the voltage across the capacitor on pin VCap is
sampled and stored on a storage capacitor con­nected on pinVAGCCap. During the following ver-

VOB

threshold.

VOT

minimum value

HPOS

(I2C)

range

maximum value

Soft stop

Stop

Stop

BOut

HOut

t

100%

0%

tical period, this voltage is compared to internal
reference REF (V
ling thegain ofthe transconductance amplifierpro-

), the result thereof control-

VOT

viding the charging current. Speed of this AGC
loop depends on the storage capacitance on pin
VAGCCap. The VLock I2C bus flag is set to 1
when the loop is stabilized, i.e. when the voltage
on pin VAGCCap matches V

value. On the

VOT

screen, this corresponds to stabilized vertical size
of picture. After a change of frequency on the
sync. input, the stabilization time depends on the
frequency difference and on the capacitor value.
The lower its value, the shorter the stabilization
time, buton the other hand,the lower the loop sta­bility. A practical compromise is a capacitance of
470nF. The leakage current of this capacitor re­sults in difference in amplitude between low and
high frequencies.The higher its parallel resistance

R

L(VAGCCap)

, the lower this difference.

When the synchronization pulse is not present, the
charging current is fixed. As a consequence, the
free-running frequency f

only depends on the

VO(0)

value of the capacitor on pin VCap. It can be
roughly calculated using the following formula

f

VO(0)

150nF

=

C

(VCap)

.

100Hz

31/50

TDA9113

The frequency range in which the AGC loop can
regulate the amplitude also depends on this ca­pacitor.

The C- and S-corrections of shape serve to com­pensate for the vertical deflection system non-line­arity. They are controlled via

CCOR

and

SCOR

I2C bus controls.
Shape-corrected sawtooth with regulated ampli-

tude is lead to amplitude control stage. The dis­charge exponential is replaced by V
which, under control of the CONTROLLER, cre-

VOB

level,

ates a rapid falling edge and a flat part before be­ginning of new ramp. Mean value of the waveform
output on pin VOut is adjusted by means of
I2C bus control, its amplitude through

VPOS

VSIZE

I2C

bus control. Vertical moiré is superimposed.

Figure 11. Vertical section block diagram

OSC

Cap.

Discharge

VSyn

2

Synchro

Controller

The biasing voltage for external DC-coupled verti­cal power amplifier is to be derived from V
voltage providedon pin RefOut, usinga resistor di­vider, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of V
mean output value) between particular devices.

value (and so

RefO

9.4.2 - Vertical moiré

To blur the interaction of deflection lines with CRT
mask grid pitch that can generate moiré pattern,
the pictureposition is tobe alternatedat half-frame
frequency. Forthis purpose, asquare waveform at
half-frame frequency is superimposed on the out­put waveform’s DC value. Its amplitude is adjusta­ble through

VCap

22

Q1

VMOIRE

Chargecurrent

Sampling

I2C bus control,.

Transconductanceamplifier

REF

20

VAGCCap

Sampling
Capacitance

S-correction

RefO

Polarity

19

VOscF

9.5 - EW DRIVE SECTION

The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an exter­nal DC-coupled power stage, serves to compen­sate for those geometry errors of the picture that
are symmetric versus vertical axis across the mid­dle of the picture.

SCOR

(I2C)

18

23

2

(I

C)

VEHTIn

VOut

V

VOB

VMOIRE

VPOS

sawtooth
discharge

(I2C)
(I2C)

VSIZE

(I2C)

CCOR

CCOR

C-correction

The waveform consistsof an adjustable DC value,
corresponding tohorizontal size,aparabola of2nd
order for “pin cushion”correction, a linear for “key­stone” correction and independent half-parabolas
of 4th order for top and bottom corner corrections.
All of them are adjustable via I2C bus, see I2C
BUS CONTROL REGISTER MAP on page 22
chapter.

32/50

TDA9113

Refer to Figure 12, Figure 13 and to chapter TYP­ICAL OUTPUT WAVEFORMS. The correction
waveforms have no effect in the vertical middle of
the screen (if the
medium value). As they are summed, the resulting
waveform tends to reach its maximum span at top
and bottom of the picture. The voltage at the
EWOut is top and bottom limited (see parameter

VEW). According to Figure 13, especially the bot-

tom limitation seems to be critical for maximum
horizontal size (minimum DC). Actually it is not
critical sincethe parabola componentmust always
be applied. As all the components of the resulting
correction waveform are generated from the out­put vertical deflection drive waveform, they all
track with real vertical amplitude and position (in­cluding breathing compensation), thus being fixed
vertically on the screen. They are also affected by
C- andS-corrections. The sumof components oth­er than DC is affected by value in

VPOS

control is adjusted to its

HSIZE

I2C bus

control in reversedsense. Refer to electrical spec­ifications for value. The DC value, adjusted via

HSIZE

HTIn input, thus providing a horizontal breathing
compensation (seeelectrical specificationsfor val­ue). The resulting waveform is conditionally multi­plied with voltage on HPLL1F, which depends on
frequency. Refer to electrical specifications for val­ue and moreprecision. This tracking with frequen­cy provides a rough compensation of variation of
picture geometry with frequency and allows to fix
the adjustmentranges of I2C buscontrols through­out the operating range of horizontal frequencies.
It can be switched off by EWTrHFr I2C bus bit (off
by default).

The EW waveform signal is buffered by an NPN
emitter follower, the emitter of which is directly
routed to EWOut output,with nointernal resistorto
ground. It is to be biased externally.

control, is also affected by voltage on HE-

33/50

TDA9113

Figure 12. Geometric corrections’ schematic diagram

Controls:

one-quadrant

two-quadrant

V

mid(VOut)

VOut

23

Vertical ramp

HDC-AMP

HDC-SYM

2

Top parabola

generator

2

2

Bottom parabola

generator

(I2C)

(I2C)

Tracking

HEHTIn/HSize

HDyCorTr (I

H-dynamic

correction

(I2C)

TCC

(I2C)

BCC

2

C)

KEYST

VDC-AMP

VDyCorPol (I2C)

2

(I

PCC

2

C)

(I

PCAC

(I

C)

HEHTIn/HSize

(I2C)

2

C)

11

Tracking

Tracking

with Hor
Frequency

HDyCor

32

VDyCor

HSize

17

HEHTIn

PARAL

To horizontal

dyn. phase control

(I2C)

24

EWOut

34/50

Figure 13. EWOut output waveforms

V

(EWOut)

V

EW-Key

Keystone PCC

V

EW-PCC

alonealone

V

V

EW-TCor

V

EW-BCor

Top Bottom

Corners

alone

EW-DC

V

EW

HSIZE

m

a

xim

m

e

d

iu

m

in

im

non-authorized region

VEW(min)

Breathing

compensation

(max)

u

m

m

u

m

(I2C)

TDA9113

operating range

EW

V

V

V

(VCap)

(VCap)

T

0

0

T

0

0

VR

VR

9.6 - DYNAMIC CORRECTION
OUTPUTS SECTION

9.6.1 - Horizontal dynamic correction output

HDyCor

A parabolic waveform at horizontal frequency is
output on pin HDyCor. It can be adjusted in ampli­tude and phase (
bus controls). See also I2C BUS CONTROL REG­ISTER MAP on page 22. The minimum value in
horizontal parabola amplitude I2C bus control
does not correspond to null horizontal amplitude.
Refer to Figure 14. The phase of theparabola can
roughly be adjusted via
coincide either with the beginning or the middle of
the H-flyback pulse. Moreover, its centre can be
offset via

HDC-SYM

part of a quasi-constant length at the beginning of

HDC-AMP

and

HDyCorPh

HDC-SYM

I2C bus bit to

I2C buscontrol. There is aflat

I2C

V

(min)

V

(min)

HEHT

HEHT

Vertical sawtooth

Vertical sawtooth

0

0

T

T

VR

VR

T

T

VR

VR

t

t

VR

VR

the parabola. Refer to electrical specifications for
values.

The parabola tracks with value in

HSIZE

and is horizontal breathing compensated if

CorTr

I2C bit is set to 1 (0 by default).

9.6.2 - Vertical dynamic correction output

VDyCor

A parabolaat vertical deflection frequency is avail­able onpin VDyCor. Its amplitude isadjustable via

VDC-AMP

I2C bus control and polarity controlled
via VDyCorPol I2C bus bit. It tracks with real verti­cal amplitude and position (including breathing
compensation). It is also affected by C- and S-cor­rections.

The use of both correction waveforms is up to the
application (e.g. dynamic focus).

V

V

RefO

RefO

V

(HEHT)

control

HDy-

35/50

TDA9113

Figure 14. HDyCor output horizontal component waveform

T

H

t

HVD-Hflat

t

HVD-Hoffset

(min) (max)

t

HVD-Hoffset

V

HVD-H

V

HVD-DC

1

Shaped H-flyback

0

HDyCorPh

9.7 - DC/DC CONTROLLER SECTION

The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC conver­tor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize poten­tial interference into the picture.

Its operation is similarto that of standard UC3842.
The schematic diagram of the DC/DC controller is

in Figure 15. The BOutoutput controls an external
switching circuit (a MOS transistor) delivering
pulses synchronized on horizontal deflection fre­quency, the phase of which depends on I2C bus
configuration, seethe table at the end of this chap­ter. Their duration depends on feedback provided
to the circuit, generally a copy of DC/DCconverter
output voltage and a copy of current passing
through the DC/DC converter circuitry (e.g. current
through external power component). The polarity
of the output can becontrolled by BOutPol I2C bus

2

(I

C)

bit. ANPN transistor open-collectoris routedout to
the BOut pin.

During the operation, a sawtooth is to be found on
pin BISense, generated externally by the applica­tion. According to BOutPh I2C bus bit, the R-S flip­flop is set either at H-drive signal edge (rising or
falling, depending on BOHEdge I2C bus bit), or a
certain delay (t

BTrigDel/TH

) after middle of H-fly­back. The output is set On at the end of a short
pulse generated by the monostable trigger.

Timing of reset of the R-S flip-flop affects duty cy­cle of the output squaresignal and so the energy
transferred from DC/DC converter input to its out­put. A reset edge is provided by comparator C2 if
the voltage on pin BISense exceeds the internal
threshold V

ThrBIsCurr

. This represents current limi­tation if a voltage proportional to the current
through the power component or deflection stage
is available on pin BISense. This threshold is af­fected by the voltage on pin HPosF, which rises at
soft start and descends at soft stop. This ensures
self-contained soft control of duty cycle of the out­put signalon pin BOut. Refer toFigure 10. Another

36/50

TDA9113

condition for the reset of the R-S flip-flop, OR-ed
with the one described before, is that the voltage
on pin BISense exceeds the voltage VC1, which
depends on the voltage applied on input BISense
of the error amplifier O1. The two voltages are

Both step-up (DC/DC converter output voltage
higher than its input voltage) and step-down (out­put voltage lower than input) are possible.

DC/DC controller Off-to-On edge timing

compared, and the reset signal generated by the
comparator C1. The error amplifier amplifies (with
a factor defined by external components) the dif­ference between the input voltage proportional to
DC/DC convertoroutput voltage and internal refer­ence V
put voltage is I2C bus adjustable by means of

BREF

. Theinternal reference and so theout-

BReg

I2C bus control.

Figure 15. DC/DC converter controller block diagram

BOHEdge

2

BOutPh

C)

H-drive edge

H-flyback
(+delay)

Feedback

V

BReg

BRegIn

BComp

V

ThrBIsCurr

(I

+

O1

-

Soft start

2

C)

(I

Monostable

~500ns

V

C1

2R

R

-

C1

+

-

C2

+

BOutPh
(Sad07/

D7)

BOHEdge

(Sad17/

D3)

0 don’t care Middle of H-flyback plus t
1 0 Falling edge of H-drive signal
1 1 Rising edge of H-drive signal

I1

S

Q

R

HBOutEn

XRayAlarm

(I

Timing of Off-to-On transition

on BOut output

I2

N type

P type

BOutPol

(I

2

C)

I3

2

C)

V

CC

BOut

BTrigDel

HPosF

BIsense

37/50

TDA9113

9.8 - MISCELLANEOUS

9.8.1 - Safety functions

The safety functions comprise supply voltage
monitoring with appropriate actions, soft start and
soft stop features on H-drive and B-drive signals
on HOut and BOut outputs and X-ray protection.

For supply voltage supervision, refer to paragraph
Power supply and voltage references on page 26
and Figure 1. A schematic diagram putting togeth­er all safety functions and composite PLL1 lock
and V-blanking indication is in Figure 16.

9.8.2 - Soft start and soft stop functions

For softstart and soft stop features for H-drive and
B-drive signal, refer to paragraph Soft-start and
soft-stop on H-drive on page 30 and sub chapter­DC/DC CONTROLLER SECTION on page 36, re­spectively. See also the Figure 10. Regardless
why the H-drive or B-drive signal are switched on
or off (I2C bus command, power up or down, X-ray
protection), the signals always phase-in and
phase-out in the way drawn in the figure, the first

to phase-inand last to phase-outbeing theH-drive
signal, which is to better protect the power stages
at abrupt changes like switch-on and off. The tim­ing of phase-in and phase-out only depends on
the capacitance connected to HPosF pin which is
virtually unlimited for thisfunction. Yet it has adual
function (see paragraph PLL1 on page 27), so a
compromise thereof is to be found.

9.8.3 - X-ray protection

The X-ray protection is activated if the voltage lev­el onXRay inputexceeds V
consequence, the H-drive and B-drive signals on
HOut and BOut outputs are inhibited (switched off)
after a 2-horizontal deflection line delay provided
to avoid erratic excessive X-ray condition detec­tion at short parasitic spikes. The XRayAlarm I2C
bus flag is set to 1 to inform the MCU.

This protectionis latched;it may be reset either by

VCCdrop or by I2C bus bit XRayReset (see chap-

ter I2C BUS CONTROL REGISTER MAP on
page 22).

ThrXRay

threshold. As a

38/50

Figure 16. Safety functions - block diagram

TDA9113

HBOutEn

2

I

C

V

CCEn

V

CCDis

29

Vcc

XRayReset

2

C

I

XRay

25

V

ThrXRay

HFly

12

V

ThrHFly

VOutEn

2

C

I

VCCsupervision

+

_

+

_

H-VCO

discharge

control

+
_

In Out

:2

R

RSQ

HPosF

(timing)

10

SOFT START

& STOP

B-drive inhibit
H-drive inhibit

2

I

XRayAlarm

H-drive inhibition

(overrule)

V-drive inhibition

C

BlankMode

2

C

I

HlockEn

2

I

C

H-lock detector

V-sawtooth

discharge

V-sync

B-drive inhibition

L1=No blank/blank level

Σ

HLckVbk

L3=L1+L2

3

L2=H-lock/unlock level

HLock

Q

R

2

I

C

S

2

I

C3I2C bit/flag

Int. signal

Pin

39/50

TDA9113

9.8.4 - Composite output HLckVBk

The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic di­agram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 16, the combinations, their respective
levels andthe HLckVBk configuration in Figure 17.

The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator dis­charge. Thecombination correspondsto the draw­ing in Figure 17. The blanking pulse is started with

Figure 17. Levels on HLckVBk composite output

V

CC

HLckVBk3

I

SinkLckBlk

the leading edge of any of the two signals, which­ever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I2C bus bit, when
at 1 (default), the blanking level (one of two ac­cording to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking,
irrespective of the BlankMode I2C bus bit, is also
provided if the supply voltage is low (under V
or V

thresholds), if the X-ray protection is ac-

CCDis

CCEn

tive or if the V-drive signal is disabled by VOutEn
I2C bus bit.

L1 - No blank/blank level
L2 - H-lock/unlock level

L1

+L2

(H)

(H)

L1

+L2

(L)

(H)

V

OLckBlk

V-early blanking

HPLL1 locked

L1

(L)

Yes

+L2

(L)

L1

+L2

(H)

(L)

YesNo
Yes No

No Yes

No

40/50

Figure 18. Ground layout recommendations

TDA9113

1
2

TDA9113

3
4
5
6

7
8
9
10
11
12
13
14
15

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

16 17

General Ground

41/50

TDA9113

10 - INTERNAL SCHEMATICS

Figure 19.

Figure 22.

Pins 1-2
H/HVSyn
VSyn

Figure 20.

HLckVBkl

5V

3

200Ω

12V

13

RefOut

5

HPLL2C

Figure 23.

12V

6

C0

12V

RefOut

13

RefOut

13

Figure 21.

HOSCF
Pin 4

42/50

12V

Pin 13

Figure 24.

8

R0

12V

RefOut

13

TDA9113

Figure 25.

HPLL1F

Figure 26.

HPosF

Figure 28.

9

HFly

12V

12

Figure 29.

RefOut

12V

10

BComp

14

Figure 27.

HDyCor

11

12V

12V

Figure 30.

BRegIn

12V

15

43/50

TDA9113

Figure 31.

BISense

16

Figure 32.

18 VEHTIn

17

HEHTIn

12V

12V

Figure 34.

VAGCCap

Figure 35.

12V

22

VCap

12V

20

Figure 33.

VOSCF

44/50

19

12V

Pin 13

Figure 36.

23

VOut

12V

TDA9113

Figure 37.

24 EWOut

32 VDyCor

Figure 38.

XRay

Figure 40.

12V

30 SCL
31SDA

12V

25

Figure 39.

26 HOut

28 BOut

12V

45/50

TDA9113

11 - PACKAGE MECHANICAL DATA

32 PINS - PLASTIC SHRINK

E

E1

A2

B1B

D

32 17

1

Dimensions

A 3.556 3.759 5.080 0.140 0.148 0.200
A1 0.508 0.020
A2 3.048 3.556 4.572 0.120 0.140 0.180

B 0.356 0.457 0.584 0.014 0.018 0.023
B1 0.762 1.016 1.397 0.030 0.040 0.055

C .203 0.254 0.356 0.008 0.010 0.014

D 27.43 27.94 28.45 1.080 1.100 1.120

E 9.906 10.41 11.05 0.390 0.410 0.435
E1 7.620 8.890 9.398 0.300 0.350 0.370

e 1.778 0.070
eA 10.16 0.400
eB 12.70 0.500

L 2.540 3.048 3.810 0.100 0.120 0.150

Min. Typ. Max. Min. Typ. Max.

Millimeters Inches

e

16

A

A1

L

Stand-off

C

eA
eB

46/50

12 - GLOSSARY

AC Alternate Current
ACK ACKnowledge bit of I2C-bus transfer
AGC Automatic Gain Control
COMP COMParator
CRT Cathode Ray Tube
DC Direct Current
EHT Extra High Voltage
EW East-West
H/W HardWare
HOT Horizontal Output Transistor
I2CInter-Integrated Circuit
IIC Inter-Integrated Circuit
MCU Micro-Controller Unit
NAND Negated AND (logic operation)
NPN Negative-Positive-Negative
OSC OSCillator
PLL Phase-Locked Loop
PNP Positive-Negative-Positive
REF REFerence
RS, R-S Reset-Set
S/W SoftWare
TTL Transistor Transistor Logic
VCO Voltage-Controlled Oscillator

TDA9113

47/50

TDA9113

Revision follow-up

PRELIMINARY DATA

06/ 2000 version 3.1 Document creation

07/2000 version 3.2

BLOCK DIAGRAM : addition of Hsize under E/W correction
QUICK REFERENCE DATA : addition of parrallelogram
I2C BUS CONTROL REGISTER MAP : subaddress 08 - 0:no tracking
Few corrections in text

08/ 2000 version 3.4

Figure 16 and Figure 17: corrections
ABSOLUTE MAXIMUM RATINGS : definition of VESD
Miscellaneous : X-ray detection instead of protection
Horizontal moiré cancellation: new sentence about frequency range

09/ 2000 version 3.6

HMOIRE (pin) becomes HMOIRE (field register), VDyCorPol (register) becomes VDy­CorPol (pin)

Note 37 : text modified

01/ 2001 version 3.6

QUICK REFERENCE DATA : new value for autosync frequency 4.28 (4.5 previously)

April 2001 version 3.6

EW drive section : VEW-BCor parameter: sadOF instead of sadOE

DATASHEET

April 2001 version 4.0 Valid for cut 2 (“G” at the end of second line of package marking)

ELECTRICAL PARAMETERS AND OPERATING CONDITIONS :
new values for : VRefO, VHPosF and VTopHPLL2C, VVOB, VThBlsCurr and VBReg,
VThrXRay

VPos changed to VHPosF + new values

page 15 TBD mentions deleted

May 2001 version 4.1 Valid for cut 2.2 (“H” at the end of second line of package marking)

Miscellaneous : value for Horizontal Moire Canceller changed: 0.02% instead of 0.04%
previously

July 2001 version 4.2
page31 Section 9.4.1 -. right column”The higher its value,...” ---> ”The lower its value”
page 33 Section 9.5 -.”...at the vertical middle...” ---> ”...in the vertical middle...”
page 14 Section 6.6 - E/W drive: parameter ”∆VEW/VEW.∆VHO”, added [fmax].and changed typ.

value to +20

2

TDA9113

Note 32: added: “VEW[fmax] is the value at condition VHO>VHOThrfr”.
page 31 Section 9.4 - “stabilizing time” replaced by “stabilization time” (twice)
page 18 Section 6.9 - vertical moiré canceller: max. values moved to typ.values

October 2001 version 4.3
page 35 Section 9.5 - correction of figure 13 “EWOut output waveform”

TDA9113

Information furnished isbelieved tobe accurate and reliable. However, STMicroelectronics assumes no respon­sibility for the consequences of use of such information nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change with­out notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics
products are not authorized for use as critical components in life support devices or systems without the ex­press written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2001 STMicroelectronics - All Rights Reserved.

Purchase of I
components in an I

2

C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights touse these

2

C system is granted provided that the system conforms tothe I2C Standard Specification as defined

by Philips.

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