SGS Thomson Microelectronics TDA9103 Datasheet

TDA9103

USER’S MANUAL

DEMONSTRATION BOARD

April 1995

I - INTRODUCTION

Thisdemonstationboardhasbeenrealizedinorder
to provide the user with a complete and simple
evaluation tool of the deflectionprocessorfor mul­tisyncmonitor TDA9103 (andpossiblyof the verti­cal boosterTDA8172).

This demoboard is in fact the core of a monitor
chassis.To have a completemonitor,wehave only
to add a command board (microprocessor + key­board), a linepowerboard (EHT, S-correction,de­flection transistor), a SMPS board and a video
board.

BesidestheTDA9103describedinaseparatedata
sheet,we willfind on thisboard thefollowing func­tions :

- Averticaldeflectioncircuitbasedon theTDA8172

- Aclass A power amplifier for the EWcorrection

- Aline transistor driver stage

- A DC/DC converter for the scanning supply (so
calledB+)

- A separable analog command board with poten­tiometersfor thegeneration (from anexternal 5V
powersupply) of the 11control voltagesrequired
bytheTDA9103and withasimulatorofhorizontal
flyback

In this way, the user will be able in a first step to
evaluate the performances of the IC under clean
conditions. In a second step, after having broken
the printed board, he will be able to connect the
demoboardto a monitorand to usethecommands
of an existing monitor and thus use his own soft­ware todrive the TDA9103.

II - TECHNICALINFORMATIONS
II.1 - Board Description
II.1.1 - MainBoard

II.1.1.1 - Core
The boardisbuiltaroundtheICTDA9103and very

few externalcomponents :

- C2-R32 Line oscillator.

- C3-C7-R31 Filterof the line PLL.

- C4 Verticaloscillator.

- C5 Memory capacitor forthe

verticalAGC.

- C26-R68-R67 Gain of the error amplifier

of DC/DC converter.

- D4-R80-C48 Circuitfor improvement
behaviourwith Composite Sync
(SeeSection II.1.1.8. These
componentsmay be omitted
if such standardsare not used).

II.1.1.2 - 0/5V to 2/6VInterface
The IC TDA9103 uses two 8V internal voltage

referencesV

REF

(fortheverticalpart) and H

REF

(for
the horizontalone).So,theanalogvoltagerange is
2to6V.

As a microprocessor usually delivers a voltagein
the range 0-5V, we must implement an interface
with 3 resistors for each of the 10 adjustments
required by the TDA9103(R1 to R30).

Thefour circuitsforhorizontal(respvertical)adjust­ments are connectedto H

REF

(respV

REF

).

II.1.1.3- EW Amplifier
The parabola generated by the TDA9103 for the

EW correction must be amplified in order to drive
the diodemodulator.

Thisfunction is performed by theclass Aamplifier
Q3-Q4-Q9.A DC voltageis added tothe parabola
to achievethe horizontalsize adjustments.

Fora proper working,this amplifiermustbe loaded
(100Ω connectedto Vp = 24V).

II.1.1.4 - Horizontal Line Driver Stage
TheHOUTpulsedeliveredbytheTDA9103isused

to turn on a MOS transistor via a push pull stage.
The pulse is transmittedto the line transistor by a
drivertransformer.When Q2 isON (HOUT at high
level), the linetransistoris off.

You will find in annexe the specification of the
transformerused on this board. Two key points of
the specmust be highlighted :

- Leakageinductor ≤2µH (this data set the turnoff

time of the power transistor).

- Parasiticcapacitor< 50pf(a toohighvalue leads

to a transmission of a commutationspike to the
secondarysideandthechassisground andcould
makesometroublein the workingofthechassis).

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This transformeris made with a EIcore fromTDK
(ref. PC30 EI22/19/6-Z) whose specifications are
given in annexe.

For a proper working,this stage is to be loaded by
the followingcircuit(Figure 1).

II.1.1.5 - VerticalDeflectionStage
This isthe typical applicationofthe TDA8172 used

with a symetrical power supply ±12V in order to
avoid usinga highvalueelectrolytic capacitor.

This stage is designed for driving a yoke with the
following characteristics :

-L≈ 5mH

-R≈8Ω
II.1.1.6 - B+Converter

The B+ is generated by a booststep up converter
working incurrent mode.

The powerMOS Q6startsto conduct at thebegin­ning of the line sawtooth and it stops when the
voltageon R61(imageof draincurrentof the MOS)
becomes greater than the output voltage of the
error amplifier(inside the TDA9103). This voltage
is setby the regulation loop.

The board offers two possibilites for choosing the
regulationloop :

- Localregulation of B+: SW2 in position1.

- EHTregulation : SW2 in position 2 and feedback
input on J25.

This secondmodewillbe choosen when the board
is connectedon a multi-frequencymonitor.

The main featuresof this converterare the follow­ing :

- Frequencyrange 31kHz- 64kHz

- Outputvoltage 70V - 140V

- Input voltage 45V ±X%

- Outputpower 35Wmax.

Youwill find in annexe A the specifications of the
inductanceT2 used in this converter.

BYW98-100

1

Ω

47Ω

BUH715

9103-62.EPS

Figure1

II.1.1.7 - OtherFunctions

X ray protectionTP2

A level higher than 1.6V (TTL level) in this point
inhibitsall theoutputs (Horizontal,Vertical, SMPS,
Blanking).

Blankingoutput TP6

This output is activated in case of Xray detection,
loss of line synchro, power failure (V

CC

, ...) or

activationof theON/OFF switch.

ON/OFFswitch

When the voltage on pin 2 is smallerthan 1V,the
HOUT,VOUT and SMPSoutputsare disabledand
the BLANKoutput TP6is activated.

CS switchJ17

Theses4 outputsaresequentiallyswitchedon(low
level)if the inputhorizontal frequencygoesthrough
the following thresholds : 34kHz, 41kHz, 51kHz,
61kHz.

These frequencies are given for a free running
frequencyequal to 27kHz.

The CS switchoutputs could be used to switchthe
S correctioncapacitors if necessary.

Frame Blanking TP11

This output is in fact the flyback generator of the
vertical booster TDA8172. It could be used for
blankingthe videosignalduring the frame retrace.

II.1.1.8 - Operationwith CompositeSync
When using these standards, the board is not

driven directlyby the sync signals but by a circuit
(microproc or something else) who generatesthe
Hsyncand Vsync signals.Unfortunately,theHsync
signalpresentgenerallya jumpof phaseduringthe
Vsync time. This phase jump disturb the line PLL
anditcantakealongtimetorecovertherightphase
at theend of the vertical sync.

So,wehavetoinhibitthelinePLLduringthevertical
returntime (and a littlelater).

Thisis doneby thediode D4and the time constant
R80-C48.WhenVsyncisatHIGH level,the voltage
on pin 35 is highand the linePLLis inhibited.

The consequenceis that the board will not work
with standardshaving an inverted polarity vertical
synchro. In this case, D4 must be removed or
Vsync must be inverted in order to have a correct
workingof the line PLL.

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

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II.1.2 - ControlBoard

This board, required by the first and quick evalu­ation, is intended to be separated from the main
board forthe connectionto a monitor whenwe will
use thecommand from the microprocessor.

On this board, we find 11 potentiometers for the
generationof thecontrolvoltagesin therange0-5V
(use ofan externalpowersupply).

In addition, thanks to a small circuit with a
monostablegeneratingapseudohorizontalflyback
pulse ; the demoboard can be used without con­nectingit to a monitor.

ThewidthandthedelayofthepseudoHflybackcan
be adjustedby the trimmers P1 and P2.

II.2 - Instructionsfor Use
II.2.1 - StandAlone Mode

This demoboardis able to work aloneby using :

- The analogcommand fromthe control board,

- Apseudo Hflyback from the controlboard,

- AlocalB+ regulation.

The value of B+ is preset to 100V. This value can
be be changedby changingthe divider R65-R66.

- Configure the two jumper as following (see Fig­ure 2) :

• SW1 position1,

• SW2 position1.

- Connectthe following power supply:

• +12V betweenJ3 and J19,

• -12V between J21 and J19,

• +5V betweenJC4 and JC26,

• 45V 2Abetween J12 and J20,

• 24V between J24 and J20 (these power sup-

pliesare onlyrequiredforSMPS,LINEDRIVER
and EW amplifiertesting).

- Connect the following loads on all the outputs
(Figure4).

- ConnectHsync and Vsyncfrom the pattern gen­erator on J2 and J5 respectively.

II.2.2 - Connectionto aMonitor Chassis

II.2.2.1- AnalogCommand andB+ Regulation
ConfigureSW1in position2and connecttheboard

to thechassis(see Figure5).
II.2.2.2- AnalogCommand andEHT Regulation

ConfigureSW2 in position 2, connecttheboard as
before and connect the HVFEED inputs with a
shieldedcable (see Figure3).

Thevalue ofR79issuitableforgetting25kVapprox
high voltage value with a standard EHT trans­former.

When the EHV regulation loop is acting correctly,
the voltage at J25 is ≈5V (depending on the B+
adjust (pin 39) voltage.It’s easy to calculate the
valueof R79 if theequivalentresistanceReq of the

bleederis differentof theone used to develop this
demoboard:

R79 ≈

5 ⋅ Req

EHV

II.2.2.3 - Commands from Microprocessor
Breakoff the control boardand connecttheappro-

priateoutputs of themicro on theconnectorsJ1B,
J2Band J3B.

C35

C45

S1

R71

R67 R73

C36

C33

C2

R32

C9

R31

C34

IC1

R26

R68

TP8

TP9

R72

SW1

SW2

C1

SW2

1
2

SW1

1
2

9103-63.EPS

Figure2

FOCUS

SCREEN

EHT
TRANSFORMER

J25

TP10

R79

75k

Ω

DEMOBOARD

9103-66.EPS

Figure3

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

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