MIXER FOR 1ST FM IF 10.7MHz WITH
PROGRAMMABLE IF TANK ADJUST FOR FM
AND AM UPCONVERSION
■ 2 PROGRAMMABLE IF-GAIN STAGES
ND
■ 2
MIXER FOR 2ND IF 450KHz
■ INTERNAL IF BANDPASS FILTER WITH
THREE BANDWIDTHS CONTROLLED BY ISS
(INCLUDING WEATHER BAND)
■ FULLY INTEGR ATED FM-DEMODULATOR
AM-PART
■ WIDE AND NARROW AGC GENERATION
■ PREAMPLIFIER AND MIXER FOR 1ST IF
10.7MHZ,
AM UPCONVERSION
ND
■ 2
MIXER FOR 2ND IF 450KHZ
■ INTEGRATED AM-DEMODULATOR
■ OUTPUT FOR AM-STEREO-DECODER
ORDERING NUMBER: TDA7511
MULTIPATH
■ QUALITY DETECTION INFORMATIONS AS
ANALOG SIGNALS EXT ERN AL AVAIL ABLE
■ ISS (INTELLIGENT SELECTIVITY SYSTEM)
FOR CANCELLATION OF ADJACENT
CHANNEL AND NOISE INFLUENCES
■ ADJACENT CHANNEL MUTE
■ FULLY ELECTR ONIC ALIGNMENT
■ ALL FUNCTIONS I
■ ISS FILTE R STATUS I NFORMATION I
READABLE
TQFP64
2
C-BUS CONTROLLED
2
C-BUS
ADDITIONAL FEATURES
■ HIGH PERFORMANCE FAST PLL FOR RDS-
SYSTEM
■ IF COUNTER FOR FM AND AM
UPCONVERSION WITH SEARCH STOP
SIGNAL
■ QUALITY DETECTOR FOR LEVEL,
DEVIATION, ADJACENT CHANNEL AND
November 2001
DESCRIPTION
The TDA 7511 is a high performance tuner circuit for
AM/FM car radio. It contains mixers, IF amplifiers, demodulators for AM and FM, quality detection, ISS filter and PLL synthesizer with IF counter on a single
chip.
Use of BICMOS technology allows the implementation of several tuning function s and a mini mum of external components.
1AMMIX1IN2AM Input2 Mixer1
2AMMIX1IN1AM Input1 Mixer1 Reference
3AMRFAGCINInput AM RF AGC
4AMRFAGCOUTOutput AM RF AGC
5FMPINDRFM PIN Diode Driver Output
6FMMOSDRFM MOS Driver Output
7FMMIX1IN1FM Input1 Mixer1
8GNDRFRF Ground
9FMMIX1IN2FM Input2 Mixer1
10TV1Tuning Voltage 1
11FMRFAGCINFM RF AGC Input
12TV2Tuning Voltage 2
13ADJCHIdent. Adjacent Channel Output
14FSUUnweighted Fieldstrength Output
VREF2
LPOUT
LPAM
LPFM
LPHC
3/41
TDA7511
PIN DESCRIPTION
N°PinFunction
15ISSTCTime Constant for ISS Filter Switch
16VCCVCOVCO Supply
17GNDVCOVCO Ground
18VCOBVCO Input Base
19VCOEVCO Output Emitter
20DEVTCDeviatio n Detector Time Cons tant
21XTALDXtal Oscillator to MOS Drain
22XTALGXtal Oscillator to MOS Gate
23GNDVCC3VCC3 Ground
24SSTOPSe arch Stop Outpu t
25SDA
26SCL
27VCC3Supply Tuning Voltage
28LPOUTOp Amp Output to PLL Loop Filters
29VREF2Voltage Reference for PLL Op Amp
30LPAMOp Amp Input to PLL Loop Filters AM
31LPFMOp Amp Input to PLL Loop Filters FM
32LPHCHigh Current PLL Loop Filter Input
33GNDVCC1Digital Ground
34AMST/MPAM Stereo Out / Ident. Multipath Output
35FSWWeighted Fieldstrength Output
36VCC1Digital Supply
37MPX/AFAMMPX Output / AM AF Output
38AMIFREFReference Voltage AM IF Amp
39AMIFBPFAM IF Filter
40AMAGC2TCAM AGC2 Time Constant
41AMDETCAM Detector Capacitor
42MU TETCSoftmute Time Constant
43AMIF2INInput AM IF2
44FMDEMCFM Demodulator Reference
45FMMIX2IN2FM IF1 MIX2 Input1
46FMMIX2IN1FM IF1 MIX2 Input2
47GNDDEMGround FM Demodulator
48VREF1Reference 5V
49GNDVCC2Analog Ground
50FMAMP2OUTFM IF1 Amplifier2 Output
= 10.25MHz, in test or application circuit, (unless otherwise noted, V
inRF
antenna input).
SymbolParameterTest ConditionMin. Typ.Max.Unit
AGain6dB
C
C
C
61-62
AM Mixer2 (450kHz)
R
IP33rd order intercept point140
∆A
C
C
Min. capacitance stepIF1T0.55pF
min
Max. capacitanceIF1T8.25pF
max
IF1T2pF
Input impedanceDependent on application 5
IN
k
dB
FN oise figure12dB
AMax. gainMixer2 tank output15dB
Gain control range20dB
Min. cap stepIF2T1.6pF
min
Max. capIF2T24pF
max
Ω
µV
C
55-56
ELECTRICAL CHARACTERISTICS
IF2T2pF
SymbolParameterTest ConditionMin. Typ.Max.Unit
ADDITIONAL PARAMETERS
Outputs of Tuning Voltage(TV1, TV2)
V
R
Output voltageTVR,TVO1VCC3-1VV
OUT
Output impedance20
OUT
Xtal Reference Oscillator
f
C
C
∆f/f
∆f/f
2
I
C-Bus interface
f
SCL
Reference frequencyC
LO
Min. cap stepXTAL0.6pF
Step
Max. capXTAL19.4pF
max
Freq. deviation versus VCC2
= 15pF10.25MHz
Load
∆V
CC2
= 1V
1.5ppm/V
Freq. deviation versus temp-40°C < T < +85°C0.2ppm/K
Clock frequency400kHz
Ω
k
12/41
V
Input low voltage1V
IL
TDA7511
ELECTRICAL CHARACTERISTICS
(continued)
SymbolParameterTest ConditionMin. Typ.Max.Unit
V
I
V
Input high voltage3V
IH
Input current-55
IN
Output voltage SDA acknowledge IO = 1.6mA0.4V
O
Loop Filter Input/Output
-I
I
V
V
I
OUT
I
OUT
Input leakage currentVIN = GND, PD
IN
Input leakage currentVIN = VREF1
IN
Output voltage LowI
OL
Output voltage HighI
OH
Output current, sinkV
Output current, sourceV
PD
= Tristate
OUT
= -0.2mA0.050.5V
OUT
= 0.2mAVCC3
OUT
= 1V to V
OUT
= 1V to V
OUT
= Tristate-0.10.1
OUT
-0.10.1
VCC3
-0.5
-1V10mA
CC3
CC3
-1V
-10
-0.05
Voltage Controlled Oscillator (VCO)
f
VCOmin
f
VCOmax
Minimum VCO frequency
Maximum VCO frequency200MHz
50
µA
µA
µ
A
V
mA
MHz
C/NCarrier to Noise1KHz offset85dBc
SSTOP Output
V
V
V
Output voltage low
24
Output voltage high
24
IF counter sensitivityAntenna input6
46
= -20µA
I
24
= 20µA
I
24
3V
0.2V
dB
µV
13/41
TDA7511
1FUNCTIONAL DESCRIPTION
1.1FM Section
1.2Mixer1, AGC and 1.IF
Mixer1 is a wide dynamic range stage with low noise and large input signal performance. The mixer1 tank can
be adjusted by software (IF1T). The AGC operates on different sensitivities and bandwidths (FMAGC) in order
to improve the input sensitivity and dynamic range (keying AGC). The output signals of AGC are controlled voltage and current for preamplifier and pr estage pin diode attenuator.
Two 10.7MHz programmable amplifier s (IFG1, IFG2) correct the IF ceramic inser tion loss and the cos tumer level plan application.
1.3Mixer2, Limiter and Demodulator
In this 2. mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multi-stage limiter generates
signals for the complete integrated demodulator without external tank. MPX output DC offset compensation is
possible by software (DEM).
(look at Figure 4)
1.4Quality Detection and ISS
(look at Figure 2)
Fieldstrength
Parallel to mixer2 input a 10.7MHz limiter generates a signal for digital IF counter and a fieldstrength output signal. This internal unweighted fieldstrength is used for keying AGC, adjacent channel and multipath detection
and is available at PIN14 (FSU) after +6dB buffer stage. The behaviour of this output signal can be corrected
for DC offset (SL) and slope (SMSL). The internal generated unweighted fieldstrength is filtered at PIN35 and
used for softmute function and generation of ISS filter switching signal for weak input level (sm).
Adjacent Channel Detector
The input of the adjacent c hannel detecto r is AC c oupled from i nter nal unweighted fiel dstrength. A programmable highpass or bandpass (ACF) and amplifier ( ACG) as well as rectifier determines the influences. This voltage
is compared with adjustable comparator1 thresholds (ACWTH, ACNTH). The output signal of this comparator
generates a DC level at PIN15 by programmable time constant. Time control (TISS) for a present adjacent channel is made by charge and discharge current after comparator1 in an external capacitance. The charge current
is fixed and the discharge current is controlled by I
2
C Bus. This level produces digital signals (ac, ac+) in an
additional comparator4. The adjacent channel information is available as analog output signal after rectifier and
+8dB output buffer.
Multipath Detector
The input of the multipath detector is AC coupled from internal unwe ighted fieldstrength. A programm able bandpass (MPF) and amplifier (MPG) as well as rectifier determines the influences. This voltage is compared with
an adjustable comparator2 thresholds (MPTH). The output signal of this comparator2 is used for the "Milano"
effect. In this case the adjac ent channel detection is switched off. The "Milano" effect is selectable by I
2
C Bus
(MPOFF). The multipath information is available as analog output signal after rectifier and +8dB output buffer.
450kHz IF Narrow Bandpass Filter (ISS filter)
The device gets an additional second IF narrow bandpass filter for suppression nois e and adjacent channel signal influences. This narrow filter has three switchable bandwidthes, narrow range of 80kHz, mid range of
120kHz and 30KHz for weather band information. Without ISS filter the IF bandwidth (wide range) is defined
only by ceramic filter chain. The filter is switched in after mixer2 before 450kHz limiter stage. The centre frequency and matching to the demodulator center frequency can be fine adjusted (AISS) by software..
Deviation Detector
In order to avoid distortion in audio output signal the narrow ISS filter is switched OFF for present overdeviation.
14/41
TDA7511
Hence the demodulator output signal is detected. A lowpass filtering and peak rectifier generates a signal that
is defined by software controll ed current (TDEV) in an external capac itance. This value is c ompared with a programmable comparator3 thresholds (DWTH, DTH) and generates two digital signals (dev, dev+).
ISS Switch Logic
All digital signals coming fr om adjacent channel de tector, devia tion detector and softmute are ac ting vi a sw itching matrix on ISS filter switch. The IF bandpass switch mode is controlled by software (ISSON, ISS30, IS S80,
ISSCTL). The switch ON of the IF bandpass is also available by manipulation of the voltage at PIN15. Two application modes are available (APPM). The conditions are described in table 37.
1.5Soft Mute Control
The external fieldst reng th signal at PIN 35 is the ref erenc e for mute con trol. The startpoi nt, mute dep th and slop e
are progr ammable (SMTH, SM D, SLOPE) in a w ide range . The time c onstant i s define d by exter nal c apacit ance.
Additional adjacent channel mute function is supported. A highpass filter with -3dB threshold frequency of
100kHz, am plifie r and peak re ctifie r gen erates an adjac ent nois e sign al from MPX outp ut with th e same time co nstant for sof tmute. Thi s value is compare d with compar ator5 thres holds (ACM). For present stron g adjacent cha nnel the MPX signal is attenuated typical 6dB.
1.6AM Section
The upconversion mixer1 is combined with a gain control circuit 1 sensing three input signals, narrow band information at PIN 39, upconversion signal at PIN 58 and wide band information at PIN 3.This gain control circuit
gives two output signals. The first one is a current for pin diode attenuator and the second one is a voltage for
preamplifier. It is possible to put in a separate narrow bandpass filter before mixer2 at PIN 58. The intervention
point for first AGC (AMAGC) is programmable by software.
The oscillator frequency for mixer1 is generated by dividing the FM V CO frequency (AMD).
In mixer2 the IF1 is downconverted into the IF2 450kHz. Before the output signal reaches the 450kHz tank an
attenuator for IF gain control 2 is passed. Mixer1 and mixer2 tanks are software controlled adjustable
(IF1T, IF2T).
After filtering by ceramic filter a 450kHz amplifier with a gain control 3 is included. The gain control 2 and 3 are
the second AGC and programmable too by s oftware (DAGC). In or der to av oid an osc illation i n intervention point
it is important to know that the D AGC thr eshold has to be smaller than AMAGC! .
The demodulator is a peak detector. A further time constant with capacitor at pin40 produces a DC AGC reference voltage depe ndent on input signal. The ti me c onstant i s s witchable by ratio of 30. This is necessary fo r the
station search function. The switching is software controlled (AMSEEK).
An internal comparator compares the AGC voltage with a programmable reference (AMSS). Consequently it is
possible to generate a seekstop impulse over a defined range.
A separate output is available for AMIF stereo or a permanent seek stop signal(SSTSEL).
1.7PLL and IF Counter Section
PLL Frequency Synthesizer Block
This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required
to build a complete PLL system for FM and AM upconversion. For auto search stop operation an IF counter
system is available.
The counter works in a two stages configurati on. The first stage is a swallow counter with a two modulus (32/33)
precounter. The second stage is an 11-bit programmable counter.
The circuit receives the sca ling factor s for the progr ammabl e counters and the val ues of the r eference frequencies via an I
2
C-Bus interface.The reference frequency is gener ated by an adjustable internal (XTA L) oscillator
followed by the reference divider. The reference and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are swi tching the programmable cur rent s ources. The l oop filter i ntegrates
15/41
TDA7511
their currents to a DC voltage.
The values of the current sour ces are programmable by 6 bits also r eceived via the I
To minimize the noise induced by the digital part of the system, a special guard area is implemented.
The loop gain can be set for different conditions by setting the current values of the chargepump generator.
Frequency Generation for Phase Comparison
The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-bit divider(A). The
5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit divider(B). The 11-bit PC register (PC5 to PC15) controls this divider
Dividing range:
f
= (R+1) x f
OSC
f
= [33 x A + (B + 1 - A) x 32] x f
VCO
f
= (32 x B + A + 32) x f
VCO
REF
REF
REF
Important: For correct operation: A ≤ 32; B ≥ A
Three State Phase Comparator
The phase comparator generates a phase error signal according to phase difference between f
This phase error signal drives the charge pump current generator.
Charge Pump Current Generator
This system generators signed pulses of current. The phase error signal decides the duration and polarity of
those pulses. The current absolute values are programmable by A register for high current and B register for
low current.
2
C Bus (A, B, CURRH, LPF).
and f
SYN
REF
.
Inlock Detector
Switching the chargepump in low current mode can be done either via software or automatically by the inlock
detector, by setting bit LDENA to "1".
After reaching a phase difference of 10 - 40nsec and a delay of some times 1/f
in low current mode. A new PLL divider alternation by I
2
C-Bus will switch the chargepump in the high current
, the chargepump is forced
REF
mode.
Few programmable phase errors (D0, D1) are available for inlock detection
The count of detected inlock informations, to release the inlock signal is adjustable (D2, D3), to avoid a switching
to low current during a frequency jump.
Low Noise CMOS Op -a mp
An internal voltage divider at pi n VREF2 connects the positi ve input of th e low n oise op-amp. The c harge pump
output connects the negative input. This inter nal ampli fier in cooperation w ith external components ca n provide
an active filter. The negative input is switchable to three input pins, to increase the flexibility in application. This
feature allows two separate active filters for different applications.
A logical "0" in the LP F register activates PIN LPFM, otherwise PI N LPAM is active. Whil e the high curre nt mode
is activated LPHC is switched on.
IF Counter Block
The input signal for FM and AM upconv ersion is the same 10.7MHz IF level after limiter . The grade of i ntegration
is adjustable by eight different measuring cycle times. The tolerance of the accepted count value is adjustable,
to reach an optimum compromise for search speed and precision of the evaluation.
For the FM range the center frequency of the measured count value is adjustable in 32 steps, to get the possibility of fitting the IF-filter tole rance. In the AM upconversion range an IF frequency of 10.689MHz to 10.720MHz
with 1kHz steps is available.
16/41
TDA7511
The IF -Counter Mode
The IF counter works in 2 modes controlled by IFCM register.
Sampling Timer
A sampling timer to generate the gate signal for the main counter is build wi th a 14-bit programmable counter
(IRC). In FM mode a 6.25kHz, in AM mode a 1kHz basically signal is generated. This is followed by an asynchronous divider to generate several sampling times.
Intermediate Frequency Main Counter
This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have
the possibility for an adjust to the frequency of the IF-filter . The counter length is automatic adjusted to the chosen sampling time and the counter mode (FM, A M -UPC).
At the start the counter will be loaded with a defined value which is an equivalent to the divider value
(t
SamplexfIF
If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main
counter is changing its state from 0h to 1FFFFFh.
This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The frequency range inside which a successful count result is adjustable by the EW bits.
).
= (IRC + 1) / f
t
TIM
OSC
t
= (CF + 1697) / f
CNT
= (CF + 10689) / f
t
CNT
IF
IF
FM mode
AM up conversion mode
Counter result succeeded:
t
TIM
t
TIM
≥ t
≤ t
CNT
CNT
- t
+ t
ERR
ERR
Counter result failed:
> t
t
TIM
t
TIM
t
TIM
t
CNT
t
ERR
+ t
CNT
ERR
< t
- t
CNT
ERR
= IF timer cycle time
= IF counter cycle time
= discrimination window (controlled by the EW registers)
The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA).
Adjustment of the Measurement Sequence Time
The precision of the measurements is adjustabl e by contr oll ing the disc rimination window. This is adjustabl e by
programming the control registers EW0 to EW2.
The measurement time per cycle is adjustable by setting the Register IFS0 - IFS2.
Adjust of the Frequency Value
The center frequency of the discrimination window is adjustable by the control register CF0 to CF4.
17/41
TDA7511
1.8I2C-Bus Interface
The TDA 7511 supports the I2C-Bus protocol. This protocol defines any device that sends data onto the bus as
a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and
device being controlled is the slave. The master will always initiate data transfer and provide the clock to transmit or receive operations.
Data Transition
Data transition on the SDA line must only occur w hen the clock SCL is LOW. S DA transitions while SCL is HIGH
will be interpreted as START or STOP condition.
Start Condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level.
This "START" condition must precede any command and initiate a data transfer onto the bus. The TDA 7511
continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this
condition has not been met.
Stop Condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable H IGH
level. This condition terminates the communication between the devices and forces the bus-interface of the TDA
7511 into the initial condition.
Acknowledge
Indicates a successful data transfer . The transmitter will release the bus after sending 8 bits of data. During the
9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits of data.
Data Transfer
During data transfer the TDA 7511 samples the SDA line on the leading edge of the SCL clock. Therefore, for
proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.
Device Addressing
To start the communication between two devices, the bus master must initiate a start instructi on sequence, followed by an eight bit word corresponding to the address of the device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA 7511 device type is fixed as "110001".
The next significant b it is used to addres s a partic ular devic e of the previ ous defin ed type co nnected to the bus.
The state of the hardw ired PI N 41 defines the s tate of this addr ess bit . So up to two devices could be connected
on the same bus. When PIN 41 is connected to VCC2 the address bit “1” is selected. In this case the AM part
doesn’t work. Otherwise the address bit “0” is selected (FM and AM is working). Therefor a double FM tuner
concept is possible.
The last bit of the start instruction defines the type of operation to be performed:
- When set to "1", a read operation is selected
- When set to "0", a write operation is selected
The TDA 7511 connected to the bus will compare their own hardwired address with the slave address being
transmitted, after detecting a START co ndition. After this comparis on, the TD A 7511 wi ll generate an "acknow ledge" on the SDA line and will do either a read or a write operation according to the state of R/W bit.
18/41
TDA7511
Write Operation
Following a START condition the master s ends a s lave addres s w ord with the R/W bit set to "0". The TDA 7511
will generate an "acknowledge" after this firs t transmission and will wait for a second word (the word addr ess
field). This 8-bit address field provides an access to any of the 32 internal addresses. Upon receipt of the word
address the TDA 7511 slave device will respond with an "acknowledge". At this time, all the following words
transmitted to the TDA 7511 will be considered as Data. The internal address will be automatically in cremented.
After each word receipt the TDA 7511 will answer with an "acknowledge".
Read Operation
IF the master sends a slave address word with the R/W bit set to "1", the TDA 7511 will transit one 8-bit data
word. This data word includes the following informations:
bit0 (ISS filter, 1 = ON, 0 = OFF)
bit1 (ISS filter bandwidth, 1 = 80kHz, 0 = 120kHz)
bit2 (MPOUT,1 = multipath present, 0 = no multipath)
bit3 (1 = P LL is locked in , 0 = PLL is locked out).
bit4 (fieldstrength indicator, 1 = lower as softmute threshold, 0 = higher as softmute threshold)
bit5 (adjacent channel indicator, 1 = adjacent channel present, 0 = no adjacent channel)
bit6 (deviation indicator, 1 = strong overdeviation present, 0 = no strong overdeviation)
bit7 (deviation indicator, 1 = over deviation present, 0 = no overdeviation)
TEST26-----DIV2DIV1DIV0
TEST MODE127OUT7OUT6OUT5OUT4OUT3OUT2OUT1OUT0
TEST MODE228--TINMPTINACOUT11OUT10OUT9OUT8
2.2Con t rol Re gi s te r Fun c tion
Table 2.
Register NameFunction
ACharge pump high current
ACFAdjacent channel filter select
ACGAdjacent channel filter gain
ACMThreshold for startpoint adjacent channel mute
ACNTHAdjacent channel narrow band threshold
ACWTHAd jacen t channel wide band thres hold
AISSISS filter fine adjust
20/41
Table 2. (continued)
Register NameFunction
AMAGCAM wide band AGC threshold
AMDAM prescaler
AMONAM -FM switch
AMSEEKSwitch time constant for AM seek
AMSSAM seek stop threshold
AMSTAM stereo select
APPMApplication mode quality detection
BCharge pump low current
CFCenter frequency IF counter
CLKSEPClock separation (only for testing)
CURRHSet current high charge pump
DInlock phase error and delay time for lock detector
DAGCAM narrow band AGC threshold
DEMDemodulator offset
DEMOFFDemodulator clock “OFF” (only for testing)
DNBDemodulator noise blanking
DIVDivider ratio for reference frequency (only for testing)
DTHDeviation detector threshold for ISS filter “OFF”
DWTHDeviation detector threshold for ISS filter narrow/wide
EWFrequency error window IF counter
FMAGCFM AGC threshold
IF1TFM/AM mixer1 tank adjust
IF2TAM mixer2 tank adjust
IFCMIF counter mode
IFENAIF counter enable
IFGIF1 amplifier gain (10.7MHz)
IFSIF counter sampling time
IRCIF reference counter
ISSCOFFISS filter clock “OFF” (only for testing)
ISSCTLISS filter control
ISSINTest input for ISS filter
ISSONISS filter “ON”
ISS30ISS filter 30KHz weather band
ISS80ISS filter narrow/mid switch
LDENALock detector enable
LPFLoop filter input select
MENASoftmute enable
MPACAdjacent channel control by multipath
MPOFFMultipath control “OFF”
MPFMultipath filter frequency
MPGMultipath filter gain
MPTHMultipath threshold
OUTTest output (only for testing)
TDA7511
21/41
TDA7511
Table 2. (continued)
Register NameFunction
PCCounter for PLL (VCO frequency)
RCReference counter PLL
RESReservation
SLS meter slider threshold
SLOPESoftmute slope select
SMCTHSoftmute capacitor threshold for ISS “ON”
SMDSoftmute depth threshold
SMSLS mete r slope
SMTHSoftmute startpoint threshold
SSTSELSearch stop select for continuous signal
TEST3Testing PLL/IFC (only for testing)
TESTOUTSwitch FSW output to TEST output (only for testing)
TESTINSwitch FSU input to TEST input (only for testing)
TDEVTime constant for deviation detector
TINACTest input adjacent channel (only for testing)
TINMPTest input multipath(only for testing)
TISSTime constant for ISS filter “ON”/”OFF”
TVRTuning voltage for prestage proportional referred to PLL
TVOTuning voltage offset for prestage
XTALXtal frequency adjust
450LOFF450kHz limiter “OFF” (only for testing)
01Application mode 2
0Multipath eliminates ac
1Multipath eliminates ac and ac+
LSB
0Multipath control “ON”
1Multipath control “OFF”
0MP bandpass frequency 19KHz
1MP bandpass frequency 31KHz
Function
Function
29/41
TDA7511
Addr 16 Quality Deviation Detection
Table 19.
MSB
LSB
d7 d6 d5 d4 d3 d2 d1 d0
000
001
010
011
charge current 34
charge current 32
charge current 30
charge current 28
µΑ, discharge current 6µΑ
µΑ, discharge current 8µΑ
µΑ, discharge current 10µΑ
µΑ, discharge current 12µΑ
----
111
charge current 20
µΑ, discharge current 20µΑ
00DEV threshold for ISS narrow/wide 30kHz
01DEV threshold for ISS narrow/wide 45kHz
10DEV threshold for ISS narrow/wide 60kHz
11DEV threshold for ISS narrow/wide 75kHz
00DEV threshold for ISS filter “OFF” ratio 1
01DEV threshold for ISS filter “OFF” ratio 1.3
10DEV threshold for ISS filter “OFF” ratio 1.4
11DEV threshold for ISS filter “OFF” ratio 1.5
0has to be 0
Addr 17 Quality ISS Filter
Table 20.
MSB
d7 d6 d5 d4 d3 d2 d1 d0
0Switch ISS filter 120kHz
1Switch ISS filter 80kHz
000
001
010
011
----
111
00ISS filter fine adjust -20kHz
01ISS filter fine adjust -10kHz
10ISS filter fine adjust 0kHz
11ISS filter fine adjust +10kHz
LSB
0ISS filter control “ON”
1ISS filter control “OFF”
0Switch ISS filter “OFF”
1Switch ISS filter “ON”
0Multipath information available FM
1AM stereo output available
Function
0Normal AGC time constant
1Short time constant for AM seek stop
Narrow band AGC threshold 74.4dB
Narrow band AGC threshold 78.8dB
Narrow band AGC threshold 80.0dB
Narrow band AGC threshold 80.7dB
Narrow band AGC threshold 53.2dB
Narrow band AGC threshold 77.1dB
Narrow band AGC threshold 78.5dB
Narrow band AGC threshold 79.4dB
Narrow band AGC threshold 42.7dB
Narrow band AGC threshold 65.8dB
Narrow band AGC threshold 77.6dB
Narrow band AGC threshold 78.5dB
Narrow band AGC threshold 32.6dB
Narrow band AGC threshold 55.0dB
Narrow band AGC threshold 73.3dB
Narrow band AGC threshold 77.6dB
00Function “OFF”
01Mute depth threshold for ISS filter “ON” 2dB
10Mute depth threshold for ISS filter “ON” 1dB
11Mute depth threshold for ISS filter “ON” 0.2dB
LSB
Function
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Addr 21 S oftmute Cont rol 2
Table 24.
TDA7511
MSB
LSB
d7 d6 d5 d4 d3 d2 d1 d0
0000
0001
0010
0100
Startpoint mute 0 in application 3dB
Startpoint mute 1 in application 4dB
Startpoint mute 2 in application 5dB
Startpoint mute 3 in application 6dB
acNo adjacent channelAdjacent channel present
ac+No strong adjacent channelAdjacent channel higher as ac
smFieldstrength higher as softmute thresholdFieldstrength lower as softmute threshold
devDeviation lower as threshold DWTHDeviation higher as threshold DWTH
dev+Deviation lower as threshold DTH*DWTHDeviation higher as threshold DTH*DWTH
intonISS filter off by logic (wide)ISS filter on by logic
int80ISS filter 120kHz (mid)ISS filter 80kHz (narrow)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent r i ght s of STMi croelectr oni cs. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroel ectronics.
The ST logo is a registered trademark of STMicroelectronics
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