SGS Thomson Microelectronics TDA7502 Datasheet
IN-CAR REMOTE AMPLIFIER DSP
24-Bit Fixed-point DSP core delivering up to
50 MIPS
2x512 x 24BitofRAMforX andYdatamemory.
1536 x 24 Bitof RAMfor Program.
1536 x 24 Bit of Additional RAM memory us-
able fordelay or program
SerialAudio Interface.
DebugPort.
Control Interface for external GPIOs, Inter-
rupts,and RESET.
SPI andI
nal micro andDSP. Both master and slaveoperating modes.
PLL Clock Oscillator
5V-tolerant3V I/O interface
DESCRIPTION
This device is a high-performance,fully programmable DSP, suitable for a wide range of applications and particularly for Audio and Sound Processing. It contains a 24-bit 50 MIPS DSP core,
several interfaces for control and data, plus a
BLOCK DIAGRAM
2
C for communicationbetween exter-
TDA7502
PRODUCT PREVIEW
TQFP44
(10 x 10)
configurablePLL.
The computational power and the memory con-
figuration make this device particularly suitable
for in car equalisation. This device will offer the
best trade-off between performance and cost
when coupled with the TDA7531, or other devices of the same family.A library of sound processing functions is available for this device; some
of these functions are: parametric equaliser,
cross over filters, acoustic delay, dynamic compression, Vol/Bass/Treble/Fader, active equalisation, StereoSpatial Enhancement.
SDI0 SDI1 SDI2 SDO0 SDO1 SDO2 VDD3 GND3 SCANEN TESTEN
LRCLKT
SCKT
LRCLKR
SCKR
SCL
SDA
SS
SCK
MISO
MOSI
GPIO3
GPIO4
GPIO5
DBCK/GPIO1
DBIN/GPIO2
DBRQN/GPIO3 DBRQ VDD1 GND1 VDD2 GND2 XTO XTI CLKOUT
April 1999
This is preliminary information on a new product foreseen to be developed. Details are subject tochange withoutnotice.
Serial
Audio
Interface
I2C
Interface
SPI
Interface
GPIO
Debug
interface
XAB
XDB
YAB
YDB
PAB
ORPHEUS
24bit DSP
CORE
PDB
512 x 24
X-RAM
512 x 24
Y-RAM
3072 x 24
P/Delay-RAM
128 x 24
BOOT-ROM
PLL
oscillator
VDD4
GND4
VDD5
GND5
VDD6
GND6
RESET
INT
PVCC
PGND
1/8
TDA7502
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DDC
V
DDP
V
I,VIN
T
op
T
stg
PIN CONNECTION
Core DC Supply voltage 4.6 V
Pads DC Supply voltage 4.6 V
Digital or analog input voltage -0.5 to (VDDP +0.5) V
Operative temperature range -40 to 85 °C
Storage temperature range (plastic) -55 to 150 °C
SDI0
SDA
3435363738394041424344
SDI1
SCL
33
32
31
30
29
28
27
26
25
24
23
SDI2
SCKT
LRCKT
GND5
VDD5
SDO2
SDO1
SDO0
GND4
VDD4
SCKR
LRCKR
VDD1
GND1
INT
SCANEN
TESTEN
DBRQN
DBOUT
VDD2
GND2
DBCK
DBIN
GND6
VDD6
XTI
XTO
MISO
MOSISSSCK
VDD3
RESET
GND3
GPIO3
GPIO5
GPIO4
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
PVCC
PGND
CLKOUT
THERMAL DATA
Symbol Parameter Value Unit
th j-amb Thermal Resistance Junction to Ambient 50 °C/W
R
PIN DESCRIPTION
N. Name Type
1 VDD1 I – 3.3V core supply.
2 GND1 I – Core ground.
3 INT I/O – External interrupt line (Input/Output). When this line is asserted low, the
4 SCANEN I – SCAN Enable When active with TESTEN also active, controls the
5 TESTEN I – Test Enable. When active, puts the chip into test mode and muxes the
6 DBRQN I – Debug Port Request Input. Means of entering the Debug mode of
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Reset
Status (1)
Function
DSP may be interrupted. Acts as IRQA line of DSP core.
shifting of the internal scan chains.
XTI clock to all flip-flops. When SCANEN is also active, the scan chain
shifting
operation.
PIN DESCRIPTION(continued)
TDA7502
N. Name Type
Reset
Status
Function
7 DBOUT/GPIO2 I/O I The serial data output for the Debug Port. Can also be used as a GPIO.
8 VDD2 I – 3.3V core supply.
9 GND2 I – Core ground.
10 DBCK/GPIO0 I/O I Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port
is provided when an input. When an output, provides information about
the chip status. Can also be used as GPIO
11 DBIN/GPIO1 I/O I Debug Port Serial Input/Chip Status 0. The serial data input for the
Debug Port is provided when an input. When an output, provides
information about the chip status. Can also be used as GPIO.
12 CLKOUT O – Output Clock.
13 PGND I – PLL Clock Ground Input. Ground connection for oscillator circuit.
14 PVCC I – PLL Clock Power Supply. Positive supply for PLL Clock Oscillator.
15 XTO O High Crystal Oscillator Output. Crystal Oscillator output drive.
16 XTI I – Crystal Oscillator Input. External Clock Input or crystal connection.
17 RESET I/O I System Reset. A logic low level applied to RESET input initializes DSPs.
During Debug Mode if this pin is pulled low in while the DBRQN line is
pulled low then the DSP pointed to by the DBSEL pin will be reset.
18 VDD3 I – 3.3V Supply.
19 GND3 I – Ground.
20 SDI0 I – SDI0 is a stereodigital audio data inputpin channel0.
21 SDI1 I – SDI1 is a stereodigital audio data inputpin channel1.
22 SDI2 I – SDI2 is a stereodigital audio data inputpin channel2.
23 SCKR I/O – SAI receive bit clock. Master or slave.
24 LRCKR I/O – Left-Right clock for SAI Receiver. Master or slave.
25 VDD4 I – 3.3V Supply.
26 GND4 I – Ground.
27 SDO0 O High SDO0isa stereodigital audiodataoutputpinchannel 0.
28 SDO1 O High SDO1isa stereodigital audiodataoutputpinchannel 1.
29 SDO2 O High SDO2isa stereodigital audiodatapin channel2.
30 VDD5 GND – 3.3V Supply.
31 GND5 I – Ground.
32 LRCKT I/O – SAI transmit left/right clock. Master or slave.
33 SCKT I/O – SAI transmit bit clock. Master or slave.
34 SCL I/O – Clock line for I
35 SDA I/O – Data line for I
2
C bus. Schmitt trigger input.
2
C bus. Schmitt trigger input.
36 SCK I – Bit clock for SPI control interface.
37 SS I – Slave select input pin for SPI control interface.
38 MOSI I/O I Serial Data Output for SPI type serial port when in SPI Master Mode and
Serial Data Input when in SPI Slave Mode.
39 MISO I/O I Serial Data Input for SPI style serial port when in SPI Master Mode and
Serial Data Output when inSPI Slave Mode.
40 VDD6 GND – 3.3V Supply.
41 GND6 I – Ground.
42 GPIO3 I/O – This pin is dedicated as general I/O.
43 GPIO4 I/O – This pin is dedicated as general I/O.
44 GPIO5 I/O – This pin is dedicated as general I/O.
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