Input Resistance37.55062.5K
Clipping LevelTHD = 0.3%22.5Vrms
Min. Attenuation-101dB
Max. Attenuation3131.532dB
Step Resolution-10.51dB
DC StepsAdjacent att. step-303mV
SRS EFFECT CONTROL
C
range1
Sstep1Center/SpaceStep Resolution1dB
Center/Space Control Range-310dB
Ω
3/11
TDA7467
ELECTRICALCHARACTERISTICS (continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
AUDIO OUTPUTS
N
N
o(Off)
o(srs)
Output Noise(OFF)Output muted, Flat
BW (20Hz to 20KHz)
Output noise(srs)
BW (20Hz to 20KHz)50µVrms
4
5
Surround Sound
dDistortionA
S
C
V
ocl
R
out
V
out
Channel Separation90dB
Clipping Leveld = 0.3%22.5Vrms
Output Resistance30Ω
DC Voltage Level3.8V
=0;Vin= 1Vrms0.010.1%
V
BUS INPUTS
V
il
V
ih
I
in
V
o
Input Low Voltage1V
Input High Voltage3V
Input Current-55µA
Output VoltageSDA
IO=1.6mA0.4V
Acknowledge
SRS SURROUNDSOUND MATRIX
CENTERSRS Control Range-310dB
Step
SPACESRS Space Control Range-310dB
Step
P
ERSP1
P
ERSP2
L+RL+ R SRS CurveSPACE= MUTE,CENTER=0dB
L, RL, R SRS CurveSPACE= MUTE,CENTER=0dB
Center Step Resolution1dB
C
Space Step Resolution1dB
S
Perspective 1Input Signal of 125Hz
12dB
SPACE= 0dB,CENTER= MUTE
R
= GND; Li
in
Perspective 2Input Signal of 2.15KHz
n →ROUT
0dB
SPACE= 0dB,CENTER= MUTE
R
= GND; Li
in
n →ROUT
-8.5dB
R
in = GND; Lin → ROUT
-13.4dB
R
= GND; Li
in
Lin= GND; Rin→ R
n →LOUT
OUT
Vrms
µ
µVrms
4/11
TDA7467
I2C BUSINTERFACE
Data transmission from microprocessor to the
TDA7467 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of theclock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCLis HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an ac-
2
Figure 3: DataValidityon theI
CBUS
knowledgebit. The MSBis transferredfirst.
Acknowledge
The master (µP)puts a resistiveHIGHlevelon the
SDA line during the acknowledgeclock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
duringthisclockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmissionwithout Acknowledge
Avoiding to detect the acknowledge of the audioprocessor,the µP can use a simpler transmission:
simply it waits one clock without checking the
slaveacknowledging,and sends the new data.
This approach of course is less protected from
misworking.
Figure 4: TimingDiagram of I
2
Figure 5: Acknowledgeon the I
CBUS
2
CBUS
5/11
TDA7467
SOFTWARESPECIFICATION
InterfaceProtocol
The interfaceprotocol comprises:
A startcondition (S)
CHIP ADDRESSSUBADDRESSDATA1to DATAn
MSBLSBMSBLSBMSBLSB
S100000A0ACKBDATAACKDATAACKP
A chip addressbyte
A subaddressbytes
A sequenceof data (N byte + achnowledge)
A stopcondition (P)
ACK = Achnowledge
S = Start
P = Stop
B = Auto Increment
EXAMPLES
No IncrementalBus
The TDA7467receives a start condition,the correctchip address, a subaddresswith the MSB= 0 (no incrementalbus), N-data (all these data concernthe subaddressselected), a stopcondition.
CHIP ADDRESSSUBADDRESSDATA
MSBLSBMSBLSBMSBLSB
S 100 000 A 0 ACK 0 X X X X X D1 D0 ACKDATAACK P
Incremental Bus
The TDA7467receives a start condition,the correctchip address, a subaddresswith the MSB= 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from ”1XXXX1XX”to ”1XXX1111”of DATAare ignored.
The DATA 1 concerns the subaddress sent, and the DATA 2 concerns the subaddress plus one sent in
the loop etc. and at the end, it receivesthe stop condition.
CHIP ADDRESSSUBADDRESSDATA 1to DATAn
MSBLSBMSBLSBMSBLSB
S 100 000 A 0 ACK 1 X X X X X D1 D0 ACKDATAACK P
6/11
TDA7467
DATA BYTES(Address= 80(HEX) ifADDR pin is floating,82(HEX) if ADDRpin is connectedto V
FUNCTIONSELECTION:
X = INDIFFERENT 0, 1
SPACE & CENTER ATTENUATION = 0dB
POWERON RESET
-31dB
∼
INPUTMUTE
MODEOFF (FIX)
SPACE ATTENUATIONMUTE (MIN)
CENTER ATTENUATIONMUTR (MIN)
8/11
DIP28 PACKAGE MECHANICAL DATA
TDA7467
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
a10.630.025
b0.450.018
b10.230.310.0090.012
b21.270.050
D37.341.470
E15.216.680.5980.657
e2.540.100
e333.021.300
F14.10.555
I4.4450.175
L3.30.130
mminch
9/11
TDA7467
SO28 PACKAGEMECHANICAL DATA
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
A2.650.104
a10.10.30.0040.012
b0.350.490.0140.019
b10.230.320.0090.013
C0.50.020
c145°(typ.)
D17.718.10.6970.713
E1010.650.3940.419
e1.270.050
e316.510.65
F7.47.60.2910.299
L0.41.270.0160.050
mminch
S8°(max.)
10/11
TDA7467
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patentrights of SGS-THOMSONMicroelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized foruseas criticalcomponentsin lifesupport devices or systems withoutexpress
written approval of SGS-THOMSON Microelectronics.