SGS Thomson Microelectronics TDA7440D Datasheet



DIGITALLY CONTROLLED AUDIO PROCESSOR

INPUTMULTIPLEXER

- 4 STEREO INPUTS

- SELECTABLEINPUT GAIN FOR OPTIMAL
ADAPTATIONTO DIFFERENT SOURCES

ONE STEREO OUTPUT
TREBLE AND BASS CONTROL IN 2.0dB

STEPS
VOLUMECONTROL IN 1.0dB STEPS
TWOSPEAKERATTENUATORS:

- TWOINDEPENDENTSPEAKERCONTROL
IN 1.0dBSTEPS FOR BALANCEFACILITY

- INDEPENDENT MUTE FUNCTION

ALL FUNCTION ARE PROGRAMMABLE VIA
SERIALBUS

DESCRIPTION

The TDA7440D is a volume tone (bass and
treble) balance (Left/Right) processor for quality
audio applicationsin Hi-Fisystems.

TDA7440D

TONE CONTROL

SO28

ORDERING NUMBER: TDA7440D

Selectable input gain is provided. Control of all
the functionsis accomplished by serial bus.

The AC signal setting is obtained by resistor net­works and switches combined with operational
amplifiers.

Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained

BLOCK DIAGRAM

4

L-IN1

5

L-IN2

6

L-IN3

7

L-IN4

3

R-IN1

2

R-IN2

1

R-IN3

28

R-IN4

100K

100K

100K

100K

100K

100K

100K

100K

INPUT

G

0/30dB

2dB STEP

G

MULTIPLEXER

+ GAIN

MUXOUTL INL

8 9 18 14 15

VOLUME

VOLUME

10 11 19 12 13 23

MUXOUTR INR TREBLE(R)

TREBLE(L)

TREBLE

I2CBUS DECODER + LATCHES

TREBLE

BIN(L)

R

BASS

BASS

R

BOUT(L)

B

B

BOUT(R)BIN(R)

SPKR

LEFT

SPKR

RIGHT

V

SUPPLY

REF

ATT

ATT

CREF

27

21
22
20

26

24
25

LOUT

SCL
SDA
DIG_GND

ROUT

V

S

AGND

D98AU883

April 1999

1/16

TDA7440D

PIN CONNECTION (Top view)

R_IN3
R_IN2
R_IN1

L_IN1
L_IN2 V
L_IN3
L_IN4

MUXOUTL

IN(L)

MUXOUT(R)

IN(R)

BIN(R)

BOUT(R)

BIN(L)

1
2
3
4
5
6
7
8
9
10
11
12
13
14

D98AU884

28
27
26
25
24

22
21
20
19
18
17
16
15

R_IN4
LOUT
ROUT
AGND

S

CREF23
SDA
SCL
DIG-GND
TREBLE(R)
TREBLE(L)
N.C.
N.C.
BOUT(L)

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

S

T

amb

T

stg

Operating Supply Voltage 10.5 V
Operating Ambient Temperature -10 to 85
Storage Temperature Range -55 to 150 °C

C

°

THERMAL DATA

Symbol Parameter Value Unit

R

thj-pin

Thermal ResistanceJunction-pins 85 °C/W

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

V

S

V

CL

THD Total Harmonic DistortionV = 1Vrms f = 1KHz 0.01 0.1 %

S/N Signal to Noise Ratio V

S

C

2/16

Supply Voltage 6 9 10.2 V
Max. input signal handling 2 Vrms

= 1Vrms (mode = OFF) 106 dB

out

Channel Separation f = 1KHz 90 dB
Input Gain in (2dBstep) 0 30 dB
Volume Control (1dB step) -47 0 dB
Treble Control (2dB step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control 1dB step -79 0 dB
Mute Attenuation 100 dB

TDA7440D

ELECTRICALCHARACTERISTICS

R

= 600Ω, all controls flat (G = 0dB), unless otherwise specified)

G

(refer to the test circuit T

=25°C,VS= 9V,RL= 10KΩ,

amb

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

V

S

I

S

SVR Ripple Rejection 60 90 dB

Supply Voltage 6 9 10.2 V
Supply Current 4 7 10 mA

INPUT STAGE

G

G

R

V

S

inmin

inman

G

IN

CL

IN

step

Input Resistance 70 100 130 KΩ
Clipping Level THD = 0.3% 2 2.5 Vrms
Input Separation The selected input is grounded

80 100 dB

through a 2.2µ capacitor
Minimum Input Gain -1 0 1 dB
Maximum Input Gain 29 30 31 dB
Step Resolution 1.5 2 2.5 dB

VOLUMECONTROL

C

RANGE

A

A

V

A

R

VMAX

STEP

E

A

E

T

DC

mute

Input Resistance 20 33 50 KΩ

i

Control Range 45 47 49 dB
Max. Attenuation 45 47 49 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV= 0 to-24dB -1.0 0 1.0 dB

A

= -24 to -47dB -1.5 0 1.5 dB

V

Tracking Error AV= 0 to-24dB 0 1 dB

A

= -24 to -47dB 0 2 dB

V

DC Step adjacent attenuation steps

from 0dB to A

V

max

0

0.5

Mute Attenuation 80 100 dB

3mV

BASS CONTROL(1)

Gb Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB

B

STEP

R

B

Step Resolution 1 2 3 dB
Internal Feedback Resistance 33 44 55 KΩ

TREBLECONTROL(1)

Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB

T

STEP

Step Resolution 1 2 3 dB

SPEAKERATTENUATORS

C

RANGE

S

STEP

E

A

V

DC

A

mute

NOTE1:

1) The device is functionally goodat Vs = 5V. a step down,on Vs, to 4V does’t reset thedevice.

2) BASS and TREBLE response: The centerfrequency and the response quality can be chosen by the external circuitry.

Control Range 70 76 82 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV= 0 to-20dB -1.5 0 1.5 dB

= -20 to -56dB -2 0 2 dB

A

V

DC Step adjacent attenuation steps 0 3 mV
Mute Attenuation 80 100 dB

mV

3/16

TDA7440D

ELECTRICALCHARACTERISTICS

(continued.)

Symbol Parameter Test Condition Min. Typ. Max. Unit

AUDIOOUTPUTS

VCLIP Clipping Level d = 0.3% 2.1 2.6 VRMS

R

L

R

O

DC DC Voltage Level 3.5 3.8 4.1 V

V

Output Load Resistance 2 KΩ
Output Impedance 10 30 50

GENERAL

E

NO

E

t

S/N Signal to Noise Ratio All gains 0dB; V

S

C

d Distortion A

Output Noise All gains = 0dB;

515µV

BW = 20Hz to 20KHz flat

Total Tracking Error AV= 0to -24dB 0 1 dB

A

= -24to -47dB 0 2 dB

V

O

=1V

; 95 106 dB

RMS

Channel Separation Left/Right 80 100 dB

=0;VI=1V

V

; 0.01 0.08 %

RMS

BUS INPUT

V

IL

V

IH

I

IN

V

O

Input Low Voltage 1V
Input High Voltage 3 V
Input Current VIN= 0.4V -5 0 5 µA
Output Voltage SDA

IO= 1.6mA 0.4 0.8 V

Acknowledge

Ω

TEST CIRCUIT

0.47µF

0.47µF

0.47µF

0.47µF

0.47µF

0.47µF

0.47µF

0.47µF

L-IN1

L-IN2

L-IN3

L-IN4

R-IN1

R-IN2

R-IN3

R-IN4

2.2µF

4

100K

5

100K

6

100K

7

100K

3

100K

2

100K

1

100K

28

100K

INPUT

MUXOUTL INL

G

0/30dB

2dB STEP

G

MULTIPLEXER

+ GAIN

MUXOUTR INR TREBLE(R)

8 9 18 14 15

10 11 19 12 13 23

2.2µF

5.6nF

TREBLE(L)

VOLUME

VOLUME

TREBLE

I2CBUS DECODER +LATCHES

TREBLE

5.6K

100nF 100nF

BIN(L)

R

B

BASS

BASS

R

B

100nF 100nF

5.6K

BOUT(L)

SPKR

LEFT

SPKR

RIGHT

SUPPLY

BOUT(R)BIN(R)

27

ATT

ATT

V

REF

CREF

10µF5.6nF

21
22
20

26

24
25

LOUT

SCL
SDA
DIG_GND

ROUT

V

S

AGND

D98AU885

4/16

TDA7440D

APPLICATIONSUGGESTIONS

The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute) for
the first one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution.
The very high resolution allows the implementation
of systems freefromanynoisyacousticaleffect.
The TDA7440D audioprocessorprovides 3 bands
tones control.

Bass Stage

Several filter types can be implemented, connect­ing external components to the BassIN and OUT
pins.

The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-

Figure 1.

Ri internal

OUTIN

R

2

D95AU313

C

2

C

1

ternal and R2,C1,C2 external) the centre fre­quency Fc, the gain Av at max. boost and the fil­ter Q factorare computedas follows:

=

F

C

⋅ π⋅√

2

R2 C2 + R2 C1 + RiC1

=

A

V

R2 C1 + R2 C2

√

R1⋅R2⋅C1⋅C2

Q =

R2 C1 + R2 C2

1

R1⋅R2⋅C1⋅C2

Viceversa, once Fc, Av, and Ri internal value are
fixed, the external componentsvalues will be:

C1

=

2 ⋅ π ⋅ F

R2 =

− 1

A

V

C

⋅ Ri⋅ Q

A

V

C2

− 1 − Q

2

2 ⋅ π ⋅ C1 ⋅ FC⋅ (AV− 1) ⋅Q

=

Q

A

V

2

⋅ C1

− 1 − Q

2

TrebleStage

The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25KΩ
typical) and an external capacitor connected be­tween treble pins andground

Typical responsesare reported in Figg. 10 to 13.

CREF

The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application
requiresfasterpower ON.

Figure 2:

THD vs. frequency

Figure3:

THDvs. R

LOAD

5/16

TDA7440D

Figure 4:

Figure 6:

Channelseparationvs. frequency

Trebleresponse

Figure5: Bassresponse

Ri= 44kΩ
C9 = C10 = 100nF (Bout,Bin)
R3 = 5.6kΩ

6/16

TDA7440D

2

C BUS INTERFACE

I
Data transmission from microprocessor to the

TDA7440D and vice versa takes place through
the 2 wires I

2

C BUS interface, consisting of the
two lines SDA and SCL (pull-up resistors to posi­tive supply voltage must be connected).

Data Validity

As shown in fig. 7, thedata on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.

Start and Stop Conditions

As shown in fig.8 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran­sition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred on the SDA line must con­tain 8 bits. Each byte must be followed by an ac-

Figure 7:

Data Validityon theI

2

CBUS

knowledgebit. The MSB is transferredfirst.

Acknowledge

The master (µP)puts a resistiveHIGHlevel on the
SDA line during the acknowledge clock pulse (see
fig. 9). The peripheral (audio processor) that ac­knowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.

The audio processor which has been addressed
has to generate an acknowledge after the recep­tion of each byte, otherwise the SDAline remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen­erate the STOP information in order to abort the
transfer.

Transmissionwithout Acknowledge

Avoiding to detect the acknowledge of the audio
processor,the µP canuse a simplertransmission:
simply it waits one clock without checking the
slaveacknowledging,and sends the new data.

This approach of course is less protected from
misworking.

Figure 8:

TimingDiagram of I

2

Figure 9: Acknowledgeon the I

CBUS

2

CBUS

7/16

TDA7440D

SOFTWARESPECIFICATION

InterfaceProtocol
The interface protocol comprises:

A start condition (S)

address
A subaddressbytes
A sequenceof data (N byte + acknowledge)
A stopcondition (P)

A chip address byte, containingthe TDA7440D

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU420

SUBADDRESS DATA1 to DATA n

X DATA

XXB

ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment

EXAMPLES
No IncrementalBus

correct chip address,a subaddresswith the B = 0
(no incremental bus), N-data (all these data con­cern the subaddressselected),a stop condition.

The TDA7440D receives a start condition, the

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU421

IncrementalBus

The TDA7440D receive a start conditions, the
correct chip address, a subaddresswith the B = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas

CHIP ADDRESS

MSB LSB MSB LSB MSB LSB

S10001000ACK ACK DATA ACK P

D96AU422

SUBADDRESS DATA

XD3

XX0 D2D1D0

SUBADDRESS from ”XXX1000” to ”XXX1111”of
DATAare ignored.
The DATA 1 concern the subaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.

SUBADDRESS DATA1 to DATA n

XD3

XX1 D2D1D0

8/16

POWERON RESET CONDITION

INPUT SELECTION IN2

INPUT GAIN 28dB

VOLUME MUTE

BASS 0dB

TREBLE 2dB

SPEAKER MUTE

DATA BYTES

Address = 88 HEX (ADDR:OPEN).
FUNCTIONSELECTION:First byte (subaddress)

TDA7440D

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

XXXB00 00INPUT SELECT
XXXB00 01INPUT GAIN
XXXB00 10VOLUME
XXXB00 11BASS
XXXB01 00NOTUSED
XXXB01 01TREBLE
XXXB01 10SPEAKER ATTENUATE ”R”
XXXB01 11SPEAKER ATTENUATE ”L”

B = 1: INCREMENTAL BUSACTIVE
B = 0: NO INCREMENTALBUS
X = DON’T CARE

SUBADDRESS

In Incremental Bus Mode, the ”not used” function must be addressed in any case. For example to re­fresh ”Volume = 0dB” and Speaker_R = -40dB”,thefollowingbytes must be sent:

SUBADDRESS XXX10010

VOLUME DATA X0000000

BUS DATA XXXX1111

NOT USED DATA XXXX1111

TREBLE DATA XXXX1111

SPEAKER_R DATA X0000010

INPUT SELECTION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

XXXXXX00 IN4
XXXXXX01 IN3
XXXXXX10 IN2
XXXXXX11 IN1

INPUT MULTIPLEXER

9/16

TDA7440D

DATA BYTES (continued)

INPUT GAIN SELECTION

MSB LSB INPUT GAIN

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0000 0dB
0001 2dB
0010 4dB
0011 6dB
0100 8dB
0 1 0 1 10dB
0 1 1 0 12dB
0 1 1 1 14dB
1 0 0 0 16dB
1 0 0 1 18dB
1 0 1 0 20dB
1 0 1 1 22dB
1 1 0 0 24dB
1 1 0 1 26dB
1 1 1 0 28dB
1 1 1 1 30dB

GAIN = 0 to 30dB

VOLUMESELECTION

MSB LSB VOLUME

D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS

0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB

1 1 1 -7dB
0000 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
X 1 1 1 X X X MUTE

VOLUME = 0 to 47dB/MUTE

10/16

DATA BYTES (continued)

BASS SELECTION

MSB LSB BASS

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

TDA7440D

TREBLESELECTION

MSB LSB TREBLE

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB

11/16

TDA7440D

DATA BYTES (continued)

SPEAKERATTENUATE SELECTION

MSB LSB SPEAKER ATTENUATION

D7 D6 D5 D4 D3 D2 D1 D0 1dB

0 0 0 0dB

0 0 1 -1dB

0 1 0 -2dB

0 1 1 -3dB

1 0 0 -4dB

1 0 1 -5dB

1 1 0 -6dB

1 1 1 -7dB

0000 0dB
0 0 0 1 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
0 1 1 0 -48dB
0 1 1 1 -56dB
1 0 0 0 -64dB
1 0 0 1 -72dB
1 1 1 1 X X X MUTE

SPEAKER ATTENUATION = 0 to-79dB/MUTE

12/16

TDA7440D

PINS:

23

CREF

PINS:

1, 2, 3, 4, 5, 6, 7, 28

V

S

PINS:

26,27

V

S

V

V

S

S

20K

20K

D96AU430

PINS:

8, 10

ROUT
LOUT

D96AU434

V

S

20µA

24

V

S

IN

PINS:

19, 11

INL

INR

20µA

MIXOUT

20µA

100K

GND

V

REF

D96AU425

D96AU426

PINS: 12,14

V

S

20µA

V

S

20µA

33K

44K

BIN(L)

BIN(R)

D96AU428

V

D96AU427

REF

13/16

TDA7440D

PINS:

BOUT(L)

BOUT(R)

PINS:

13, 15

20

PINS:

18, 19

V

S

20µA

TREBLE(L)

TREBLE(R)

44K

D96AU429

PINS:

21

20µA

V

S

20µA

50K

D96AU433

20µA

SCL

D96AU424

SDA

D96AU423

14/16

TDA7440D

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050
S8°(max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO28

15/16

TDA7440D

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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publicationsupersedes and replaces all informationpreviously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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