3 STEREO/4STEREOINPUTS
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLEMIDDLE AND BASS CONTROL
THREE SURROUND MODES ARE AVAIL-
ABLE:
- MUSIC: 4 SELECTABLERESPONSES
- MOVIE ANDSIMULATED:
256SELECTABLE RESPONSES
FOURSPEAKERS ATTENUATORS:
- 4 INDEPENDENTSPEAKERSCONTROL
IN 1dB STEPSFORBALANCE FACILITY
- INDEPENDENTMUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
DESCRIPTION
The TDA7429 is volume tone (bass middle and
treble) balance (Left/Right) processors for quality
audio applicationsin TV and Hi-Fisystems.
TDA7429T
SDIP42TQFP44
ORDERING NUMBERS:
TDA7429STDA7429T
It reproduces surround sound by using programmable phase shifters and a signalmatrix. Control
of all the functionsis accomplishedby serial bus.
The AC signal setting is obtainedby resistor networks and switches combined with operational
amplifiers.
Thanks to theused BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
In-phase Gain (Movie)Movie mode, Effect Ctrl = -6dB
LR In-phase Gain Difference
(Movie)
Input signal of 1kHz, 1.4 V
Rin→ R
out,Lin
→ L
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
(Rin→ R
)–(Lin→ L
out
out
out
p-p
p-p
)
In-phase Gain (Music)Musicmode, Effect Ctrl = -6dB
LR In-phase Gain Difference
(Music)
Input signal of 1kHz, 1.4 V
R
(R
in
→
out
), (L
→
in
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
(Rin→ R
)-(Lin→ L
out
p-p
L
)
out
p-p
)
out
Simulated L Output 1SimulatedMode,EffectCtrl= -6dB
-101dB
-101dB
8dB
0dB
7dB
0dB
4.5dB
Input signal of 250Hz,
1.4 V
Simulated L Output 2SimulatedMode,EffectCtrl= -6dB
p-p,Rin
and Lin→ L
out
–4.0dB
Input signal of 1kHz,
1.4 V
Simulated L Output 3SimulatedMode, EffectCtrl= -6dB
p-p,Rin
and Lin→ L
out
7.0dB
Input signal of 3.6kHz,
1.4 V
p-p,Rin
and L
Simulated R Output 1SimulatedMode,EffectCtrl= -6dB
L
→
in
out
– 4.5dB
Input signal of 250Hz,
1.4 V
Simulated R Output 2SimulatedMode,EffectCtrl= -6dB
p-p,Rin
and Lin→R
out
3.8dB
Input signal of 1kHz,
1.4 V
Simulated R Output 3SimulatedMode,EffectCtrl= -6dB
p-p,Rin
and Lin→R
out
–20dB
Input signal of 3.6kHz,
1.4 V
p-p,Rin
and Lin→ R
out
Low Pass FilterResistance71013KΩ
High Pass FilterResistance426078KΩ
LP PinImpedance71013K
Ω
Ω
Ω
Ω
7/20
TDA7429S - TDA7429T
ELECTRICALCHARACTERISTICS (continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
SPEAKER & AUXATTENUATORS
C
range
S
STEP
E
A
V
DC
A
MUTE
R
VEA
AUDIOOUTPUTS
N
O(OFF)
N
O(MOV)
N
O(MUS)
N
O(MON)
dDistorsionAv = 0; V
S
C
V
OCL
R
OUT
V
OUT
MONITOROUTPUTS
dDistorsionAv = 0; Vin= 1Vrms0.010.1%
S
C
V
OCL
R
OUT
V
OUT
BUS INPUTS
V
IL
V
IH
I
IN
V
O
Control Range79dB
Step Resolution-0.511.5dB
Attenuation set errorAv = 0 to -20dB-1.501.5dB
Av = -20to -79dB-302dB
DC Stepsadjacent att. steps-303mV
Output Mute Condition+70100dB
Input Impedance213039KΩ
Output Noise(OFF)Output Mute, Flat
B
= 20Hz to 20KHz
W
Output Noise(Movie)Mode =Movie ,
B
= 20Hz to 20KHz
W
Output Noise(Music)Mode = Music ,
B
= 20Hz to 20KHz,
W
Output Noise(Simulated)Mode = Simulated,
B
= 20Hz to 20KHz
W
= 1Vrms0.010.1%
in
4
5
30µVrms
30mVrms
30µVrms
Channel Separation7090dB
Clipping Leveld = 0.3%22.5Vrms
Output Resistance255085Ω
DC Voltage Level3.8V
Channel Separation7090dB
Clipping Leveld = 0.3%22.5Vrms
Output Resistance255085Ω
DC Voltage Level4.5V
Input Low Voltage1V
Input High Voltage3V
Input Current-5+5
Output VoltageSDA
IO= 1.6mA0.4V
Acknowledge
µVrms
µVrms
A
µ
8/20
TDA7429S - TDA7429T
2
C BUS INTERFACE
I
Data transmission from microprocessor to the
TDA7429 and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of theclock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and StopConditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGHtransition of the SDAline while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
Figure 3:
Data Validityon theI
2
CBUS
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (µP)puts a resistiveHIGH level on the
SDA line during the acknowledgeclock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission withoutAcknowledge
Avoiding to detect the acknowledge of the audio-
processor,the µP can use a simplertransmission:
simply it waits one clock without checking the
slaveacknowledging, and sends the new data.
This approach of course is less protected from
misworking.
Figure 4:
TimingDiagram of I
2
Figure 5: Acknowledgeon theI
CBUS
2
CBUS
9/20
TDA7429S - TDA7429T
SOFTWARESPECIFICATION
InterfaceProtocol
The interfaceprotocol comprises:
A startcondition (S)
address
A subaddressbytes
A sequenceof data (N byte + achnowledge)
A stopcondition (P)
A chip address byte, containing the TDA7429
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU226A
SUBADDRESSDATA 1 to DATA n
BDATA
ACK = Achnowledge
S = Start
P = Stop
A = Address
B = Auto Increment
EXAMPLES
No IncrementalBus
The TDA7429 receives a start condition, the cor-
rect chipaddress, a subaddresswith the MSB = 0
(no incremental bus), N-datas (all these datas
concern the subaddress selected), a stop condition.
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU306
IncrementalBus
The TDA7429receive s a startcondition, the correct chip address,a subaddresswith theMSB = 1
(incremental bus): now it is in a loop condition
with an autoincrease of the subaddress whereas
CHIP ADDRESS
MSBLSBMSBLSBMSBLSB
S100000A0ACKACKDATAACKP
D95AU307
SUBADDRESSDATA
0D3
X X XD2 D1 D0
SUBADDRESS from ”1XXX1010” to ”1XXX1111”
of DATAare ignored.
The DATA 1 concern thesubaddress sent, and
the DATA 2 concern the subaddress sent plus
one in the loop etc, and at the end it receivers the
stop condition.
SUBADDRESSDATA 1 to DATA n
1D3
X X XD2 D1 D0
10/20
TDA7429S - TDA7429T
DATA BYTES
Address = 80(HEX)
FUNCTIONSELECTION:
The first byte (subaddress)
MSBLSBSUBADDRESS
D7D6D5D4D3D2D1D0
BXXX0000INPUT ATTENUATION
BXXX0001SURROUND & OUT & EFFECT
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