AM-FM RADIO FREQUENCY SYNTHESIZER
ON-CHIP REFERENCE OSCILLATOR AND
PROGRAMMABLEIF COUNTER
VHF INPUT AND PRECOUNTER FOR FREQUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)
HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORTWAVE BAND)
IN-LOCK DETECTOR FOR SEARCH/STOP
STATIONFUNCTION
STAND-BY MODE FOR LOW POWER CONSUMPTION
HIGH CURRENT SOURCE FOR 0.5ms
LOCK-INTIME
DIGITAL PORT EXTENSION WITH TWO
OUTPUTS FOR FLEXIBILITY IN APPLICATION
FULLY PROGRAMMABLEBYI
DESCRIPTION
The TDA7427 is a PLL frequency synthesizer
2
C BUS
TDA7427
AND IF COUNTER
DIP20
ORDERING NUMBERS:
with an additional IF counting system that performs all the functionsneeded in a complete PLL
radio tuning system for conventional and high
speedRDS tuners. The devicehas dedicatedoutputs for IN-LOCK detectionand Search/Stopstation.
SO20
TDA7427(DIP20)
TDA7427D (SO20)
BLOCK DIAGRAM
16
FM_IN
14
HFREF
17
AM_IN
5
OSCIN
OSCOUT
SCL
SDA
VDD2
VDD1
IF_AM
IF_FM
6
8
9
19
15
10
11
I2C BUS
INTERFACE
OSCILLATOR
SWITCH
AM/FM
REF
14 BIT
PROG
CNT
D95AU418B
PRECOUNTER
:32/33
SWITCH
SWM/DIR
PROG
16 BIT
CNT
TIMER CONTROL
11-21 BIT PROG CNT
5 BIT
SWITCH
SWM/DIR
11 BIT
PROG.
CNT
PROG
CNT
SSTOP
DETECTOR
PHASE
COMP
INLOCK
CHARGE
PUMP
TEST
LOGIC
PORT EXTENSION
712
DOUT3
SWITCH
LP1/LP2
+
POWER
RESET
13
DOUT1/INLOCK
2
LP_HC
3
LP_AM
1
LP_FM
-
ON
VDD1
20
4
18
LPOUT
VREF
GNDan/GNDdig
November 1999
1/21
TDA7427
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD1
V
DD2
P
tot
T
stg
T
amb
PIN CONNECTION
Supply Voltage - 0.3 to + 7 V
Supply Voltage - 0.3 to+ 11 V
Total PowerDissipation 300 mW
Storage Temperature - 55 to + 150
Ambient Temperature -40 to + 85
o
C
o
C
LP_FM
LP_HC
LP_AM
VREF
OSCIN
OSCOUT
DOUT3
SCL
SDA
1
2
3
4
5
6
7
8
9 SSTOP
19
18
17
16
15
14
13
12
LPOUT20
VDD2
GND
AM_IN
FM_IN
VDD1
HFREF
DOUT1/INLOCK
IF_AM 10 IF_FM11
D95AU373B
THERMAL DATA
Symbol Parameter DIP20 SO20 Unit
R
th j-amb
Thermal ResistanceJunction-Ambient max 100 150
o
C/W
2/21
TDA7427
PIN DESCRIPTION
PIN SYMBOL DESCRIPTION INPUT/OUTPUT
1
2
3
4
5
6
7
8
9
10
11
12
13*
13*
14
15
16
17
18
19
20
* Pin function is userdefined bysoftware
LP_FM FilterOPAMPinput, charge pump output (FM mode)
LP_HC
LP_AM FilterOPAMPinput, charge pump output (AM mode)
VREF OPAMPreferencevoltage
OSCIN Oscillator reference clock input
OSCOUT Oscillatoroutput
DOUT3 Opencollectoroutput
SCL I2C busclock input Input
SDA I2C busdata I/O Input/output
IF_AM IF counterinput (AMmode) Analoginput
IF_FM IF counter input (FM mode) Analog input
SSTOP IF counterresultoutput Output
DOUT1 Digital output Push-pulloutput
INLOCK Inlockdetectoroutput Output
HFREF HF reference
VDD1 Positivepowersupply 5V Supply
FM_IN HighfrequencyinputFM Analoginput
AM_IN High frequency input AM Analoginput
GND Analogdigitalground Supply
VDD2 Positivepowersupply 10V Supply
LPOUT Filter input, change pump output
(TDA7427/D)
FilterOPAMPinput, charge pump output (high current
mode)
3/21
TDA7427
ELECTRICAL CHARACTERISTICS
(T
amb
=25°C; V
DD1
= 5V; V
DD2
= 10V; f
OSC
= 4MHz; unless other-
wise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
DD1
V
DD2
I
DD1 Supply Current no output load 2 4 6 mA
I
DD2
I
DD1 STB
RF INPUT (AM_IN, FM_IN)
f
iAM
f
iFM Input Frequency FM Vi = 100mV
V
iMIN
V
iMAX
V
iMIN Min Input Voltage FM 70 to 120MHz range sinusoidal 30 mVrms
V
iMAX
Z
in Input Impedance FM input 3 4 5 KΩ
Z
in
IF COUNTER (IF_AM, IF_FM)
f
iAM Input Frequency range AM Vi = 100mV
f
iAM
V
iMIN Min Input Voltage AM IF pin f
V
iMIN
V
iMAX
V
iMAX Max Input Voltage FM IF pin f
Z
in
Z
in Input Inpedance AM IF pin 3 4 5 KΩ
BUS INTERFACE
T
f
SCL
t
AA SCL Low to SDA Data Valid 300 ns
t
buf
t
HD-START
t
LOW
t
HIGH
t
SU-SDA
t
HD-DATA Data Input Hold Time 1 µs
t
SU-DATA
t
R SDA & SCL Rise Time 1 µs
t
F
t
SU-STOP
t
DH DATA OUT Time 300 ns
Supply Voltage 4.5 5.0 5.5 V
Supply Voltage 9.0 11.0 V
Supply Current PLL locked 1 2 3 mA
Supply Current Standby mode 1
Input Frequency AM Vi = 100mV
sinusoidal 0.5 64 MHz
rms
sinusoidal 30 200 MHz
rms
Min Input Voltage AM 0.5 to 16MHz range sinusoidal 30 mVrms
Max Input Voltage AM 0.6 to 16MHz range sinusoidal 600 mVrms
Max Input Voltage FM 70 to 120MHz range sinusoidal 600 mVrms
Input Impedance AM input 3 4 5 KΩ
0.400 11 MHz
10 11 MHz
Input Frequency range FM Vi = 100mV
= 455kHz 30 mVrms
in
rms
rms
Min Input Voltage FM IF pin fin= 10.7MHz 30 mVrms
Max Input Voltage AM IF pin fin= 455kHz 600 mVrms
= 10.7MHz 600 mVrms
in
Input Inpedance FM IF pin 3 4 5 KΩ
Noise Suppression Time
j
50 ns
Constant on SCL, SDA Input
SCL Clock Frequency 400 kHz
Time the bus must be free for
4.7 µs
the new transmission
START Condition hold time 4.0
Clock Low Period 4.7 µs
Clock High Period 4.0 µs
Start Condition Setup Time 4.7
Data Input Setup Time 250 ns
SDA & SCL Full Time 0.3 µs
Stop Condition Setup Time 4.7
A
µ
s
µ
s
µ
s
µ
4/21
TDA7427
ELECTRICALCHARACTERISTICS
(continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
IL
V
IH Input High Voltage 3 V
I
IN
V
OUT
Input Low Voltage 1V
Input Current -5 +5 µA
Output Voltage SDA
IO= 1.6mA 0.15 0.4 V
acknowledge
OSCILLATOR
t
bu
C
in
C
OUT Internal Capacitance f
Z
in
V
in Input Voltage (for Slave Mode) f
Build Up Time f
Internal Capacitance 20 pF
Input Impedance f
= 4MHz 100 ms
out
= 4MHz 20 pF
osc
= 4MHz 100 KΩ
osc
= 4 to 13MHz (Sinus)
IN
300 V
DD
capacitance coupling
fin Max Input frequency (for Slave
VIN= 600mVPP(Sinus) 30 MHz
Mode)
LOOP FILTER
I
IN
I
IN
V
OL
V
OH
I
OUT Output Current Sink 10 30 mA
I
OUT
(LP_FM, LP_AM, LP_HC, LP_OUT)
Input Leakage Current (*) VIN= GND; PD
Input Leakage Current (*) VIN=V
Output Voltage Low I
Output Voltage High I
Output Current Source V
OUT
OUT
OUT
;PD
DD1
= -0.2mA 0 0.5 V
= 0.2mA 9.5 10 V
= 0.5to 9.5V 10 30 mA
= Tristate (1) -1 0.1 1 µA
out
= Tristate (1) -1 0.1 1
out
DOUT1/SSTOP (push-pull outputs)
V
OL Output Voltage Low I
V
OH
DOUT3
I
OUT
V
OL
I
OUT Output Current Sink V
1) PD = Phase Detector
(*) LP_FM and LP_HC pins only
Output Voltage High I
(open collector output)
Output leakage Current V
Output Voltage Low I
= -0.1mA 0.1 0.2 V
OUT
= 0.1mA V
OUT
= 10V -1 0.1 1 mA
OUT
= -1mA 0.2 0.5 V
OUT
= 0.5to 9.5V 3 5 mA
OUT
*0.2 4.9 V
DD1
mV
µ
pp
A
5/21
TDA7427
GENERAL DESCRIPTION
This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning systems. Only a VCO is required to build a complete
PLL system. For auto search/stopoperationan IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stageconfiguration.Thefirst stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit programmable counter.
For LW and MW application,a 16-bit programmable counteris available.
The circuit receivesthe scaling factors for the programmable counters and the values of the reference frequenciesviaa I
2
C bus interface.
The reference frequency is generated by an internal XTAL oscillator followed by the reference divider. The device can operate with XTAL oscillator between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free selectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bitsalso received via the I
2
C bus.
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the current valuesof thecharge/pumpgenerator.
IF COUNTER SYSTEM
Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuringcycletimes.
The tolerance of the accepted count value is adjustable, to reach an optimum compromise for
searchspeed and precisionof the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter tolerance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-conversion)with 1KHz steps is available.
PLL FREQUENCYSYNTHESIZER
InputAmplifiers
The signals applied on AM and FM inputs are amplified to get a logic level in order to drive the frequencydividers.
The typical input impedance for FM and AM inputs is 4kΩ.
Table 1. Address Organization
MSB LSB
FUNCTION SUBAD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PLL CHARGE PUMP
PLL COUNTER
PLL COUNTER
PLL REF COUNTER
PLL REF COUNTER
PLL LOCK DETECT
IFC REF COUNTER
IFC REF COUNTER
IFC CONTROL
IFC CONTROL
OSC ADJUST
PORT EXTENSION
00H LPIN1/2 CURRH B1 B0 A3 A2 A1 A0
01H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
02H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
03H RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
04H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8
05H LDENA INLOCK D3 D2 D1 D0 PM1 PM0
06H IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0
07H IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8
08H IFENA - - - - EW2 EW1 EW0
09H IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0
0AH - - - OSC4 OSC3 OSC2 OSC1 OSC0
0BH - - - - - DOUT3 - DOUT1
6/21
Figure 1. FM and AM (SW) operation (swallowmode)
REGISTER
OSC IN
AM IN
R0 ...R15
PREDIVIDER
:R
REGISTER
PC0 ...PC4
COUNTER
A
fref
fsyn
REGISTER
PC5 ... P15
PD
TDA7427
∆ϕ
TO CHARGE
PUMP
PRESCALER
M/M+1
FM IN
Table 2. Control Register Functions.
REGISTER NAME FUNCTION
PC
RC
IRC
IFCM
EW
IFENA
CF
IFS
PM
D
LPIN1/2
PLLSTOP
A
B
LDENA
CURRH
OSC
DOUT1
DOUT3
INLOCK
Programmable counter for VCO frequency
Reference counter PLL
Reference counter IF
IF counter mode selector
Frequency error window IF counter
Enable IFRC
Center frequency IF counter
Sampling time IF counter
Stby, FM, AM, AM swallow mode selector
Programmable delay and phase error for lock detector
Loop filter input select
PLL stop
Charge pump high current
Charge pump low current
Lock detector enable
Set current high
Oscillator adjust
Push pull output 5V
Open collector output
Lock detector output
COUNTER
:B
D95AU375A
7/21
TDA7427
Figure 2. AM direct mode operation for SW, MW and LW
PREDIVIDER
OSC IN
AM IN
FM IN
:R
REGISTER
RC0 ... RC15
REGISTER
PC0 ... PC15
PRESCALER
:C
DIVIDERFROM VCO FREQUENCY TO
REFERENCEFREQUENCY
This divider provides a low frequency f
SYN
which
phase is compared with the reference frequency
. It is controlled by the registers PC0 to PC4
f
REF
and PC5to PC15
OPERATINGMODES
Four operating modes are available fo PLL; they
are user programmable with the Mode PM registers (see table):
fref
fsyn
D95AU376A
PHASE
DETECTOR
TO
PUMP
∆ϕ
CHARGE
Dividingrange calculation:
f
=[33⋅A + (B + 1 - A) ⋅ 32 ] ⋅ f
VCO
f
= (32 ⋅ B + A + 32) ⋅ f
VCO
REF
REF
Important:forcorrectoperationA≤32,B≥A,with
AandB variablevaluesofthedividers).
- AM direct mode:
the AM signal is applied directly to the 16 bit static divider ’C’. (PC0 to
PC15)
=(R+1)⋅ fREF
f
OSC
PM0 PM1 Operating Mode
0 0 Standby
1 0 AM (swallow)
0 1 AM (direct)
11 FM
- Standby mode: in this mode all device functions are stopped. This allows low current
consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V,
and all data registers are set to EFH. The oscillatorkeeps running.
- FM and AM (SW) Swallow Mode (SW):
in this mode the FM or AM signal is applied to
a 32/33 prescaler, which is controlled by a 5
bit divider ’A’.The 5 bit register (PC0 to PC4)
controls this divider. In parallel the output of
the prescaler is connected to a 11 bit divider
’B’. (PC5 to PC15).
= (R+1)⋅ f
f
OSC
8/21
REF
Dividingrange:
f
=(C+1)⋅ f
VCO
REF
THREESTATE PHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
f
SYN
and f
. This phase error signal drives the
REF
chargepump current generator (fig. 3)
CHARGEPUMP CURRENT GENERATOR
This stage generates signed pulses of current.
The phase error signal decides the duration and
polarityof those pulses.
The current absolutevalues are programmableby
A0, A1, A2 registers for high current and B0, B1,
registersfor low current.
LOWNOISE CMOS OP-AMP
An internal voltage divider at pin VREF connects
the positive input of the low noise Op-Amp. The
charge pump output connects the negative input.
This internal amplifier in cooperationwith external
componentscan providean active filter.
Figure 3. Phase comparator waveforms
TDA7427
Figure 4. IF Counter internal block diagram
IFENA
IF-AM
IF-FM
OSC
3 BIT COUNTER14 BIT COUNTER
11-21 BIT COUNTER
CF-REGISTER
IFS-REGISTERIFC-REGISTER
EW-REGISTER
ZD
UP/DOWN COUNTER
DECODE SSTOP
D95AU377A
9/21
TDA7427
The negative input is switchable to three input
pins ( LPIN 1, LPIN 2 and LPIN 3) to increasethe
flexibility in application. This feature allows two
separateactive filters for differentapplications
A logical ”1” in the LPIN 1/2 register activates
pin LPIN 1, otherwise pin LPIN 2 is active. While
the high current mode is activated LPIN 3 is
switchedon.
INLOCK DETECTOR
The charge pump can be switchedin low current
mode either via software or automatically by the
inlock detector by setting bit LDENA to ”1”.
The charge pump is forced in low current mode
when a phase difference of 10-40 nsec is
reached.
A phase difference larger then the programmed
values will switch the charge pump immediately in
the high current mode.
Programmable delays are available for inlock detection.
IF COUN TER SYSTEM(AM/FM/AM- UPC MODES)
The if counter works in modescontrolled by IFCM
register(see table):
IFCM1 IFCM0 FUNCTION
0 0 NOT USED
0 1 FM MODE
1 0 AM MODE
11
10.7MHz AM UP
CONVERSION MODE
Typical input impedance for IF inputs is 4KΩ.
A sampletimer to generate the gate signal for the
main counter is build with a 14-bit programmable
counter to have the possibility to use any crystal
oscillator frequency. In FM mode 6.25KHz in AM
modea 1KHz signal is generated.This is followed
by an asynchronous divider to generate different
samplingtimes (see fig. 4).
IntermediateFrequencyMain Counter
This counter is a 11/21 bits synchronous autoreload down-counter. Four bits are programmable
to have the possibility for an adjust to the frequency of the CF filter. The counter length is
automatically adjusted to the chosen sampling
time and the countermode (AM, FM, AM-UPC).
At the start the counter will be loaded with a defined value which is an equivalent to the divider
value (t
sample
⋅ fIF).
If a correct frequency is applied to the IF counter
frequency inputs IF-AM IF-FM, at the end of the
sampling time the main counter is changing its
state from 0 H to 1FFFFFH.
This is detected by a control logic. The frequency
range inside which a successful count results is
detected is adjustable by bitsEW 0,1,2.
Adjustment of the Measurement Sequence
Time
The precision of the measurements is adjustable
by controllingthe discrimination window .
This is adjustable by programming the control
registersEW0...EW2.
The measurement time per cycle is adjustable by
setting the Register IFS0 - IFS2.
Adjust of the Frequency Value
The center frequency of the discrimination window is adjustable by the control register ”CF0” to
”CF4”.(see data byte specification).
PortExtension and additional functions
One digital open collector output and one digital
push-pull output are available in application
mode. This digital ports are controlledby the data
bits DOUT1 and DOUT3.
Figure 5. I2C Bus timing diagram
t
HIGH
SCL
t
SU-STA
SDA IN
SDA OUT
10/21
t
HD-STA
t
AA
t
R
t
HD-DAT
t
LOW
t
DH
t
R
t
SD-DAT
t
SUBTOP
t
txt
D95AU378
TDA7427
I2C BUS INTERFACE DESCRIPTION
The TDA7427 supports the I
2
C bus protocol. This
protocol defines any device that sends data into
the bus as a transmitter and the receiving device
as the receiver. The device that controls the
transfer is the master and the device being controlled is the slave. The master always initiates
data transfer and provides the clock to transmit or
receive operations.
Data Transition
Data transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as START or
STOP condition.
Start Condition
A start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any commandand initiate a data transferonto the
bus. The TDA7427 continuously monitors the
SDA and SCL lines for a valid START and will not
response to any command if this condition has
not been met.
Stop Condition
A STOP condition is defined by a LOW to HIGH
transitionof theSDA whilethe SCLline is at a stable
HIGH level .This conditionterminatethe communicationbetweenthedevicesandforcesthebusinterface
oftheTDA7427intotheinitialcondition.
Acknowledge
Indicatesa successfuldata transfer.The transmit-
ter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the
SDA line to LOW level to indicate it has receive
the eight bits of data correctly.
Data transfer
During data transfer the TDA7427 samples the
SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
DeviceAddressing
To start the communicationbetween two devices,
the bus master must initiate a start instructionsequence, followed by an eight bit word corresponding to the addressof the device it is addressing.
The most significant 6 bits of the slave address
are the device type identifier.
The TDA7427 frequency synthesizer device type
is fixed as ”110001”
The next significant bit is used to address a particular device of the previous defined type connected to the bus. The state of the hardwired A0
pin defines the state of this address bit. So up to
two devices could be connected on the same bus.
The last bit of the instruction defines the type of
operationto be performed:
- When set to ”1”, a readoperation is selected
-
Whenset to ”0”, a writeoperationis selected
The chip selection is accomplished by setting the
bit of the chip address to thecorrespondingstatus
of the A0 input.
All TDA7427 connected to the bus will compare
their own hardwired address with the slave ad-
Figure 6. Applicationwith two loop filters
+10V
VDD1
CONTROLLER
+5V
100nF
100nF
D95AU379B
10µF 100nF
VDD2
SCL
SDA
VDD1
10µF
VREF
OSCIN OSCOUT
19
8
9
15
4
56
10
4MHz
AM-FM
IF
10nF 10nF
IF_FM
IF_AM
11
TDA7427
10nF
FM VCO
AM VCO
10nF1nF
3.9K 100nF
AM_INFM_IN
16
17
714
20
1
2
3
13
12
DOUT3HFREF
LPOUT
LP_FM
LP_HC
LP_AM
INLOCK/DOUT1
SSTOP
1nF
27K
15K
100K
6.8nF
820Ω
U
tun
6.8nF
68nF
3.3nF
FM:50KHz
AM:1KHz
11/21
TDA7427
dress being transmitted.
After this comparison, the TDA7427 will generate
an ”acknowledge” on the SDA line and will perform either a read or write operationaccording to
the state of R/Wbit.
Write Operation
Following a START condition the master sends a
slave address word with the R/W bit set to ”0”.
The TDA7427 will ”acknowledge” after this first
transmission and wait for a second word (the
word addressfield).
This 8 bit address field provides an accessto any
of the 8 internal addresses. Upon receipt of the
word address the TDA7427 slave device will respond with an ”acknowledge”. At this time, all the
CHIP ADDRESS SUBADDRESS DATA 1 to DATA n
MSB LSB MSB LSB MSB LSB
S1100010R/W
ACK T T T I A3 A2 A1 A0 ACK DATA ACK P
following words transmitted to the TDA7427 will
be considered as Data. The internal address will
be automaticallyincremented.After each word receipt the TDA7427 will answer with an ”acknowledge”.
SOFTWARE SPECIFICATION
2
C Protocol
I
The interface protocol comprises:
A startcondition (s)
A chip address byte (the LSB determines
read/writetransmission)
A sub-addressbyte.
A sequenceof data (N-bytes + acknowledge)
A stopcondition (P)
ACK = Acknowledge
S = Start
P = Stop
I = AutoIncrement
T = used for testing (in applicationmode they have to be ” 0”)
MAX CLOCK SPEED 400kbits/s
CHIP ADDRESS
MSB LSB
11000100
SUBADDRESS
MSB LSB FUNCTION
T3 T2 T1 I A3 A2 A1 A0
0000Charge pump control
0001PLLcounter 1 (LSB)
0010PLLcounter 2 (MSB)
0011PLLreference counter 1 (LSB)
0100PLLreference counter 2 (MSB)
0101PLLlockdetector control and PLL modeselect
0110IFCreference counter 1 (LSB)
0111IFCreferencecounter2(MSB)andIFCmode select
1000IFcounter control 1
1001IFcounter control 2
1010Oscillator adjust
1011Port extension
0 page mode off
1 page mode enabled
T1, T2, T3 used for testing, in application mode they have to be”0”
12/21
TDA7427
Data Byte Specification
CHARGEPUMP CONTROL
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 High current = 0mA
0 0 0 1 High current = 0.5mA
0 0 1 0 High current = 1.0mA
0 0 1 1 High current = 1.5mA
0 1 0 0 High current = 2.0mA
0 1 0 1 High current = 2.5mA
0 1 1 0 High current = 3.0mA
0 1 1 1 High current = 3.5mA
1 0 0 0 High current = 4.0mA
1 0 0 1 High current = 4.5mA
1 0 1 0 High current = 5.0mA
1 0 1 1 High current = 5.5mA
1 1 0 0 High current = 6.0mA
1 1 0 1 High current = 6.5mA
1 1 1 0 High current = 7.0mA
1 1 1 1 High current = 7.5mA
0 0 Low current = 0µA
0 1 Low current = 50µA
1 0 Low current = 100µA
1 1 Low current = 150µA
0 Select low Current
1 Select high Current
1 Select loop filter LP_FM
0 Select loop filter LP_AM
LPIN1/2 CURRH B1 B0 A3 A2 A1 A0 Subaddress = 00H
PLL COUNTER1 (LSB)
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000LSB=0
00000001LSB=1
00000010LSB=2
11111100LSB=252
11111101LSB=253
11111110LSB=254
11111111LSB=255
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Bit name Subaddress = 01H
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TDA7427
PLL COUNTER2 (MSB)
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000MSB=0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512
1 1 1 1 1 1 0 0 MSB = 64768
1 1 1 1 1 1 0 1 MSB = 65024
1 1 1 1 1 1 1 0 MSB = 65280
1 1 1 1 1 1 1 1 MSB = 65536
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 Bit name Subddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32
Direct mode: fvco/fsyn = LSB + MSB + 1
PLL REFERENCECOUNTER1 (LSB)
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000LSB=0
00000001LSB=1
00000010LSB=2
1 1 1 1 1 1 0 0 LSB = 252
1 1 1 1 1 1 0 1 LSB = 253
1 1 1 1 1 1 1 0 LSB = 254
1 1 1 1 1 1 1 1 LSB = 255
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 Bitname Subaddress =03H
PLL REFERENCECOUNTER2 (MSB)
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000MSB=0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512
1 1 1 1 1 1 0 0 MSB = 64768
1 1 1 1 1 1 0 1 MSB = 65024
1 1 1 1 1 1 1 0 MSB = 65280
1 1 1 1 1 1 1 1 MSB = 65536
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Bit name Subddress = 04H
f
= LSB + MSB + 1
OSC/fREF
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TDA7427
LOCK DETECTOR& PLL MODE CONTROL
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 PLL standby mode
0 1 PLL AM swallow mode
1 0 PLL AM direct mode
1 1 PLL FM mode
0 0 PD phase difference threshold 10ns
0 1 PD phase difference threshold 20ns
1 0 PD phase difference threshold 30ns
1 1 PD phase difference threshold 40ns
0 0 Not used in application mode
0 1 Activation delay = 4⋅fref
1 0 Activation delay = 6⋅fref
1 1 Activation delay = 8 ⋅ fref
0 Digital output 1 at pin ”dout1/inlock”
1 Inlock information at pin ”dout1/inlock”
0 No lock detector controlled chargepump
1 Lock detector controlledchargepump
LDENA INLOCK D3 D2 D1 D0 PM1 PM0 Bit name Subaddress = 05H
IF COUNTERREFERENCE CONTROL1 (LSB)
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000LSB=0
00000001LSB=1
00000010LSB=2
11111100LSB=252
11111101LSB=253
11111110LSB=254
11111111LSB=255
IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRC0 Bit name Subaddress = 06H
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TDA7427
IF COUNTERREFERENCE CONTROL2 (MSB)AND IF COUNTERMODE SELECT
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000000MSB=0
0 0 0 0 0 0 0 1 MSB = 256
0 0 0 0 0 0 1 0 MSB = 512
1 1 1 1 0 1 MSB = 15616
1 1 1 1 1 0 MSB = 15872
1 1 1 1 1 1 MSB = 16128
0 0 NOT USED IN APPLICATION MODE
0 1 IF counter FM mode
1 0 IF counter AM mode
1 1 IF counter AM 10.7MHz upconversion mode
IFCM1 IFCM0 IRC13 IRC12 IRC11 IRC10 IRC9 IRC8 Bitname Subaddress= 07H
fosc/ftim = LSB + MSB + 1
IF COUNTERCONTROL 1
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 don’t use
0 0 1 don’t use
011EWdeltaf=
100EWdeltaf=±12.5kHz (FM); ±2kHz(AM;AM-UPC)
1 0 1 EW deltaf = ±25kHz(FM); ±4kHz(AM; AM-UPC)
1 1 0 EW deltaf = ±50Hz (FM); ±8kHz (AM; AM-UPC)
111
X X X X don’t use
0 IF counter disabled / stand by
1 IF counter enabled
FENA FR3 FR2 FR1 FR0 EW2 EW1 EW0 Bit name Subaddress = 08H
EW delta f =±100kHz (FM);±16kHz (AM; AMUPC)
6.25kHz (FM);±1kHz(AM; AM-UPC)
±
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TDA7427
IF COUNTERCONTROL 2
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
00000fcenter = 10.60000MHz (FM) 448KHz (AM) 10.688MHz (AM UPC)
00001fcenter = 10.60625MHz (FM) 449KHz (AM) 10.689MHz (AM UPC)
00010fcenter = 10.61250MHz (FM) 450KHz (AM) 10.690MHz (AM UPC)
00011fcenter = 10.61875MHz (FM) 451KHz (AM) 10.691MHz (AM UPC)
00100fcenter = 10.62500MHz (FM) 452KHz (AM) 10.692MHz (AM UPC)
00101fcenter = 10.63125MHz (FM) 453KHz (AM) 10.693MHz (AM UPC)
00110fcenter = 10.63750MHz (FM) 454KHz (AM) 10.694MHz (AM UPC)
00111fcenter = 10.64375MHz (FM) 455KHz (AM) 10.695MHz (AM UPC)
01000fcenter = 10.65000MHz (FM) 456KHz (AM) 10.696MHz (AM UPC)
01001fcenter = 10.65625MHz (FM) 457KHz (AM) 10.697MHz (AM UPC)
01010fcenter = 10.66250MHz (FM) 458KHz (AM) 10.698MHz (AM UPC)
01011fcenter = 10.66875MHz (FM) 459KHz (AM) 10.699MHz (AM UPC)
01100fcenter = 10.67500MHz (FM) 460KHz (AM) 10.700MHz (AM UPC)
01101fcenter = 10.68125MHz (FM) 461KHz (AM) 10.701MHz (AM UPC)
01110fcenter = 10.68750MHz (FM) 462KHz (AM) 10.702MHz (AM UPC)
01111fcenter = 10.69375MHz (FM) 463KHz (AM) 10.703MHz (AM UPC)
10000fcenter = 10.70000MHz (FM) 464KHz (AM) 10.704MHz (AM UPC)
10001fcenter = 10.70625MHz (FM) 465KHz (AM) 10.705MHz (AM UPC)
10010fcenter = 10.71250MHz (FM) 466KHz (AM) 10.706MHz (AM UPC)
10011fcenter = 10.71875MHz (FM) 467KHz (AM) 10.707MHz (AM UPC)
10100fcenter = 10.72500MHz (FM) 468KHz (AM) 10.708MHz (AM UPC)
10101fcenter = 10.73125MHz (FM) 469KHz (AM) 10.709MHz (AM UPC)
10110fcenter = 10.73750MHz (FM) 470KHz (AM) 10.710MHz (AM UPC)
10111fcenter = 10.74375MHz (FM) 471KHz (AM) 10.711MHz (AM UPC)
11000fcenter = 10.75000MHz (FM) 472KHz (AM) 10.712MHz (AM UPC)
11001fcenter = 10.75625MHz (FM) 473KHz (AM) 10.713MHz (AM UPC)
11010fcenter = 10.76250MHz (FM) 474KHz (AM) 10.714MHz (AM UPC)
11011fcenter = 10.76875MHz (FM) 475KHz (AM) 10.715MHz (AM UPC)
11100fcenter = 10.77500MHz (FM) 476KHz (AM) 10.716MHz (AM UPC)
11101fcenter = 10.78125MHz (FM) 477KHz (AM) 10.717MHz (AM UPC)
11110fcenter = 10.78750MHz (FM) 478KHz (AM) 10.718MHz (AM UPC)
11111fcenter = 10.79375MHz (FM) 479KHz (AM) 10.719MHz (AM UPC)
1 1 1 tsample = 160µs (FM mode); 1ms (AM; AM-UPC)
1 1 0 tsample = 320µs (FM mode); 2ms (AM; AM-UPC)
1 0 1 tsample = 640µs (FM mode); 4ms (AM; AM-UPC)
1 0 0 tsample = 1.280ms (FM mode); 8ms (AM; AM-UPC)
0 1 1 tsample = 2.560ms (FM mode); 16ms (AM; AM-UPC)
0 1 0 tsample = 5.120ms (FM mode); 32ms (AM; AM-UPC)
0 0 1 tsample = 10.240ms (FM mode); 64ms (AM; AM-UPC)
0 0 0 tsample = 20.480ms (FM mode); 128ms (AM; AM-UPC)
IFS2 IFS1 IFS0 CF4 CF3 CF2 CF1 CF0 bit same Subaddress = 09H
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TDA7427
OSCILLATORADJUST
MSB LSB FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 Cload 1,2 = 3pF
X X X 0 0 0 0 1 Cload 1,2 = 4.25pF
X X X 0 0 0 1 0 Cload 1,2 = 5.5pF
X X X 0 0 0 1 1 Cload 1,2 = 6.75pF
X X X 0 0 1 0 0 Cload 1,2 = 8pF
X X X 0 0 1 0 1 Cload 1,2 = 9.25pF
X X X 0 0 1 1 0 Cload 1,2 = 10.5pF
X X X 0 0 1 1 1 Cload 1,2 = 11.75pF
X X X 0 1 0 0 0 Cload 1,2 = 13pF
X X X 0 1 0 0 1 Cload 1,2 = 14.25pF
X X X 0 1 0 1 0 Cload 1,2 = 15.5pF
X X X 0 1 0 1 1 Cload 1,2 = 16.75pF
X X X 0 1 1 0 0 Cload 1,2 = 18pF
X X X 0 1 1 0 1 Cload 1,2 = 19.25pF
X X X 0 1 1 1 0 Cload 1,2 = 20.5pF
X X X 0 1 1 1 1 Cload 1,2 = 21.75pF
X X X 1 0 0 0 0 Cload 1,2 = 23pF
X X X 1 0 0 0 1 Cload 1,2 = 24.25pF
X X X 1 0 0 1 0 Cload 1,2 = 25.5pF
X X X 1 0 0 1 1 Cload 1,2 = 26.75pF
X X X 1 0 1 0 0 Cload 1,2 = 28pF
X X X 1 0 1 0 1 Cload 1,2 = 29.25pF
X X X 1 0 1 1 0 Cload 1,2 = 30.5pF
X X X 1 0 1 1 1 Cload 1,2 = 31.75pF
X X X 1 1 0 0 0 Cload 1,2 = 33pF
X X X 1 1 0 0 1 Cload 1,2 = 34.25pF
X X X 1 1 0 1 0 Cload 1,2 = 35.5pF
X X X 1 1 0 1 1 Cload 1,2 = 36.75pF
X X X 1 1 1 0 0 Cload 1,2 = 38pF
X X X 1 1 1 0 1 Cload 1,2 = 39.25pF
X X X 1 1 1 1 0 Cload 1,2 = 40.5pF
X X X 1 1 1 1 1 Cload 1,2 = 41.75pF
- - - OSC4 OSC3 OSC2 OSC1 OSC0 Bit name Subaddress = 0AH
PORT EXTENSIONCONTROL
MSB LSB FUNCTION
D7 D6 D2 D0
0 CMOS push-pull DOUT1 low
1 CMOS push-pull DOUT1 high
0 NPN opencollector DOUT3 inactive
1 NPN opencollector DOUT3 active
0 0 always ”0” in application mode
- - DOUT3 DOUT1 Bit name Subaddress = 0BH
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TDA7427
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.254 0.010
B 1.39 1.65 0.055 0.065
b 0.45 0.018
b1 0.25 0.010
D 25.4 1.000
E 8.5 0.335
e 2.54 0.100
e3 22.86 0.900
F 7.1 0.280
I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053
mm inch
OUTLINE AND
MECHANICAL DATA
DIP20
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TDA7427
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.1 0.3 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009
D 12.6 13 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
K0°(min.)8°(max.)
mm inch
0.013
OUTLINE AND
MECHANICAL DATA
SO20
B
e
D
1120
110
L
hx45°
A
K
A1
C
H
E
SO20MEC
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TDA7427
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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